JPS62117198A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS62117198A
JPS62117198A JP60258376A JP25837685A JPS62117198A JP S62117198 A JPS62117198 A JP S62117198A JP 60258376 A JP60258376 A JP 60258376A JP 25837685 A JP25837685 A JP 25837685A JP S62117198 A JPS62117198 A JP S62117198A
Authority
JP
Japan
Prior art keywords
output
circuit
constitution
parity bit
corrected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60258376A
Other languages
Japanese (ja)
Inventor
Masao Taguchi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60258376A priority Critical patent/JPS62117198A/en
Publication of JPS62117198A publication Critical patent/JPS62117198A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Abstract

PURPOSE:To prevent a cycle time from extending even in a DRAM with an ECC circuit by selecting either of the output of a circuit which performs an error detection and correction and that of an encoder adding them, and outputting it to a write amplifier. CONSTITUTION:A parity bit is also corrected with the output of a decoder DEC, and a correct read out output of twelve bits can be obtained. A constitution in such a way makes unnecessary the generation of the parity bit at an encoder ENC, and after a data has been read out, or when a corrected data is written in a refresh operation, the output of an error correction circuit EC can be directly written on a memory cell through as selector SEL and write amplifiers WA1-WA12.
JP60258376A 1985-11-18 1985-11-18 Semiconductor memory device Pending JPS62117198A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60258376A JPS62117198A (en) 1985-11-18 1985-11-18 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60258376A JPS62117198A (en) 1985-11-18 1985-11-18 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS62117198A true JPS62117198A (en) 1987-05-28

Family

ID=17319383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60258376A Pending JPS62117198A (en) 1985-11-18 1985-11-18 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS62117198A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005017914A1 (en) * 2003-08-18 2005-02-24 Fujitsu Limited Semiconductor memory and operation method of semiconductor memory
US7458004B2 (en) 2004-04-12 2008-11-25 Nec Electronics Corporation Semiconductor storage device
US7692943B2 (en) 2002-12-27 2010-04-06 Renesas Technology Corp. Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7692943B2 (en) 2002-12-27 2010-04-06 Renesas Technology Corp. Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells
WO2005017914A1 (en) * 2003-08-18 2005-02-24 Fujitsu Limited Semiconductor memory and operation method of semiconductor memory
US7458004B2 (en) 2004-04-12 2008-11-25 Nec Electronics Corporation Semiconductor storage device

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