JP2003059290A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory having a preferable relieving mode for defective data. SOLUTION: This semiconductor memory is provided with a cell array provided with a normal data section used for normal write-in and read-out of data and a parity data section storing data for test for performing error detection of read-out data from the normal data section, a data buffer holding temporarily read-out data from the cell array and write-in data for the cell array, and an error detecting and correcting circuit generating data for test to be stored in the parity data section from write-in data inputted at write-in of data and performing error detection and correction of read out data based on data read out from the normal data section and data for test read out from the parity data section at read-out of data. (n) bits parallel data is delivered and received between the data buffer and the normal data section of the cell array, and (m) bits parallel data (m<n) is delivered and received between the data buffer and an external input/output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of relieving a data defect due to power saving.

[0002]

2. Description of the Related Art With the miniaturization, large capacity, and power saving of semiconductor memories, it is difficult to secure reliability in terms of process and transistor characteristics of memory cells having a particularly fine structure among semiconductor memories. . In the SRAM of the semiconductor memory, it is difficult to reduce the size and increase the capacity because the memory cell is composed of a plurality of transistors (six transistors of full CMOS type). In contrast, DR
Since the AM memory cell is composed of one transistor and one capacitor, it is suitable for miniaturization and large capacity.

Considering these characteristics of SRAM and DRAM, for example, in conventional portable electronic equipment and the like, conventional SR
Part of the memory system that was configured using AM
Pseudo SRAM (Pseudo-SR) using RAM cells
It is considered to replace the AM; PSRAM) to achieve miniaturization. Normally, DRAM multiplexes row and column addresses, whereas SRAM does not perform address multiplexing. Therefore, if the SRAM interface is used as is, PSRAM
Will be used without address multiplexing. Further, since the DRAM requires a data refresh operation, it is necessary to incorporate an automatic refresh circuit inside the PSRAM as well.

[0004]

As described above, the PSR is
Since the AM uses DRAM cells, the data holding current is larger than that of the SRAM, but it is suitable for downsizing and large capacity of the system. However, if further power saving is attempted, the data retention characteristic of the memory cell deteriorates, and even if the automatic refresh circuit is built in, the generation of defective data becomes a problem due to the deterioration of the data retention characteristic. The deterioration of the data retention characteristic due to the power saving is not peculiar to the PSRAM, but is a problem in the ordinary DRAM and further in the EEPROM as well.

It is an object of the present invention to provide a semiconductor memory device having a preferable data defect relief mode.

[0006]

A semiconductor memory device according to the present invention includes a normal data section used for normal data writing and reading, and inspection data for detecting an error in read data from the normal data section. A cell array having a parity data section for storing, a data buffer for temporarily holding read data from the cell array and write data to the cell array, and an inspection to be stored in the parity data section from input write data at the time of data writing Error correction circuit for generating error data and performing error detection and correction of the read data based on the data read from the normal data part and the inspection data read from the parity data part when the data is read The data buffer and the cell array Between the normal data area is performed the transfer of n-bit parallel data, between the data buffer and the external input and output terminals m-bit parallel data (where, m <n)
In the first half of the data write cycle, n-bit data including m-bit data to be rewritten is read in parallel, and the error detection and correction circuit performs error detection and correction of the n-bit data. In the latter half of the data write cycle, the m-bit data portion to be rewritten of the n-bit parallel data corrected by the error detection / correction circuit is replaced with the m-bit parallel data supplied from the external input / output terminal, It is characterized by being transferred to the normal data section.

The error detection / correction circuit, for example, performs a single-bit error correction using a Hamming code.
The inspection data stored in the parity data section is composed of the minimum number of bits required for error detection and correction of read data. More preferably, the inspection data stored in the parity data section is configured by a bit number that is one bit larger than the minimum bit number required for error detection and correction of read data.

The error detection / correction circuit does not perform error correction when there is an error in the m-bit data portion to be rewritten, and does error correction when there is an error in a portion other than the m-bit data portion to be rewritten. Further, in the data read cycle, the error detection / correction circuit does not correct the corresponding cell data in the normal data portion even if the read data is error-corrected. Further, when the cell array is a DRAM cell array in which data is refreshed at a predetermined cycle, the error detection / correction circuit, during the refresh operation of the DRAM cell array,
It shall stop operating.

The semiconductor memory device according to the present invention also includes
A cell array including a normal data section used for normal data writing and reading and a parity data section for storing inspection data for detecting an error in the read data from the normal data section, read data from the cell array, and A data buffer for temporarily holding write data to the cell array, and test data to be stored in the parity data section from write data input at the time of data write, and data read from the normal data section at the time of data read And a syndrome generation circuit for generating a syndrome signal based on the read data and the inspection data, for performing error detection and correction of the read data based on the inspection data read from the parity data section And the generated syndrome signal An error detection / correction circuit having a syndrome decoding / error correction circuit for decoding and correcting an error bit, a timing signal generation circuit for detecting a change in output data in the data buffer and generating a timing signal, and the timing signal generation And a correction timing adjusting circuit which transfers the syndrome signal to the syndrome decoding / error correcting circuit under the control of the timing signal generated by the circuit.

Also in this case, n-bit parallel data is exchanged between the data buffer and the normal data part of the cell array, and m-bit parallel data (where m <n) is exchanged between the data buffer and the external input / output terminal. In the first half of the data write cycle, n-bit data including m-bit data to be rewritten is read in parallel, and the error detection / correction circuit performs error detection / correction on the n-bit data. In the latter half of the data write cycle, the m-bit data portion to be rewritten of the n-bit parallel data corrected by the error detection / correction circuit is replaced with the m-bit parallel data supplied from the external input / output terminal to become the normal data portion. Shall be transferred.

It is preferable that the error detection / correction circuit is configured to be able to switch between the active and inactive states by externally controlling the active and inactive states of the timing signal generating circuit. Further, it is preferable to provide a monitor terminal for outputting the output of the correction timing adjustment circuit as a monitor signal for notifying the presence / absence of error correction to the outside.

The semiconductor memory device according to the present invention further includes
A cell array including a normal data section used for normal data writing and reading and a parity data section for storing inspection data for detecting an error in the read data from the normal data section, read data from the cell array, and A data buffer for temporarily holding write data to the cell array, and test data to be stored in the parity data section from write data input at the time of data write, and data read from the normal data section at the time of data read And an error detection / correction circuit that performs error detection / correction of the read data based on the inspection data read from the parity data section, wherein the error detection / correction circuit is configured to detect the read data and the inspection data. A syndrome signal based on the training data A syndrome generation circuit and a syndrome decode / error correction circuit having a built-in syndrome decode circuit that decodes the generated syndrome signal to correct error bits. A first NAND gate for detecting the combination of
A NOR gate for detecting a combination of "0" data, and a second NAND gate for performing coincidence detection of the inverted signal of the output of the first NAND gate and the output of the NOR gate are provided. .

The semiconductor memory device according to the present invention further includes
A cell array including a normal data section used for normal data writing and reading and a parity data section for storing inspection data for detecting an error in the read data from the normal data section, read data from the cell array, and A data buffer for temporarily holding write data to the cell array, and test data to be stored in the parity data section from write data input at the time of data write, and data read from the normal data section at the time of data read And an error detection / correction circuit that performs error detection / correction of the read data based on the inspection data read from the parity data section, wherein the error detection / correction circuit is configured to detect the read data and the inspection data. A syndrome signal based on the training data A syndrome generation circuit and a syndrome decode / error correction circuit having a built-in syndrome decode circuit that decodes the generated syndrome signal to correct error bits. It is characterized by being configured by a NAND gate array in which NAND gates for detecting the combination of are combined.

The semiconductor memory device according to the present invention further includes
A cell array including a normal data section used for normal data writing and reading and a parity data section for storing inspection data for detecting an error in the read data from the normal data section, read data from the cell array, and A data buffer for temporarily holding write data to the cell array, and test data to be stored in the parity data section from write data input at the time of data write, and data read from the normal data section at the time of data read And an error detection / correction circuit for performing error detection / correction of the data read based on the inspection data read from the parity data section, wherein the error detection / correction circuit corrects a single bit error by a Hamming code. And the parity data Inspection data stored in the data unit,
It is characterized in that the number of bits is one more than the minimum number of bits required for 1-bit error correction.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic configuration of a semiconductor memory according to an embodiment of the present invention. This semiconductor memory is a PSRAM configured using DRAM cells. In this embodiment, in order to relieve a data defect in the cell array 1, an error check of read data is performed between the cell array 1 and the I / O buffer 6, and an error checking and correction (error checking and c
orrecting (ECC) circuit 7 is interposed. The ECC circuit 7 performs single-bit error detection and correction using a Hamming-Code.

The DRAM cell array 1 includes a normal data portion 1a for storing normal data and inspection data for ECC, specifically, parity data for storing parity data for determining odd / even of syndrome. And part 1b. The word lines WL selectively driven by the row decoder / word line driver 2 are arranged so as to be continuous from the normal data portion 1a to the parity data portion 1b, and DRAM cells are provided at the intersections of the word lines WL and the bit lines BL. MC is provided.

A sense amplifier 3 is connected to the bit line BL of the cell array 1. The bit line BL is selected by the column gate 4 and data transfer is performed with the data line DQ. A DQ buffer 5 is provided on the data line DQ, and E is provided between the DQ buffer 5 and the I / O buffer 6.
The CC circuit 7 is arranged.

The ECC circuit 7 includes a DQ buffer 5 and an I / O.
It has a read / write driver 71 that relays read / write data between the buffers 6. The ECC circuit 7 also includes a check bit generation circuit 73 that generates check data for writing in the parity data section 1b based on the write data WD supplied from the I / O terminal. Single-bit error correction (Single-Error-Co
redirection), the check bit generation circuit 73 determines the code length N + M from the data bit N bits.
The M-bit check data is generated so as to generate the correctable codeword (Hamming code). Specifically, a Hamming code word is a vector V, and a check matrix H that is a binary matrix of M digits is used to generate check data so that HV ^T = 0 is satisfied.

The ECC circuit 7 also includes a parity data section 1
A syndrome generation circuit 75 that generates a syndrome signal based on the inspection data PRWD read from b and the data RD read from the normal data section 1a.
Have. The information bit generation circuit 74 is composed of an exclusive OR gate array, and generates M bits of information bits used for syndrome generation based on the read data RD and predetermined check matrix data.
This is sent to the syndrome generation circuit 75. The syndrome generation circuit 75 is composed of an exclusive OR gate array, and has M bits of information bits and M bits of inspection data PRW generated by the information bit generation circuit 74.
Input D to generate an M-bit syndrome signal.

A syndrome decode / error correction circuit 72 is provided in the read / write driver 71. In the syndrome decoding / error correction circuit 72, the syndrome signal generated by the syndrome generation circuit 75 is decoded to detect an error, and the error bit is corrected. The syndrome decode circuit is a NAND / NOR gate array or NAND for detecting a column corresponding to an error bit in a check matrix in which the syndrome signal S (= HV ^T ) is not “0”.
It is composed of a gate array.

In FIG. 1, the read data RD and the write data WD are shown as if they are transferred on different data lines, but in reality, they are transferred on the same data bus at different timings. The same applies to the I / O data between the read / write driver 71 and the I / O buffer 6. The same applies to the following embodiments.

The operation of the semiconductor memory configured as above will be described. When reading data, the ECC circuit 7 uses the data RD read from the normal data portion 1a and the inspection data PR read from the parity data portion 1b.
The syndrome generation circuit 75 compares WD with the syndrome generation circuit 75 to generate a syndrome signal. By decoding the syndrome signal, "0" is output at an address having no error in the Hamming code check matrix, and "1" is output at an address where an error occurs. In the read / write driver 71, the syndrome decoding / correction circuit 72 decodes the syndrome signal to detect an error, inverts the bit data of the address where the error is detected, and outputs the corrected data to the outside.

At the time of writing data, the inspection data is generated in the ECC circuit 7 from the write data WD from the outside. Then, the write data WD is simultaneously written in the normal data portion 1a, and the generated inspection data is simultaneously written in the parity data portion 1b.

As described above, by incorporating the ECC circuit, even if the data holding characteristic of the memory cell array 1 is deteriorated to some extent by power saving, it is possible to read correct data corrected based on the inspection data. Become.
Although not shown in the figure, by using together with a redundant circuit system for replacing defective cells, high relief efficiency can be obtained when various cell defects are included. The redundant circuit system cannot deal with a cell defect after packaging, but the ECC circuit can deal with this.

As in the following embodiments, the ECC circuit outputs the correct data externally even if there is an error in the cell data when reading the data. The corresponding cell data is not corrected. Further, the ECC circuit 7 can also detect an error bit of the inspection data of the parity data portion 1b in the case of 1-bit error correction using the Hamming code. However, the presence of error bits in the parity data part 1b means that the data in the normal data part 1a is correct. Therefore, it is not necessary to correct the data in the parity data section 1b.

FIG. 2 shows a more specific configuration example of the ECC circuit 7 in FIG. Here, a case where n-bit parallel data is transferred between the data buffer 5 and the cell array 1 and m-bit parallel data is transferred between the data buffer 5 and the I / O terminal is dealt with. However, m,
n is a positive integer (preferably a power of 2),
m <n. Specifically, in FIG. 2, m = 16, n = 64
Shows an example of.

Normal data section 1 of memory cell array 1
The parallel read / write data of a is n = 64 bit data. Further, the ECC circuit 7 is assumed to perform 1-bit error correction using a Hamming code. Generally, for n data bits, the number of check bits k required for 1-bit error correction is represented by 2 ^k ≧ n + k + 1. The minimum inspection bit number k required for 1-bit error detection and correction of n = 64-bit data is k = 7.
Therefore, the parity data unit 1b is accessed simultaneously with the 64-bit parallel data area, and the 7-bit inspection data is read / written.

The ECC circuit 7 reads 64-bit data of the normal data section 1a at the time of data reading, and at the same time, reads 7-bit test data from the parity data section 1b. A syndrome calculation circuit 75 performs a syndrome calculation based on these data to generate a 7-bit syndrome signal. The syndrome signal is transferred to the read / write driver 71 and decoded.
As a result, a 1-bit error is detected and corrected.

The number of I / O terminals is m = 16. That is,
The ECC circuit 7 transmits / receives 64-bit parallel data to / from the cell array 1 via the data buffer 5.
16-bit parallel data is transferred between the C circuit 7 and the I / O buffer 6 (hence the I / O terminal). This assumes a page mode, and the 64-bit data read by the ECC circuit 7 can be serially read in 16-bit units outside.

In this embodiment, the data write cycle is divided into the first half and the second half. That is, data writing is performed in 16-bit units from the external terminal,
In the first half of the write cycle, the normal data section 1
64-bit data including 16-bit data to be rewritten of a is first read in parallel. The ECC circuit 7 performs error detection and correction on this read data. Then, in the latter half of the write cycle, one of the 64-bit data error-corrected in the ECC circuit 7
6 bits are replaced with 16 bits write data supplied from the outside in the read / write driver 71. The 64-bit data thus partially overwritten is transferred to and written in the normal data section 1a. At the same time, inspection data is generated based on the partially overwritten 64-bit write data, and this is written in the parity data unit 1b.

As described above, when 16 bits of the read data of 64 bits in parallel are overwritten by the external data, it is not necessary to perform error correction on the overwritten portion. Therefore, when the error bit position of the 64-bit data is detected, it is determined whether or not it is within the address of the write data. If the error bit position is within the address of the write data, error correction is not performed. Since the normal write address is held inside the chip during the write cycle, such address determination can be performed. Then, only when the error bit is not the same address as the 16-bit data supplied from the outside, the error bit portion is corrected by the correction circuit 72, and the remaining portion is rewritten by the external data. Write in parallel.

The function of the ECC circuit 7 is to perform error detection and correction even if there is an error in the read data and output it as correct data to the outside. When new data is written, the ECC circuit 7 generates test data based on the written data and rewrites the parity data part 1b. Therefore, if data is transferred between the normal cell section 1a and the read / write driver 71, and the read / write driver 7 is used.
If data transfer between 1 and the external terminal is performed with the same number of bits, it is not necessary to perform error detection and correction in the write cycle. Even if the data held in the address to be written in the normal data portion 1a has an error, the write data overwrites the erroneous data portion and rewrites it to correct data, and also the inspection data in the parity data portion 1b. This is because it will be updated.

However, the memory chip is equipped with a page mode and the like, and data is exchanged with external terminals in units of 16 bits, but this is a problem when 64 bits are accessed in parallel inside the chip. In such a mode, (64-16) bits other than the rewritten 16 bits are normally rewritten while being read inside the chip. This is because erroneous bit data is rewritten as it is. Therefore, as described above, the error detection and correction of the read data is performed in the first half of the write cycle, so that it is possible to prevent the situation where erroneous data is rewritten as it is. When the ECC circuit 7 is a one-bit error correction type, by performing such data writing, the ECC circuit function can be made highly reliable.

FIG. 3 shows another configuration example of the ECC circuit 7 of FIG. The memory cell array 1 has a normal data section 1a.
Is 64 bits, and the parity data portion 1b is 8 bits, which is one bit larger than that in the case of FIG. The ECC circuit 7 is for single-bit error correction using a Hamming code.

The ECC circuit 7 reads 64-bit data of the normal data section 1a at the time of data reading, and at the same time, reads 8-bit test data from the parity data section 1b. A syndrome calculation circuit 75 performs a syndrome calculation based on these data to generate an 8-bit syndrome signal. The syndrome signal is transferred to the read / write driver 71 and decoded.
As a result, a 1-bit error is detected and corrected.

Also in this embodiment, the data write cycle is divided into the first half and the second half as in the embodiment of FIG. That is, the data writing is performed in units of 16 bits, but in the first half of the writing cycle, the 64-bit data of the normal data portion 1a including the write address is read to the ECC circuit 7 via the DQ buffer 5 to perform error detection and correction. To do. In the latter half, 16 out of the 1-bit corrected 64-bit data
The bit portion is replaced with 16-bit data supplied from the outside in the read / write driver 71, and writing to the normal data portion 1a and the parity data portion 1b is performed.

As a result, the same effect as the embodiment of FIG. 2 can be obtained. Further, according to this embodiment, by making the inspection data 8 bits, the variation of the configuration of the syndrome decoding circuit for decoding the syndrome signal and detecting the correction address of the inspection matrix increases. This will be specifically described in comparison with the case of FIG. As in the embodiment of FIG. 2, when the check data is 7 bits, a combination of 3 bits “1” and 4 bits “0” is set in each 7-bit column forming the check matrix of the Hamming code. I will use it. At this time, there are a maximum of 35 combinations. Also, there are a maximum of 35 combinations in which 4 bits are "1" and 3 bits are "0". Therefore, if the check bits are 7 bits, it is impossible to form a check matrix in which all the 64 data bits are linearly independent.

On the other hand, if the inspection data is 8 bits as in the embodiment of FIG. 3, there are a maximum of 70 combinations of 4 bits "1" and 4 bits "0". Therefore, it is possible to form a check matrix in which all 64 bits are linearly independent. Further, in this case, the syndrome decoding circuit can be configured by a gate array that detects a 4-bit "1" or "0" data pattern. Therefore, the pattern layout is also advantageous.

When 7-bit check data is used as in the embodiment of FIG. 2, the check matrix and code of the Hamming code are given by 7-digit binary numbers other than 0. At this time, the syndrome signal is for obtaining the address of the 1-bit error in the check matrix, but the preferred configuration of the syndrome decoding circuit is the NOR / NAND configuration as shown in FIG. This is 7 when an error of 2 bits or more occurs.
A syndrome in which all bits are “1” may be generated, and at this time, the syndrome is “1” or “0”.
This is because a circuit that detects and decodes only the correct data may rewrite a plurality of correct data.

That is, the syndrome decoder has a 3-input NAND gate G1 for detecting that all the "1" bits of the 7-digit syndrome signal are "1".
A 4-input NOR gate G2 for detecting that all the bits of "0" are "0" is additionally provided. NA
A NAND gate G4 for inverting the output of the ND gate G1 by an inverter gate G3 and detecting that both the output of this and the output of the NOR gate G2 are "1" is arranged. This is specifically for a data bit in which the syndrome is composed of a combination of 3-bit "1" and 4-bit "0". As described above, when the check bits are 7 bits, it is not possible to make all 64 bits a primary independent check matrix, and in order to construct a decoder for 64 bits, the NAND gate G
It is necessary to change the number of inputs of 1 and the NOR gate G2.
As a result, when there is no error in the read data, all the decode outputs are "0", and when there is an error, the output of the corresponding address of the check matrix is "1".

Even when the 8-bit inspection data is used as in the embodiment of FIG. 3, as shown in FIG. 8, it is possible to use the syndrome decoding circuit of NOR / NAND structure almost in the same manner as in FIG. is there. On the other hand, when the inspection data has 8 bits and therefore the syndrome signal has 8 bits, the syndrome decoding circuit can be configured by inputting only 4 bits of the 8 bits. That is, as shown in FIG. 9, 4 bits of "1" data coincidence detection is performed.
The decoding circuit can be configured using only the input NAND gate. This is because when the inspection data is 8 bits, the syndrome of 64 bits of data bits can be generated by the combination of 4 bits of "1" and 4 bits of "0", and only the matching detection of 4 bits of "1" is possible. This is because the error address can be detected.

FIG. 4 shows a modified embodiment of the ECC circuit 7 of FIG. The basic configuration and operation of the ECC circuit 7 are
Although it is similar to FIG. 3, the difference is that the timing signal TC for setting the error correction timing is used for the syndrome decode / correction circuit 72 in the read / write driver 71. Timing signal generation circuit 8
Generates the timing signal TC internally in synchronization with the data read from the normal data section 1a.

FIG. 5 shows a configuration example of the timing signal generation circuit 8 in relation to the DQ buffer 5. A write circuit 51 that converts the write data WD into complementary signals and supplies them to the data lines DQ and / DQ connected to the cell array 1.
And a buffer amplifier 52 such as a current mirror amplifier for amplifying read data. N driven by the output of the buffer amplifier 52
The read data line RD is connected to the drain of the MOS transistor QN1.

The read data from the DQ buffer 5 is usually not a complementary signal, but in the configuration of FIG. 5, the buffer amplifier 52 which is a current mirror type differential amplifier is of a differential output type. Then, an NMOS transistor QN2 driven complementarily to the output stage NMOS transistor QN1 driven by the buffer amplifier 52 is added, and a data line / RD is connected to its drain. And
An exclusive OR gate (EXOR gate) 81, which receives the outputs of these complementary data lines RD and / RD, is provided. The output of the EXOR gate 81 is the control signal CNT.
It is also input to the NAND gate 82. This allows
From the NAND gate 82, the correction timing signal TC whose control signal CNT is “H” and which becomes “L” only when data is read can be obtained.

The control of the syndrome decode / correction circuit 72 by the timing signal TC may be performed as follows, for example. As shown in FIG. 6A, syndrome decoding /
The correction circuit 72 has a syndrome decode circuit 72a and an error correction circuit 72b. In front of this syndrome decode circuit 72a, a correction timing adjustment circuit (transfer switch circuit) 72c is provided which controls the transfer of the syndrome signal output from the syndrome generation circuit 75 to the decode circuit 72a by the timing signal TC. Alternatively, FIG.
As shown in B, the transfer of the decode signal is performed between the decode circuit 72a and the error correction circuit 72b by the timing signal T.
A correction timing adjustment circuit 72c that is turned on by C is provided.

As described above, if the syndrome decoding / correction circuit 72 is controlled to be activated only when the data is read using the timing signal TC, the syndrome decoding / correction circuit 72 may malfunction due to noise or the like. The situation can be prevented.

FIG. 10 is based on the ECC circuit 7 of FIG. 3, and when the syndrome decoding / correction circuit 72 detects an error, it outputs it to the external monitor terminal as a correction monitor signal MT. It is a thing. Thereby, the operation of the ECC circuit 7 can be confirmed. The correction monitor signal MT may be 1 bit to notify only the presence or absence of correction. It is also effective to output a correction monitor signal MT of a plurality of bits so that the correction position can be confirmed.

Concretely, such an error correction monitor signal MT corresponds to FIG. 6A or FIG. 6B, and as shown in FIG. 11A or 11B, the output of the correction timing adjusting circuit 72c may be the monitor signal MT. Good.

In each of the above embodiments, the EC
The C circuit 7 can be turned on and off by an ECC
Preferred for checking circuit functionality. This is the output stage NA of the timing signal generation circuit 8 as shown in FIG.
This can be done by allowing the control signal CNT of the ND gate 82 to be turned on / off from the outside. For example, the ECC circuit 7 is turned on, and the test data is written by the write operation described in the above embodiment. Then EC
The C circuit 7 is turned off, and the previously written test data is rewritten with the data that is different only in a certain bit.
This means that the parity data part has not been updated, and therefore an error state has been forcibly created. And again E
The CC circuit 7 is turned on to read the test data.
Thereby, it is possible to confirm whether the ECC circuit 7 operates normally.

Further, the DRAM cell array requires a refresh operation in a certain cycle. For this reason, the DRAM chip has a built-in refresh circuit that automatically performs a refresh operation.
No data is read into the buffer 5. Therefore, FIG.
In the embodiment, the correction timing signal generation circuit 8 does not operate during the refresh cycle, and the operation of the ECC circuit 7 stops. Thereby, useless power consumption can be reduced.

[0051]

As described above, in the semiconductor memory according to the present invention, the built-in ECC circuit makes it possible to remedy a data defect particularly due to power saving.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory according to an embodiment of the present invention.

FIG. 2 E in a semiconductor memory according to another embodiment.
It is a figure which shows the structure of a CC circuit.

FIG. 3 shows an E in a semiconductor memory according to another embodiment.
It is a figure which shows the structure of a CC circuit.

FIG. 4 E in a semiconductor memory according to another embodiment.
It is a figure which shows the structure of a CC circuit.

FIG. 5 is a diagram showing a configuration of a correction timing signal generation circuit unit according to the same embodiment.

FIG. 6A is a diagram showing a configuration of an error detection and correction circuit unit according to the same embodiment.

FIG. 6B is a diagram showing another configuration of the error detection and correction circuit unit according to the same embodiment.

FIG. 7 is a diagram showing a configuration of a syndrome signal decoding circuit.

FIG. 8 is a diagram showing another configuration of the syndrome signal decoding circuit.

FIG. 9 is a diagram showing another configuration of the syndrome signal decoding circuit.

FIG. 10 is an ECC of a semiconductor memory according to another embodiment.
It is a figure which shows the structure of a circuit.

FIG. 11A is a diagram showing a configuration of a correction monitor signal generation unit according to the same embodiment.

FIG. 11B is a diagram showing another configuration of the correction monitor signal generation unit according to the same embodiment.

[Explanation of symbols]

1 ... Memory cell array, 1a ... Normal data section, 1b
... parity data part, 2 ... row decoder / word line driver, 3 ... sense amplifier, 4 ... column gate, 5 ... DQ
Buffer, 6 ... I / O buffer, 7 ... ECC circuit, 8 ...
Correction timing adjustment signal generation circuit, 71 ... read / write driver, 72 ... syndrome decode / error correction circuit, 72a ... decoding circuit, 72b ... error correction circuit, 72c ... correction timing adjustment circuit, 73 ... inspection data generation circuit, 74 ... Information data generating circuit, 75 ... Syndrome signal generating circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Munehiro Yoshida             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Hiroshi Shinya             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F-term (reference) 5B018 GA02 HA15 HA17 KA21 NA02                       QA03 QA15                 5L106 AA01 BB02 BB12 FF05 GG05                 5M024 AA40 BB30 BB35 EE05 KK22                       MM09 PP01 PP02 PP03

Claims (34)

[Claims] 1. A cell array comprising a normal data section used for normal data writing and reading, and a parity data section for storing inspection data for detecting an error in read data from the normal data section, and the cell array. A data buffer for temporarily holding read data from the memory cell and write data to the cell array; generating test data to be stored in the parity data portion from the input write data when writing data; and the normal data portion when reading data. An error detection / correction circuit for performing error detection / correction of the read data based on the inspection data read from the parity data part and the data read from the parity buffer, and the normal data of the data buffer and the cell array. N-bit parallel data transfer between In the first half of the data write cycle, the m-bit parallel data is transferred between the data buffer and the external input / output terminal (m and n are integers, m <n). , N-bit data including m-bit data to be rewritten is read in parallel, the error detection and correction circuit performs error detection and correction of the n-bit data, and the error detection and correction circuit corrects the latter half of the data write cycle. A semiconductor memory device, wherein an m-bit data portion to be rewritten of the generated n-bit parallel data is replaced with m-bit parallel data supplied from an external input / output terminal and transferred to the normal data portion. 2. The error detection / correction circuit performs single-bit error correction using a Hamming code, and the inspection data stored in the parity data section is a minimum necessary for error detection / correction of read data. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured by the number of bits. 3. The error detection / correction circuit performs single-bit error correction using a Hamming code, and the inspection data stored in the parity data unit is a minimum necessary for error detection / correction of read data. 2. The semiconductor memory device according to claim 1, wherein the number of bits is one more than the number of bits. 4. The error detection / correction circuit does not perform error correction when the m-bit data portion to be rewritten has an error, and corrects error when there is an error other than the m-bit data portion to be rewritten. The semiconductor memory device according to claim 1, wherein 5. The error detection / correction circuit, in the data read cycle, does not correct the corresponding cell data of the normal data portion even if the read data has an error correction. Semiconductor memory device. 6. The cell array is a DRAM cell array in which data is refreshed in a predetermined cycle, and the error detection / correction circuit is stopped during a refresh operation of the DRAM cell array. Semiconductor memory device. 7. A cell array comprising a normal data section used for normal data writing and reading, and a parity data section for storing inspection data for detecting an error in read data from the normal data section, and the cell array. A data buffer for temporarily holding read data from and write data to the cell array, and test data to be stored in the parity data section from the write data input at the time of data writing,
And the read data for performing error detection and correction of the data read from the normal data section and the inspection data read from the parity data section when reading the data. A syndrome generation circuit for generating a syndrome signal based on inspection data and a syndrome decoding / decoding for decoding the generated syndrome signal to correct an error bit.
An error detection / correction circuit having an error correction circuit, a timing signal generation circuit that detects a change in output data in the data buffer to generate a timing signal, and a timing signal generated by the timing signal generation circuit that is controlled by the timing signal. A correction timing adjusting circuit for transferring a syndrome signal to the syndrome decoding / error correcting circuit, and a semiconductor memory device. 8. The error detection / correction circuit performs single-bit error correction using a Hamming code, and the inspection data stored in the parity data unit is a minimum necessary for error detection / correction of read data. 8. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is configured by the number of bits. 9. The error detection / correction circuit performs single-bit error correction using a Hamming code, and the inspection data stored in the parity data unit is a minimum necessary for error detection / correction of read data. 8. The semiconductor memory device according to claim 7, wherein the number of bits is one more than the number of bits. 10. N-bit parallel data is exchanged between the data buffer and the normal data part of the cell array, and m-bit parallel data (where m <n. ) Is given and received in the first half of the data write cycle.
The n-bit data including the m-bit data to be rewritten is read in parallel, the error detection and correction circuit performs error detection and correction on the n-bit data, and the error detection and correction circuit corrects the latter half of the data write cycle. The m-bit data portion to be rewritten of the n-bit parallel data is replaced with the m-bit parallel data supplied from the external input / output terminal and transferred to the normal data portion. Semiconductor memory device. 11. The error detection / correction circuit does not perform error correction when there is an error in the m-bit data portion to be rewritten, but does not perform error correction when there is an error in a portion other than the m-bit data portion to be rewritten. 11. The semiconductor memory device according to claim 10, wherein: 12. The error detection / correction circuit, in a data read cycle, does not correct the corresponding cell data of the normal data portion even if there is an error correction of the read data. Semiconductor memory device. 13. The cell array is a DRAM cell array in which data is refreshed in a predetermined cycle, and the error detection / correction circuit is stopped during a refresh operation of the DRAM cell array. Semiconductor memory device. 14. The error detection / correction circuit is configured to be capable of switching between an active state and an inactive state by externally controlling an active state or an inactive state of the timing signal generating circuit. The semiconductor memory device according to claim 7. 15. The semiconductor memory device according to claim 7, further comprising a monitor terminal for outputting an output of the correction timing adjustment circuit as a monitor signal for notifying the presence / absence of error correction to the outside. 16. A cell array comprising a normal data part used for normal data writing and reading, and a parity data part for storing inspection data for detecting an error in read data from the normal data part, and the cell array. A data buffer for temporarily holding read data from and write data to the cell array, and test data to be stored in the parity data section from the write data input at the time of data writing,
An error detection / correction circuit that performs error detection / correction on the data read from the normal data section and the inspection data read from the parity data section when reading the data; The detection / correction circuit includes a syndrome generation circuit that generates a syndrome signal based on the read data and inspection data, and a syndrome decoding circuit that decodes the generated syndrome signal and corrects error bits. A syndrome decoding / error correction circuit, wherein the syndrome decoding circuit detects a first NA for detecting a combination of “1” data of a syndrome signal.
An ND gate, a NOR gate for detecting a combination of “0” data, and a second NAND gate for performing coincidence detection of the inverted signal of the output of the first NAND gate and the output of the NOR gate are provided. And a semiconductor memory device. 17. The error detection / correction circuit performs single-bit error correction by a Hamming code,
17. The semiconductor memory device according to claim 16, wherein the inspection data stored in the parity data section is composed of a minimum number of bits required for error detection and correction of read data. 18. The error detection / correction circuit performs single-bit error correction by a Hamming code,
17. The semiconductor memory device according to claim 16, wherein the inspection data stored in the parity data section has a bit number that is one bit larger than the minimum bit number required for error detection and correction of read data. 19. The n-bit parallel data is transmitted and received between the data buffer and the normal data part of the cell array, and the m-bit parallel data (where m <n In the first half of the data write cycle, n-bit data including m-bit data to be rewritten is read in parallel, and the error detection and correction circuit performs error detection and correction of the n-bit data. In the latter half of the data write cycle, the m-bit data portion to be rewritten of the n-bit parallel data corrected by the error detection / correction circuit is replaced with the m-bit parallel data supplied from the external input / output terminal. 17. The semiconductor memory according to claim 16, wherein the semiconductor memory is transferred to a normal data section. Location. 20. The error detection / correction circuit does not perform error correction when the m-bit data portion to be rewritten has an error, and corrects error when there is an error other than the m-bit data portion to be rewritten. 20. The semiconductor memory device according to claim 19, further comprising: 21. The error detection / correction circuit, in a data read cycle, does not correct the corresponding cell data in the normal data portion even if there is an error correction in the read data. Semiconductor memory device. 22. The cell array is a DRAM cell array in which data is refreshed at a predetermined cycle, and the error detection / correction circuit is stopped during a refresh operation of the DRAM cell array. Semiconductor memory device. 23. A cell array having a normal data section used for normal data writing and reading, and a parity data section for storing inspection data for detecting an error in read data from the normal data section, and the cell array. A data buffer for temporarily holding read data from and write data to the cell array, and test data to be stored in the parity data section from the write data input at the time of data writing,
An error detection / correction circuit that performs error detection / correction on the data read from the normal data section and the inspection data read from the parity data section when reading the data; The detection / correction circuit includes a syndrome generation circuit that generates a syndrome signal based on the read data and inspection data, and a syndrome decoding circuit that decodes the generated syndrome signal and corrects error bits. A semiconductor memory having a syndrome decode / error correction circuit, wherein the syndrome decode circuit is configured by a NAND gate array in which NAND gates for detecting a combination of “1” data of a syndrome signal are arranged. apparatus. 24. The error detection / correction circuit performs single-bit error correction using a Hamming code,
24. The semiconductor memory device according to claim 23, wherein the inspection data stored in the parity data section is constituted by a minimum number of bits required for error detection and correction of read data. 25. The error detection / correction circuit performs single-bit error correction by a Hamming code,
24. The semiconductor memory device according to claim 23, wherein the inspection data stored in the parity data unit is configured by a bit number that is one bit larger than the minimum bit number required for error detection and correction of read data. 26. The n-bit parallel data is transferred between the data buffer and the normal data part of the cell array, and the m-bit parallel data (where m <n is set between the data buffer and the external input / output terminal). ) Is given and received in the first half of the data write cycle.
The n-bit data including the m-bit data to be rewritten is read in parallel, the error detection and correction circuit performs error detection and correction on the n-bit data, and the error detection and correction circuit corrects the latter half of the data write cycle. 24. The m-bit data part to be rewritten of the n-bit parallel data is replaced with the m-bit parallel data supplied from the external input / output terminal and transferred to the normal data part. Semiconductor memory device. 27. The error detection / correction circuit does not perform error correction when the m-bit data portion to be rewritten has an error, and corrects error when there is an error other than the m-bit data portion to be rewritten. 27. The semiconductor memory device according to claim 26, wherein: 28. The error detection / correction circuit, in a data read cycle, does not correct the corresponding cell data of the normal data portion even if there is an error correction of the read data. Semiconductor memory device. 29. The cell array is a DRAM cell array in which data is refreshed in a predetermined cycle, and the error detection / correction circuit is stopped during a refresh operation of the DRAM cell array. Semiconductor memory device. 30. A cell array comprising a normal data section used for normal data writing and reading, and a parity data section for storing inspection data for detecting an error in read data from the normal data section, and the cell array. A data buffer for temporarily holding read data from and write data to the cell array, and test data to be stored in the parity data section from the write data input at the time of data writing,
An error detection / correction circuit that performs error detection / correction on the data read from the normal data section and the inspection data read from the parity data section when reading the data; The detection / correction circuit performs a single-bit error correction using a Hamming code, and the inspection data stored in the parity data section has a bit number that is one more than the minimum number of bits required for 1-bit error correction. A semiconductor memory device having a structure. 31. n-bit parallel data is exchanged between the data buffer and the normal data portion of the cell array, and m-bit parallel data (where m <n is satisfied) between the data buffer and an external input / output terminal. ) Is given and received in the first half of the data write cycle.
The n-bit data including the m-bit data to be rewritten is read in parallel, the error detection and correction circuit performs error detection and correction on the n-bit data, and the error detection and correction circuit corrects the latter half of the data write cycle. 31. The m-bit data portion to be rewritten of the n-bit parallel data is replaced with the m-bit parallel data supplied from the external input / output terminal and transferred to the normal data portion. Semiconductor memory device. 32. The error detection / correction circuit does not perform error correction when there is an error in the m-bit data portion to be rewritten, but does not perform error correction when there is an error in a portion other than the m-bit data portion to be rewritten. 32. The semiconductor memory device according to claim 31, wherein: 33. The error detection / correction circuit, in the data read cycle, does not correct the corresponding cell data of the normal data portion even if the read data has an error correction. Semiconductor memory device. 34. The cell array is a DRAM cell array in which data is refreshed in a predetermined cycle, and the error detection / correction circuit is stopped during a refresh operation of the DRAM cell array. Semiconductor memory device.