JP2001297595A - Semiconductor memory and semiconductor integrated circuit device - Google Patents

Semiconductor memory and semiconductor integrated circuit device

Info

Publication number
JP2001297595A
JP2001297595A JP2000111608A JP2000111608A JP2001297595A JP 2001297595 A JP2001297595 A JP 2001297595A JP 2000111608 A JP2000111608 A JP 2000111608A JP 2000111608 A JP2000111608 A JP 2000111608A JP 2001297595 A JP2001297595 A JP 2001297595A
Authority
JP
Japan
Prior art keywords
data
data line
circuit
data lines
connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000111608A
Other languages
Japanese (ja)
Other versions
JP2001297595A5 (en
Inventor
Hiroaki Tanizaki
弘晃 谷崎
Original Assignee
Mitsubishi Electric Corp
Mitsubishi Electric Engineering Co Ltd
三菱電機エンジニアリング株式会社
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp, Mitsubishi Electric Engineering Co Ltd, 三菱電機エンジニアリング株式会社, 三菱電機株式会社 filed Critical Mitsubishi Electric Corp
Priority to JP2000111608A priority Critical patent/JP2001297595A/en
Publication of JP2001297595A publication Critical patent/JP2001297595A/en
Publication of JP2001297595A5 publication Critical patent/JP2001297595A5/ja
Pending legal-status Critical Current

Links

Abstract

(57) Abstract: A data line which is not used after being shifted by a shift redundant circuit due to a defective bit occurring in a semiconductor memory device is prevented from floating. A data line including a redundant data line connected to a write driver circuit and a data line connected to a data input / output circuit are connected to a shift redundant circuit. The data lines other than the data lines are connected to each other, and when a data line connected to the memory cell array becomes defective, the data lines are sequentially connected so that the defective data line is switched to the redundant data line. The data lines connected to the write driver circuit 9 are provided with latch circuits 16 and 17 for retaining data, so that the data lines connected to the write driver circuit 9 are configured so as to be shifted and the data lines that have been shifted and are not used do not float. Is what it is.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a DRAM and a semiconductor integrated circuit device in which a semiconductor memory device and a logic circuit are mounted together and formed on one chip.

[0002]

2. Description of the Related Art FIG. 8 is a schematic diagram showing a semiconductor memory device of a system LSI in which a conventional semiconductor memory device and a logic section are mixed, and the semiconductor memory device is formed by a DRAM. 8, reference numeral 1 denotes a predecode signal RA from row / column addresses A0 to An input from the outside.
0-RAi, CA0-CAi, and clock signals (Read CLK, W) supplied to each unit from the input command signals (/ RAS, / CAS, / WE).
write CLK), an address clock generation circuit which fetches an address input from address terminals (A0 to An) and outputs a row-based predecode signal R
A0-RAi signals and column predecode signals C
A0 to CAi are generated.

Reference numeral 2 denotes predecode signals RA0 to RAi and CA0 to CAi which are outputs of the address clock generation circuit 1.
A row / column decoder circuit for decoding signals, generates a WL (word line) signal and an SA (sense amplifier) activation signal from row-related predecode signals RA0 to RAi, and selects a column from column-related predecode signals CA0 to CAi. Signal C
Generate SL. Reference numeral 3 denotes a memory cell array unit having a memory cell array 4 and a sense amplifier (SA) band 5, and accesses a memory cell selected by a WL signal and a column selection signal output by the row / column decoder circuit 2. The signal of the selected memory cell is applied to the data line (IO
Line).

Reference numeral 6 denotes an IO line write driver / read amplifier band for inputting read data from a data line and driving write data to the data line. Reference numeral 7 denotes a data input / output circuit for controlling the IO line write driver / read amplifier band 6, outputting data read out to the outside, and inputting write data input from the outside to the write driver. Here, the terminals input / output to / from the data input / output circuit 7 will be described. The DQ terminal is a terminal for inputting / outputting data from the outside. The DQ terminal has hundreds of terminals to improve the data transfer speed between the external logic circuit and the memory. WM
The terminal is a terminal to which the write mask signal WM signal is input.
When data is input to the WM terminal, writing is not performed, and data written before this operation is retained. In the circuit configuration of FIG. 8, a 1-bit WM terminal is used for an 8-bit DQ terminal. An output enable signal is input to the / OE terminal. Reference numeral 8 denotes a shift redundant circuit for replacing a redundant data line. When there is a defect in a memory cell, there is a replacement method for shifting a data line as a replacement method for replacing the memory cell with a redundant circuit. This is a shift redundant circuit 8, which is a data input / output circuit 7 and an IO line write driver / It is provided between the read amplifier band 6.

FIG. 9 is a circuit diagram showing a shift redundancy circuit of a conventional semiconductor memory device. In FIG. 9, 7 and 8 are the same as those in FIG. 9 is a write driver circuit included in the IO line write driver / read amplifier band 6, 10 is a NAND circuit, 11 is an inverter, and 12 is an N-channel MOS transistor. A shift redundancy circuit 8 is provided between the data input / output circuit 7 and the write driver circuit 9. On the write driver circuit 9 side, data lines including memory cells provided extra as redundancy cells are (data number + redundant data line). ) Are connected. On the other hand, on the data input / output circuit 7 side, m data lines are connected, and the connection of both data lines is switched by the shift redundant circuit 8. When a certain data line is defective, the shift redundancy circuit 8
The connection is switched so as to shift the data line to the next data line. The shifted data line is shifted to the next data line, and is finally replaced with a data line prepared as redundant.

More specifically, data line IOD <1> shown in FIG.
If there is a defect, the signal SCA <1> and SCA <0> become Hi by setting the shift data SD <1> to Low.
, The data line IO <1> is connected to the data line IOD <0>, and then the data line IO <0> is connected to the data line SOD. As a result, the data line IOD <1> is not connected to the input data line connected to the data input / output circuit 7. In this way, the defective data line is replaced.

FIG. 10 shows a shift data generating circuit of a conventional semiconductor memory device. In FIG. 10, 13
Is a redundancy judgment circuit for judging redundancy from an address signal,
A decoder circuit 4 decodes the output of the redundancy judgment circuit 13 and outputs the shift data SD. As shown in FIG. 10, the shift data SD signal of FIG.
The redundancy is determined by the redundancy determining circuit 13 in response to the Col address, and then the signal passes through the decoder circuit 14 and is generated.

[0008]

A data line which has been shifted and is no longer used has a problem that input data is in a floating state and a through current is generated in a transistor to which the data line is connected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is a first object of the present invention to provide a semiconductor memory device which prevents a data line which has been shifted and is no longer used from being brought into a floating state. I am aiming.
It is a second object of the present invention to obtain a semiconductor integrated circuit device in which such a semiconductor memory device is mounted together with a logic circuit on a single chip.

[0010]

In a semiconductor memory device according to the present invention, a memory cell array having a large number of memory cells arranged in a matrix, an input / output circuit for inputting / outputting data to / from the outside, and a memory cell array Are connected to n first data lines including redundant data lines connected to m and m second data lines connected to the input / output circuit, and exclude redundant data lines among the first data lines m and m second data lines are respectively connected, and
When a failure occurs in the first data line connected to the second data line, m first data lines other than the failed first data line are connected to the second data line. Thus, a shift circuit for sequentially shifting the connection is provided, and a latch circuit for holding data is provided on a first data line connected to the shift circuit. An initial value is given to a latch circuit provided on a redundant data line among the first data lines. A memory cell array having a large number of memory cells arranged in a matrix; an input / output circuit for inputting / outputting data to / from the outside; and n first data lines including a redundant data line connected to the memory cell array And the m data lines connected to the m second data lines connected to the input / output circuit and connecting the m data lines and the m second data lines of the first data lines excluding the redundant data lines. And when a failure occurs in the first data line connected to the second data line, the m first data lines excluding the failed first data line are connected to the second data line. A shift circuit for sequentially shifting the connection so as to connect to the line,
A first data line connected to the shift circuit is provided with a half-latch circuit that is precharged to a high potential at a predetermined timing and holds the precharged high potential during a period in which data is written to the memory cell array. Is what it is.

Further, a memory cell array having a large number of memory cells arranged in a matrix, an input / output circuit for inputting / outputting data to / from the outside, and n first data lines including redundant data lines connected to the memory cell array. Are connected to the m data lines and m second data lines connected to the input / output circuit, and connect the m data lines and the m second data lines except the redundant data lines among the first data lines, respectively. Be configured to
When a failure occurs in the first data line connected to the second data line, m first data lines other than the failed first data line are connected to the second data line. The first data line connected to the shift circuit is precharged to a high potential at a predetermined timing and precharged during a period in which data is written to the memory cell array. In this case, a capacitor for holding a high potential is provided. A write driver circuit for writing data to the memory cell array through the first data line is arranged between the shift circuit and the memory cell array, and the input / output circuit corresponds to m second data lines. M input / output terminals are provided. Further, a write mask signal for masking write data for every k data lines is input to the input / output circuit.
The shift circuit includes a mask shift circuit for shifting the connection of the write mask signal line, and the mask shift circuit is configured to shift the connection of one write mask signal line for every k data lines. .

In addition, in the semiconductor integrated circuit device according to the present invention, the semiconductor memory device configured as described above is connected to the m number of input / output terminals of the semiconductor memory device, and is connected to the semiconductor memory device. And a logic circuit for controlling the data transfer of the semiconductor memory device.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 The configuration of the semiconductor memory device according to the first embodiment is the same as that shown in FIG. FIG. 1 is a circuit diagram showing a shift redundant circuit of a semiconductor memory device according to a first embodiment of the present invention. In FIG. 1, reference numeral 7 denotes a data input / output circuit for controlling an IO line write driver / read amplifier band, outputting data read out to the outside, and inputting write data input from the outside to the write driver. The number of input / output terminals corresponding to the number of data lines connected to are provided.
Reference numeral 8 denotes a shift redundant circuit (shift circuit) for performing replacement with a redundant data line. 9 is a write driver circuit included in the IO line write driver / read amplifier band, and 10 is N
AND circuit, 11 is an inverter, 12 is N-channel M
OS transistor. 16 is a latch circuit composed of two inverters, 17 is a latch circuit composed of an inverter and a NAND circuit, and one of the NAND circuits receives a reset signal RSET. A shift redundancy circuit 8 is provided between the data input / output circuit 7 and the write driver circuit 9. On the write driver circuit 9 side, data lines including memory cells provided extra as redundant cells are (data number + redundant data line). ) Are connected. On the other hand, on the data input / output circuit 7 side, m data lines are connected, and the connection of both data lines is switched by the shift redundant circuit 8. When a certain data line is defective, the shift redundancy circuit 8
The connection is switched so as to shift the data line to the next data line. The shifted data line is shifted to the next data line, and is finally replaced with a redundant data line prepared for redundancy. Specifically, if the data line (first data line) IOD <1> of FIG. 1 has a defect, the shift of the shift data SD <1> to Low causes the signal S
CA <1> and SCA <0> become Hi, the data line (second data line) IO <1> and the data line (first data line) IOD <0> are connected, and then the data line IO <0>
And redundant data line SOD are connected. As a result, the data line IOD <1> is not connected to the input data line connected to the data input / output circuit 7. In this way, the defective data line is replaced.

In the first embodiment, a latch circuit 16 is provided on the data line on the side of the write driver circuit 9 as shown in FIG. 1, and when data is written, the data is latched. When entering the next cycle, when a bit is shifted by the shift redundancy circuit 8 due to a bit failure,
Since the previous state of the defective bit data line is held by the latch circuit, a signal in which Hi or Low is determined is always input to the transistor connected to the shifted defective bit data line. Further, since data is not input to the redundant data line prepared in advance as redundant, it is necessary to determine the data by the latch circuit 17. For this reason, in FIG. 1, the RSET signal is input and reset.

According to the first embodiment, the latch circuit 16,
By latching the data at 17, the data lines that have been shifted and are no longer used can be prevented from becoming floating.

Embodiment 2 FIG. 2 is a circuit diagram showing a circuit for precharging a data line of a semiconductor memory device according to a second embodiment of the present invention. In FIG.
2 is the same as that in FIG. Reference numeral 18 denotes a half latch circuit including an inverter and a P-channel MOS transistor. WPR is a precharge signal, and WDE is a write driver enable signal for sending data to the shift redundancy circuit. FIG. 3 shows an operation timing of a circuit for precharging a data line of a semiconductor memory device according to a second embodiment of the present invention. In the second embodiment, as shown in FIG. 2, by using a circuit for pre-charging the data line, even if the data line is floating when shifted, the logic is always fixed to the Hi side and the transistor connected to the data line is used. No through current flows.

The shift operation of the shift redundant circuit 8 is the same as in the first embodiment. This operation will be described with reference to FIG. First, by time t1, the precharge signal WPR line is set to Low, and the data line is Hi-precharged. Next, at time t2, the precharge signal WPR is set to Hi.
Then, the Hi precharge is maintained in the half latch circuit 18. Next, when the shift data SD signal and the data line are determined, the write driver enable signal WDE is set to Hi and the data is sent to the shift redundant circuit. At this time, since the shift data SD signal is not selected, a normal data line is selected and data is transmitted. Next, at time t3, the precharge signal WPR and the write driver enable signal WDE fall, and the data line is Hi-precharged. Next, at time t4, precharge signal WPR
Is set to Hi, the Hi precharge is held by the half latch circuit 18, and then the shift data SD signal causes
Switch data lines. After the switching is completed, the write driver enable signal WDE is set to Hi to write data. At this time, since SD <1> is Low, the data line IOD <1> is determined to be a defective bit, and data is not transferred and Hi is not transferred. Precharge is maintained. Data line IO
The data of <1> is transferred to the data line IOD <0>. As a result, the data line IOD <1 not shifted
> Do not float, and no through current is generated.

According to the second embodiment, since the Hi-precharge is held by the half-latch circuit 18, the unshifted data line IOD <1> does not float and no through current is generated. .

Embodiment 3 FIG. 4 is a circuit diagram showing a circuit for precharging a data line of a semiconductor memory device according to a third embodiment of the present invention. In FIG.
2 is the same as that in FIG. Reference numeral 19 denotes a capacitor that holds the Hi precharge during the write period. In the third embodiment, instead of the half latch circuit of the second embodiment,
A capacitor 19 is provided to hold Hi precharge during a write period. The third embodiment operates in the same manner as the second embodiment, and Hi precharge is held by the capacitor 19 instead of the half latch circuit. Even in this case, the through current does not occur without the data line floating.

According to the third embodiment, H
Since the i-precharge is held, there is an effect that the data line which has not been shifted does not float and no through current is generated.

Embodiment 4 FIG. FIG. 5 is a circuit diagram illustrating a shift circuit of a semiconductor memory device according to a fourth embodiment of the present invention. In FIG. 5, reference numeral 21 denotes a write mask signal W
A shift circuit for a write mask (mask shift circuit) for shifting M, and a shift circuit 22 for a data line. FIG. 6 is a circuit diagram illustrating a shift circuit of a semiconductor memory device according to a fourth embodiment of the present invention. 6, reference numerals 21 and 22 are the same as those in FIG. FIG. 7 is a circuit diagram showing a write mask signal shift redundant circuit of a semiconductor memory device according to a fourth embodiment of the present invention. In FIG. 7, 7 to 9 are the same as those in FIG. 23 is an N for switching a write mask signal.
A channel MOS transistor is provided for every 8 bits of the data line. Reference numeral 24 denotes a data line shift circuit for 8 bits.

Embodiment 4 relates to a shift circuit for a write mask which shifts with respect to a write mask signal WM.
The write mask signal WM is applied to 8 bits of the data line.
This signal controls whether data is written to or not written to a memory cell. The write mask signal WM controls whether the write driver circuit 9 writes or does not write to a memory cell. To shift the write mask signal WM similarly to the data line, it is necessary to shift the write mask signal WM using a circuit similar to the data line as shown in FIG. However, when the write mask signal is viewed before and after the shift in terms of the data content, it can be seen that the switching should be performed in units of 8-bit switching of the data lines. FIG. 6 shows that the data line shift circuit 22 requires a data number shift circuit.
Requires only a shift circuit for one bit for eight bits of the data line. When this configuration is made into a circuit, it becomes as shown in FIG.
The circuit for the write mask signal can be reduced to 1/8 of the conventional circuit.

According to the fourth embodiment, the shift circuit for the write mask signal can be configured with a small number of circuits.

In the first to fourth embodiments,
The shift redundancy circuit has been described as being disposed between the input / output circuit and the write driver circuit, but is also applied to data lines (including bit lines) disposed further on the memory cell array side than the write driver circuit. be able to. Further, a logic circuit connected to a number of data input / output terminals corresponding to the data lines of the semiconductor memory device described in the first to fourth embodiments and controlling data transfer with the semiconductor memory device is provided. If they are mounted together on a single chip together with the storage device, a semiconductor integrated circuit device with a high data transfer rate can be obtained.

[0025]

Since the present invention is configured as described above, it has the following effects. A memory cell array having a large number of memory cells arranged in a matrix, an input / output circuit for inputting / outputting data to / from the outside, n first data lines including redundant data lines connected to the memory cell array, and n input / output circuits It is connected to the m second data lines connected to the output circuit, and is configured to connect the m data lines and the m second data lines of the first data lines excluding the redundant data lines. At the same time, when a failure occurs in the first data line connected to the second data line, m first data lines excluding the first data line in which the failure has occurred become the second data line. A shift circuit for sequentially shifting the connection so that the first data line connected to the shift circuit is provided with a latch circuit for holding data; So that the lines do not float It can be. Further, since the initial value is given to the latch circuit provided in the redundant data line among the first data lines, the redundant data line does not float.

Also, a memory cell array having a large number of memory cells arranged in a matrix, an input / output circuit for inputting / outputting data to / from the outside, and n first data lines including redundant data lines connected to the memory cell array. Are connected to the m data lines and m second data lines connected to the input / output circuit, and connect the m data lines and the m second data lines except the redundant data lines among the first data lines, respectively. When a failure occurs in the first data line connected to the second data line, the m first data lines excluding the failed first data line are connected to the first data line. A shift circuit for sequentially shifting the connection so as to connect to the two data lines; a first data line connected to the shift circuit is precharged to a high potential at a predetermined timing, and data is stored in the memory cell array. Write period Since the half-latch circuit holding-charged high potential is provided, a first data line of the shifted defective does not become a floating the writing period.

Further, a memory cell array having a large number of memory cells arranged in a matrix, an input / output circuit for inputting / outputting data to / from the outside, and n first data lines including redundant data lines connected to the memory cell array Are connected to the m data lines and m second data lines connected to the input / output circuit, and connect the m data lines and the m second data lines except the redundant data lines among the first data lines, respectively. Be configured to
When a failure occurs in the first data line connected to the second data line, m first data lines other than the failed first data line are connected to the second data line. The first data line connected to the shift circuit is precharged to a high potential at a predetermined timing and precharged during a period in which data is written to the memory cell array. Since the capacitor holding the high potential is provided, the shifted defective first data line does not float during the writing period.

A write driver circuit for writing data to the memory cell array through the first data line is disposed between the shift circuit and the memory cell array, and m second data lines are provided in the input / output circuit. Since there are m input / output terminals corresponding to the lines, use a shift circuit to shift the data lines corresponding to the input / output terminals, so as to avoid that the shifted first data line becomes floating. Can be. In addition, a write mask signal for masking write data of every k data lines is input to the input / output circuit, and the shift circuit includes a mask shift circuit for shifting connection of the write mask signal line. Since the configuration is such that the connection of one write mask signal line is shifted for every k data lines, the number of mask shift circuits can be reduced.

In addition, in the semiconductor integrated circuit device according to the present invention, the semiconductor memory device configured as described above is connected to the m input / output terminals of the semiconductor memory device and connected to the semiconductor memory device. A semiconductor integrated circuit device having a semiconductor memory device including a logic circuit for controlling data transfer of the semiconductor memory device, and the logic circuit is mounted together with the semiconductor memory device on one chip, so that the shifted defective first data line does not float. Can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a shift redundant circuit of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a circuit for precharging a data line of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 3 is a diagram showing operation timings of a circuit for precharging a data line of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram showing a circuit for precharging a data line of a semiconductor memory device according to a third embodiment of the present invention;

FIG. 5 is a circuit diagram illustrating a shift circuit of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a shift circuit of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram illustrating a write mask signal shift redundant circuit in a semiconductor memory device according to a fourth embodiment of the present invention;

FIG. 8 is a schematic diagram showing a conventional semiconductor memory device according to the first embodiment.

FIG. 9 is a circuit diagram showing a shift redundancy circuit of a conventional semiconductor memory device.

FIG. 10 is a diagram showing a shift data generation circuit of a conventional semiconductor memory device.

[Explanation of symbols]

6 IO line write driver / read amplifier band, 7 data input / output circuit, 8 shift redundant circuit, 9 write driver circuit, 10 NAND circuit, 11 inverter, 1
2,23 N-channel MOS transistor, 16,1
7 latch circuit, 18 half latch circuit, 19 capacitance, 21 shift circuit for write mask, 22, 24 shift circuit for data line.

Claims (7)

    [Claims]
  1. In a semiconductor memory device configured to write and read data to and from a memory cell array through a data line, a memory cell array having a large number of memory cells arranged in a matrix and inputs and outputs data to and from an external device. An input / output circuit, n (n is a positive integer) first data lines including redundant data lines connected to the memory cell array, and m (m is a positive number smaller than n) connected to the input / output circuit. (Integer) and connected to the m data lines excluding the redundant data lines of the first data lines and the m second data lines. When a failure occurs in the first data line connected to the data line, m first data lines other than the first data line in which the failure has occurred are connected to the second data line. Shift connections sequentially A semiconductor memory device including a shift circuit, wherein a latch circuit for holding data is provided on a first data line connected to the shift circuit.
  2. 2. The semiconductor memory device according to claim 1, wherein an initial value is given to a latch circuit provided on a redundant data line among the first data lines.
  3. 3. A semiconductor memory device configured to write and read data to and from a memory cell array through a data line. A memory cell array having a large number of memory cells arranged in a matrix, and inputs and outputs data to and from an external device. A first data line connected to an input / output circuit, n first data lines including redundant data lines connected to the memory cell array, and m second data lines connected to the input / output circuit; Are configured to connect the m data lines except the redundant data lines and the m data lines, respectively, and when a failure occurs in the first data line connected to the second data line. Comprises a shift circuit for sequentially shifting the connection so as to connect the m first data lines except for the first data line where the failure has occurred to the second data line, and is connected to the shift circuit. The first data line is precharged to a high potential at a predetermined timing, and a half-latch circuit for holding the precharged high potential during a period in which data is written to the memory cell array is provided. Semiconductor storage device.
  4. 4. A semiconductor memory device configured to write and read data to and from a memory cell array through a data line. A memory cell array having a large number of memory cells arranged in a matrix, and inputs and outputs data to and from an external device. A first data line connected to an input / output circuit, n first data lines including redundant data lines connected to the memory cell array, and m second data lines connected to the input / output circuit; Are configured to connect the m data lines except the redundant data lines and the m data lines, respectively, and when a failure occurs in the first data line connected to the second data line. Comprises a shift circuit for sequentially shifting the connection so as to connect the m first data lines except for the first data line where the failure has occurred to the second data line, and is connected to the shift circuit. The first data line is precharged to a high potential at a predetermined timing, and is provided with a capacitor for holding the precharged high potential while data is written to the memory cell array. Semiconductor storage device.
  5. 5. A write driver circuit for writing data to the memory cell array through a first data line is arranged between the shift circuit and the memory cell array, and m input / output circuits have m second data lines. 2. The device according to claim 1, wherein m input / output terminals corresponding to the lines are provided.
    The semiconductor memory device according to claim 4.
  6. 6. A write mask signal for masking write data for every k data lines (k is a positive integer smaller than m) is input to the input / output circuit, and the shift circuit connects the write mask signal line. 6. The semiconductor memory according to claim 5, further comprising a mask shift circuit for shifting the connection of one write mask signal line for every k data lines. apparatus.
  7. 7. The semiconductor memory device according to claim 5, further comprising a logic circuit connected to the m input / output terminals of the semiconductor memory device and controlling data transfer with the semiconductor memory device. A semiconductor integrated circuit device, wherein the logic circuit is mounted together with the semiconductor storage device on a single chip.
JP2000111608A 2000-04-13 2000-04-13 Semiconductor memory and semiconductor integrated circuit device Pending JP2001297595A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000111608A JP2001297595A (en) 2000-04-13 2000-04-13 Semiconductor memory and semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000111608A JP2001297595A (en) 2000-04-13 2000-04-13 Semiconductor memory and semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JP2001297595A true JP2001297595A (en) 2001-10-26
JP2001297595A5 JP2001297595A5 (en) 2007-05-10

Family

ID=18623909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000111608A Pending JP2001297595A (en) 2000-04-13 2000-04-13 Semiconductor memory and semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2001297595A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6654298B2 (en) * 2001-03-29 2003-11-25 Fujitsu Limited Semiconductor memory device
US7428168B2 (en) 2005-09-28 2008-09-23 Hynix Semiconductor Inc. Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000076853A (en) * 1998-06-17 2000-03-14 Mitsubishi Electric Corp Synchronous semiconductor storage
JP2000100194A (en) * 1998-09-28 2000-04-07 Nec Corp Control circuit of semiconductor device
JP2000149564A (en) * 1998-10-30 2000-05-30 Mitsubishi Electric Corp Semiconductor memory device
JP2001035181A (en) * 1999-07-16 2001-02-09 Fujitsu Ltd Semiconductor memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000076853A (en) * 1998-06-17 2000-03-14 Mitsubishi Electric Corp Synchronous semiconductor storage
JP2000100194A (en) * 1998-09-28 2000-04-07 Nec Corp Control circuit of semiconductor device
JP2000149564A (en) * 1998-10-30 2000-05-30 Mitsubishi Electric Corp Semiconductor memory device
JP2001035181A (en) * 1999-07-16 2001-02-09 Fujitsu Ltd Semiconductor memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6654298B2 (en) * 2001-03-29 2003-11-25 Fujitsu Limited Semiconductor memory device
US6999358B2 (en) * 2001-03-29 2006-02-14 Fujitsu Limited Semiconductor memory device
US7428168B2 (en) 2005-09-28 2008-09-23 Hynix Semiconductor Inc. Semiconductor memory device sharing a data line sense amplifier and a write driver in order to reduce a chip size

Similar Documents

Publication Publication Date Title
US5226009A (en) Semiconductor memory device supporting cache and method of driving the same
US6957378B2 (en) Semiconductor memory device
KR100306857B1 (en) Synchronous semiconductor memory device capable of high speed reading and writing
US6084818A (en) Semiconductor memory device capable of efficient memory cell select operation with reduced element count
US6650583B2 (en) Test circuit device capable of identifying error in stored data at memory cell level and semiconductor integrated circuit device including the same
US6392938B1 (en) Semiconductor memory device and method of identifying programmed defective address thereof
US6331956B1 (en) Synchronous semiconductor memory device having redundant circuit of high repair efficiency and allowing high speed access
KR100371425B1 (en) Semiconductor memory device and method of controlling the same
KR0144810B1 (en) Semiconductor memory having a plurality
US7327613B2 (en) Input circuit for a memory device
US6636444B2 (en) Semiconductor memory device having improved data transfer rate without providing a register for holding write data
US5289413A (en) Dynamic semiconductor memory device with high-speed serial-accessing column decoder
US6421789B1 (en) Synchronous semiconductor memory device capable of reducing test cost and method of testing the same
US7275200B2 (en) Transparent error correcting memory that supports partial-word write
US6895537B2 (en) Semiconductor integrated circuit device including semiconductor memory with tester circuit capable of analyzing redundancy repair
US5963503A (en) Synchronous systems having secondary caches
US6496429B2 (en) Semiconductor memory device
US5060230A (en) On chip semiconductor memory arbitrary pattern, parallel test apparatus and method
US6166989A (en) Clock synchronous type semiconductor memory device that can switch word configuration
KR100391730B1 (en) Semiconductor memory device in which use of cache can be selected, a method of acessing a semiconductor memory deivce, and a data processing system
US4958326A (en) Semiconductor memory device having a function of simultaneously clearing part of memory data
US4667330A (en) Semiconductor memory device
US6310807B1 (en) Semiconductor integrated circuit device including tester circuit for defective memory cell replacement
US5155705A (en) Semiconductor memory device having flash write function
US5003510A (en) Semiconductor memory device with flash write mode of operation

Legal Events

Date Code Title Description
RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20060314

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20060410

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070316

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070316

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20071214

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20091014

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091020

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091216

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20100609

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20100914