JPS6059786A - Manufacture of photovoltaic device - Google Patents
Manufacture of photovoltaic deviceInfo
- Publication number
- JPS6059786A JPS6059786A JP58168762A JP16876283A JPS6059786A JP S6059786 A JPS6059786 A JP S6059786A JP 58168762 A JP58168762 A JP 58168762A JP 16876283 A JP16876283 A JP 16876283A JP S6059786 A JPS6059786 A JP S6059786A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- curved surface
- transparent conductive
- axis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 17
- 230000003287 optical effect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 46
- 239000004065 semiconductor Substances 0.000 abstract description 33
- 238000000059 patterning Methods 0.000 abstract description 4
- 238000000313 electron-beam-induced deposition Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 abstract 1
- 239000010408 film Substances 0.000 description 69
- 239000007789 gas Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 239000002245 particle Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000033001 locomotion Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000004071 soot Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000026058 directional locomotion Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 phosphor compound Chemical class 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- MZFIXCCGFYSQSS-UHFFFAOYSA-N silver titanium Chemical compound [Ti].[Ag] MZFIXCCGFYSQSS-UHFFFAOYSA-N 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000005341 toughened glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
- H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
- H01L31/03921—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/042—PV modules or arrays of single PV cells
- H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
- H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
- H02S20/00—Supporting structures for PV modules
- H02S20/20—Supporting structures directly fixed to an immovable object
- H02S20/22—Supporting structures directly fixed to an immovable object specially adapted for buildings
- H02S20/23—Supporting structures directly fixed to an immovable object specially adapted for buildings specially adapted for roof structures
- H02S20/25—Roof tile elements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B10/00—Integration of renewable energy sources in buildings
- Y02B10/10—Photovoltaic [PV]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は太陽光等の光エネルギを直接電気ｊ−不ルキに
変換する光起電力装置の製造ノコ法に関りる。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a photovoltaic device that directly converts light energy such as sunlight into electricity.
（ロ）従来技術
光エネルギを油接電気エネルギに変換４゛る光起電力装
置４、所謂太陽電池は無尽蔵な太陽光を」；たるエネル
ギ源としているために、コーネルギ資源の枯渇が問題と
なる中で脚光を浴びている。太陽は晴天時に約ＩＫＷ／
ｍ’のエネルギを地表に与え−しおり、家庭で斯るエネ
ルギを電気エネルギに変換する光起電力装置を電力源と
する場合、家屋の屋上或いは屋根上に敷設する＋法が一
般的Ｃある。(b) Conventional technology Photovoltaic devices that convert light energy into oil-immersed electrical energy4, so-called solar cells, use inexhaustible sunlight as their primary energy source, so the depletion of cornelium resources becomes a problem. It is in the spotlight inside. The sun is about IKW/ on a clear day
When the power source is a photovoltaic device that applies energy of m' to the earth's surface and converts this energy into electrical energy at home, there is a general method of installing it on the roof of the house or on the roof.
特開昭５７−６８４５４号公報、或いは実開昭５８−１
１２６１号公報に開示された太陽電池を８えた屋根瓦、
即し瓦状光起電力装置は斯る家庭用電力源、として好適
である。Japanese Unexamined Patent Publication No. 57-68454 or Utility Model Application No. 58-1
A roof tile equipped with solar cells disclosed in Publication No. 1261,
Therefore, the shingled photovoltaic device is suitable as such a household power source.
（ハ〉 発明の目的
本発明の目的は、斯る家庭用電力源として好適な太陽電
池を備えた屋根瓦の如き曲面状絶縁表面を基板とする光
起電力装置の製造方法を提供することにある。(c) Purpose of the Invention The purpose of the present invention is to provide a method for manufacturing a photovoltaic device having a curved insulating surface such as a roof tile as a substrate and equipped with a solar cell suitable as a household power source. be.
（ニ）発明の構成
本発明光起電力装置の製造方法は、基板の非平面状絶縁
表面に直接被着される膜状の光ｈＫ換領領域、エネルギ
ビームの照射により上記曲面の稜線と平行にバターニン
グし、複数の光電変換領域に分割する構成にある。(d) Structure of the Invention The method for manufacturing the photovoltaic device of the present invention is to provide a film-like light hK conversion region that is directly adhered to the non-planar insulating surface of the substrate, and a film-like light hK conversion region that is irradiated with an energy beam to form a film that is parallel to the ridgeline of the curved surface. It has a structure in which it is patterned and divided into a plurality of photoelectric conversion regions.
（ホ）実施例
第１図及び第２図は本発明製造方法により製造Ｊれイ、
光起電力装置を示し、第１区（Ｊ斜視図、第２１１Ａ１
．４第１図に於（りるＡ−Ａ’線断面図であって、（１
ンは強化ガラス・透明セラミ・／クス等の透光性１．１
．−；絶縁性の材料を瓦状に成型し波仄の絶縁表面か（
＝１劉された基板、（２）（２＞ ・は］二二基基板１
）の絶縁表面に一定間隔を隔てて帖列配ＩＣヱされた複
数の光電変換領域である。上記光電変換領域（２）（２
）・は、例えは基板（１）側から、酸化スス、酸化イン
ジウムスス等の透明導電膜（３）（３）と、その内部に
半導体接合を備えた非晶質ノリコ〉系の非晶質半導体膜
（４＞（４）・−と、該半導１本膜（４）（４）・・と
オーミック接触するアルミ−ニウム等の裏面電極膜（５
，）、（５）・・と、が順次積Ｒされたミクロンオーダ
の膜状を呈する。(E) Example Figures 1 and 2 are manufactured by the manufacturing method of the present invention.
The photovoltaic device is shown in section 1 (J perspective view, section 211A1).
．． 4 In Figure 1, it is a sectional view taken along line A-A' (1
Translucency 1.1 of tempered glass, transparent ceramic, /crystal, etc.
．． −: Is the insulating material molded into a tile shape with a wavy insulating surface?
=1 Liu board, (2) (2> ・ha]22 base board 1
) A plurality of photoelectric conversion regions are arranged in a grid array at regular intervals on the insulating surface of the semiconductor device. The photoelectric conversion area (2) (2)
)・For example, from the substrate (1) side, a transparent conductive film (3) (3) made of soot oxide, indium soot oxide, etc. The semiconductor film (4>(4)・- and the back electrode film (5
, ), (5), etc. are sequentially multiplied to form a film on the order of microns.
各非晶質半導体膜（４□）（４）・・・は、その内部に
例えは膜面に平行なＰ’ＩＮ接合を形成？−へく受光面
側からＪＶ−み５０〜２５０人程度のＰ型層、４０００
〜７０００人程度のｌ型（真性）層及び３００〜６００
人程度のＮ型層が順次積層被着され、従って基板（１）
及び透明導電膜（３）（３）・・・を透過して光入射が
あると、主に工型層に於い−ご自由状態の重子及び止孔
かうと生じ、断る電子及び止孔は上記各層が形成ｉ”、
、’）ＰＩＮ接合電界に引かれて各透明導電膜（３）（
３）・及び裏面電極膜（５）（５） に集電きれ、隣接
する光電変換領域（２）（２）・・の透明導電膜（３）
（３）・と裏面電極膜（５）（５ン・とのｆｆ畳により
電気的に相加された電力が取り出される。Does each amorphous semiconductor film (4□) (4)... form a P'IN junction parallel to the film surface inside it? - P-type layer of about 50 to 250 people, looking at JV from the light-receiving surface side, 4000
-L type (intrinsic) layer of about 7,000 people and 300 to 600 people
N-type layers of the order of magnitude are deposited in sequence, thus forming the substrate (1).
When light enters through the transparent conductive film (3) (3)..., electrons and holes are generated mainly in the mold layer in a free state, and electrons and holes are generated. Each of the above layers forms i'',
, ') Each transparent conductive film (3) (
Transparent conductive film (3) of the adjacent photoelectric conversion area (2) (2) and the back electrode film (5) (5).
The electric power electrically added is taken out by the FF combination of (3) and the back electrode film (5).
第３図乃至第１Ｏ図は本発明製造方法を説ｔｌＪｉ−ｔ
ｌ゛るための要部拡大断面図及び概略的斜視図てＪっる
。Figures 3 to 1O illustrate the manufacturing method of the present invention.
An enlarged sectional view and a schematic perspective view of the main parts are shown below.
第３図の工程では、基板（１〉の周縁部をマスクＣＭっ
だ状態で複数の光電変換領域（２）（２）・を含む曲面
状絶縁表面全域に、電イービーム然着により直接被着さ
れた厚み５００人〜４０００人の酸化インジウムスズ及
び酸化ススの積層構造から成る透ＩＪ１＋導電膜（３）
が、レーザビームの如きエネルギに−ムの照射により各
光電変換領域（２）（２） 毎に分割される。使用され
るレーザ゛は波長１０６．１＋、 ｍ、エネルギ密度７
Ｘ ｌＯ’Ｗ ／ ｃｍ ’、バＪＬ、 ７．周波数
３ ＫＨｚ’（’）Ｎｄ ： ＹＡＧレーザが適当であ
り、対物レンズｆ５０１１１ｍ、走査速度５Ｑｍｍ ／
ｓ６ｃによりバターニングされる。このレーザバター
ニングにより除去された透明導電膜く３）の間隔（Ｌｌ
）は約５０μｍに設定寄れる。In the process shown in Fig. 3, the entire curved insulating surface including a plurality of photoelectric conversion regions (2) (2) is directly coated by electric electron beam deposition with the peripheral edge of the substrate (1) covered with a mask CM. Transparent IJ1+ conductive film (3) consisting of a laminated structure of indium tin oxide and soot oxide with a thickness of 500 to 4000
is divided into photoelectric conversion regions (2) (2) by irradiation with energy such as a laser beam. The laser used has a wavelength of 106.1+ m and an energy density of 7.
X lO'W/cm', Ba JL, 7. Frequency 3 KHz'(')Nd: YAG laser is suitable, objective lens f50111m, scanning speed 5Qmm/
Buttering is performed by s6c. The interval (Ll) of the transparent conductive film 3) removed by this laser patterning
) can be set closer to about 50 μm.
斯るレーザバターニングで留意しなｔノれはならないこ
とは被加工面である透明４電膜（３）との距１）１ｔか
大幅に変動してはならないことである。即し、対物レン
ズに入射したレーデビームは、該レンズによる収束作用
によりエネルギ畜度及び加工幅か制御されるために、上
述の如く被加工面との距離が大幅に変動すると、エネル
ギ也゛度及び加］１：幅も変動し所望の加工を施すこと
ができなくなるからである。What must be kept in mind in such laser patterning is that the distance 1) 1t from the surface to be processed, ie, the transparent 4-electric film (3), must not vary significantly. In other words, the energy density and machining width of the Radhe beam incident on the objective lens are controlled by the convergence effect of the lens, so if the distance to the workpiece surface changes significantly as described above, the energy density and machining width will change. [addition] 1: This is because the width also changes, making it impossible to perform the desired processing.
従っ１本発明にあり一〇は、曲面状絶縁表面に直接被着
された透明導電膜（３）を各光ｉ変換領域（２）（’２
）・毎に分割せしめる際に、第４図に示す如く基板（１
）を載置し）ｌ、Ｙ軸及びＸ軸方向に移動せしめるＸＹ
Ｚステージ（６）の上記Ｘ軸方向と、基板（１〉表面に
於ける稜線（７）方向と、を一致せしめ、斯るＸ軸方向
に移動する過程に於いて上記レーザビーム（８）を照射
し対物レンズく９）と波力ロエ面との距離を一定に保つ
−〔いる。次いで、一つの隣接間隔ｇｌ（に位置する透
明導電膜（３）の除去が基板（１）のＸ軸方向の移動に
よる走査によって終ｒすると、ＸＹＺステージ（６）は
次に除去ずへき隣接間隔部に位置ｒる透明導電膜（３）
と対物レンズ（９）とが対向すへく基板（１）をＹ軸方
向に移動せしめる。この状態に於いて、上記対物レンズ
（９）と被加工面との距離は基板（１）の曲面状絶縁表
面がＹ＊ｔｈ方向に変化しているために先のレーザビー
ム照射時と異なっており、ＸＹＺスフ・−シ（６）を２
軸方向に上昇或いは下降けしめＰめ定められた距離に補
正する。補正後、再ひＸ Ｙ Ｚステージ（６）をＸ軸
方向に移動上しめ隣接間隔部に位置する不要な透明導電
膜く３）をレーザ５ビーム（９）の照射により除去する
。以後、斯る動作を繰返し行ない透明導電膜（３）（３
）・・を曲面の稜線（７）と平行にパターニングする。Therefore, in the present invention, the transparent conductive film (3) directly adhered to the curved insulating surface is attached to each light i conversion region (2) ('2
). When dividing the board into parts (1
) and move it in the Y-axis and X-axis directions.
The above-mentioned X-axis direction of the Z stage (6) is made to coincide with the ridge line (7) direction on the surface of the substrate (1>), and in the process of moving in the X-axis direction, the above-mentioned laser beam (8) is Keep the distance between the irradiating objective lens (9) and the wave force Loe surface constant. Next, when the removal of the transparent conductive film (3) located at one adjacent interval gl is completed by scanning by moving the substrate (1) in the X-axis direction, the XYZ stage (6) moves to the next adjacent interval without removing Transparent conductive film (3) located in
The substrate (1) facing the objective lens (9) is moved in the Y-axis direction. In this state, the distance between the objective lens (9) and the surface to be processed is different from that during the previous laser beam irradiation because the curved insulating surface of the substrate (1) is changing in the Y*th direction. Then, XYZ Sufu-shi (6) 2
Correct the upward or downward movement P in the axial direction to a predetermined distance. After the correction, the XYZ stage (6) is again moved up in the X-axis direction and the unnecessary transparent conductive film 3) located at the adjacent interval is removed by irradiation with the laser beam (9). Thereafter, such operations are repeated to form transparent conductive films (3) (3).
)... is patterned parallel to the ridgeline (7) of the curved surface.
透明導電膜（３）（３）・・・のバター−−フグ後、非
晶質半導体膜く２）の被着工程に移る。第５図はセノシ
ラン（ＳｉＨ４）、ジシラン（Ｓｉ２Ｈ，）等のシリ−
ｌン化合物′み囲気中でグロー放電をｌ１ｉｂ起し、反
シロ：カスをプラズマ分解して基板（１）」−に非晶ダ
エンリコン（ａ −Ｓｉ： Ｈ）、非晶質ノリロンカー
バイド（ａ−Ｓ ｉ＝ Ｃ＝ｘ ： Ｈ）、非晶質シリ
コン：： ス（ａ−８ｉｙ ５ｎ１−ｙ ： Ｈ）等の
非晶質シリコン系の非晶質半導体膜く４ンを被着する工
程を模式的に示し１いる。ンリーフン化合物雰囲気中で
のグロー放電により非晶質シリコンの薄膜が得られるこ
とは例えは特公昭５３−３７７１８号公報に開示された
如く既に知られでいる。即ち、従来知られたグロー放電
による非晶質半導体膜の形成は、該半導体膜を被着１・
＼きガラス、ステンレス等の基板を、相対向しグＩＪ−
放電を励起する手行電極間に位置Ｈし、めでいるために
、基板がプラズマの高速荷電粒その移動範囲に於いてそ
の移動方向と直交する結果、斯るプラズマ中の高速荷電
粒子が基板（１）の表面に衝突し、透明導電膜（３）（
３）・・・或いは形成されつつある非晶質半導体膜（４
）の特性が悪化する欠点を備えている。しかも、非晶質
半導体膜（４）が被着ｕしめられる基板（１）の表面は
従来平坦であったのに対し、本発明のそれは曲面状表面
でＪ−、ｉｐ従って従来の如く平行平板電極間に曲面状
表面を備えた基板（１）を配置ゼしめたの−Ｃは斯ｇｔ
１１１１１１１ｊ状表面と対向するー−）５の平行平
板電極との対向距１４１しか不揃いとなるために、被着
せしめられる非晶負半導体膜〈４〉は非均−とならざる
を得ない。After buttering the transparent conductive films (3) (3)..., the process moves to the step of depositing the amorphous semiconductor film (2). Figure 5 shows silanes such as senosilane (SiH4) and disilane (Si2H,).
A glow discharge is generated in the atmosphere surrounding the phosphor compound, and the anti-silicone residue is decomposed by plasma to form amorphous silicone (a-Si: H) and amorphous norilon carbide (a) on the substrate (1). -Si=C=x:H), amorphous silicon::S(a-8iy5n1-y:H), etc. It is shown schematically. It is already known, for example, as disclosed in Japanese Patent Publication No. 53-37718, that a thin film of amorphous silicon can be obtained by glow discharge in an atmosphere of an amorphous silicon compound. That is, the formation of an amorphous semiconductor film by conventionally known glow discharge involves depositing the semiconductor film on
Place the glass, stainless steel, etc. substrates facing each other.
As a result of the substrate being perpendicular to the direction of movement of the high-speed charged particles in the plasma in their moving range, the high-speed charged particles in the plasma are located between the hand electrodes that excite the discharge. It collides with the surface of transparent conductive film (3) (
3)...or an amorphous semiconductor film that is being formed (4)
) has the disadvantage of deteriorating its characteristics. Moreover, whereas the surface of the substrate (1) on which the amorphous semiconductor film (4) is deposited has conventionally been flat, the surface of the present invention has a curved surface. A substrate (1) with a curved surface is placed between the electrodes.
Since only the facing distance 141 between the parallel plate electrode 5 and the 1111111j-shaped surface is uneven, the deposited amorphous negative semiconductor film <4> must be non-uniform.
そこで本発明に用いられる曲面状絶縁表ぼｌ Ｉ＝ ｆ
＋ｉｉｉえた基板（１）は相対向する平行平板電極間に
配置されるのではなく、断る平行平板電極の外−Ｃ且つ
電極の対向面に対し基板（１〉の被着表面を実父′４的
に垂直方向に配置せしめると共に、該基板（１）を図中
矢印で示す如き表面の曲面方向、即ら稜線（７）に対し
て垂直づ５向に移動させなから非晶質半導体膜（４〉を
形成せしめている。即し、第５１２１の実施例にあって
は、上記平行平板電極はアース電極（１０）＜１０）（
１０）と、高周波電源（１１）に連なる高周波電極（１
２）（１２＞とを交互に相対向せしめたマルチ電極構造
を構成Ｌ、ツレ等電ａｉ（１０＞＜１２）（１０）の並
設方向に基板〈１）を移動せしめている。Therefore, the curved insulating surface used in the present invention I=f
+iii The substrate (1) which has been obtained is not placed between the parallel plate electrodes facing each other, but by placing the adhesion surface of the substrate (1) on the outside of the parallel plate electrodes and the opposing surface of the electrodes. At the same time, the substrate (1) is moved in the direction of the curved surface of the surface as shown by the arrow in the figure, that is, in five directions perpendicular to the ridge line (7). >.That is, in the 5121st embodiment, the parallel plate electrodes form a ground electrode (10)<10) (
10) and a high frequency electrode (1) connected to the high frequency power source (11).
2) A multi-electrode structure in which (12>) and (12>) are made to face each other alternately is constructed, and the substrate (1) is moved in the direction in which the deflection isoelectric ai (10><12) (10) is arranged side by side.
しかし、上記マルチ電極構造に関し、基本的には互いに
対向する一つのアース電極（１０）と、一つの高、２周
波電極（１２）との間に於いてグロー放電が励起され両
電極間にプラズマか発生し、反応カスを分解して得られ
た例えばシリコン原子が該内電極の外に近接配置された
基板（１）の曲面状表面にイ・］若することによっ−Ｃ
１序々に非晶質半導体膜（４）が形成されるので、必ず
しもマルチ電極構造を採用する必要はない。However, regarding the above multi-electrode structure, basically, a glow discharge is excited between one earth electrode (10) and one high-frequency, two-frequency electrode (12), which face each other, and plasma is generated between the two electrodes. For example, the silicon atoms obtained by decomposing the reaction residue generated and decomposed are applied to the curved surface of the substrate (1) disposed close to the outside of the inner electrode.
1. Since the amorphous semiconductor film (4) is formed one after the other, it is not necessarily necessary to adopt a multi-electrode structure.
この様に基板（１）を、互いに相対向するアース電極（
１０）（１０）（１０）と、高周波電極（１２）（１２
）の外に配置１−ることによって、基板（１）の被着表
面はプラズマ中での高速荷電粒子の移動領域から外れ、
斯る荷電粒子の衝突が大幅に軽減きれる結果、非晶質半
導体膜（４）へのダメージが低減され、次いで非晶質半
導体膜（４）の形成（被着）上程を、基板（１）をその
表面の曲面方向（電極の並設ツノ向）に移動する過程に
施すことによって、第６凶の示す如く均一性の高い非晶
質半導体膜（４）が得られる。In this way, the substrate (1) is connected to the ground electrodes (
10) (10) (10) and high frequency electrodes (12) (12
), the adhesion surface of the substrate (1) is removed from the region of movement of high-speed charged particles in the plasma,
As a result of the collision of such charged particles being significantly reduced, damage to the amorphous semiconductor film (4) is reduced, and the formation (deposition) of the amorphous semiconductor film (4) is then performed on the substrate (1). By applying this in the process of moving in the curved direction of the surface (toward the edges of the electrodes), a highly uniform amorphous semiconductor film (4) can be obtained as shown in the sixth example.
しかも、非晶質半導体膜形成時に於ける高速荷電粒子に
よるダメージを低減すべく抑えられていた高周波出力を
、商めることかでき膜の成長速度を上昇せしめることも
可能となる。Moreover, the high frequency output, which has been suppressed in order to reduce damage caused by high-speed charged particles during the formation of an amorphous semiconductor film, can be used to increase the growth rate of the film.
尚、斯る第５図の実施例にあ−）では、基板（１）は互
いに相対向配置されたアース電極（１０１（１０）（１
０）及び高周波電極（１２）（１２＞を挾むように２枚
よりられており、従って同時に２枚の基板（１）（１）
に対し、非晶質半導体膜（４）の形成が実１ｉされる。In the embodiment shown in FIG. 5, the substrate (1) has ground electrodes (101 (10) (1
0) and high frequency electrodes (12) (12>), and therefore two substrates (1) (1) are connected at the same time.
On the other hand, the formation of the amorphous semiconductor film (4) is actually carried out 1i.
この時基板（１）（１）を加熱ずへきヒータはし」示し
ていない反応室の側壁の凹所に埋設保Ｊ、ｊ 、すれ、
該基板（１）（１）の各々をその被着面背後から均一に
加熱している。At this time, the substrate (1) (1) is not heated, but the heater is buried in a recess in the side wall of the reaction chamber (not shown).
Each of the substrates (1) (1) is uniformly heated from behind the surface to which it is attached.
第７図は非晶質半導体膜（４）の他の被着（形成ン］−
程を模式的に示し、先の実施例、即し第１の実施例とは
、アース電極（１０）（１０）及び、犠周波′ｉ［極（
１２）（１２）と、基板（１）との対向状態と、更には
反応ガスを吐出するガス供給体（１３）の具体的構造に
於いて相違する。即ち、基板（１）と対向する各アー
スＴＪｔ、！ （１０）（１０）及び高周波電極（１２
＞（１２＞（Ｊ）対同面（１０ａ ）（１２ａ ）・・
・は基板（１）表面の曲面とｖ行に対向すべく同形状の
曲面を呈している。従っ−〔、同形状の曲面を各電極（
１０）（１２） の対向面（１０ａ ）（１２ａ ）
に付与４ることにより、該対向１ｆｉＪ （１０ａ ）
（１２ａ Ｌ ・ と基板（５〉表面とのス、ｊ同距離
は等しくなる結果、均一な非晶質半導体膜（４）の形成
を、基板（１）が停止した状態でもイＪなつことかでき
るが、より均一な非晶質半導体膜（４）を街・ようとし
た場合、やはり図中矢印で、Ｊりず如＼第１の実施例と
同様に基板く１）をアース電極＜１０）（１０）及び高
周波電極（１２）（１２＞の並設）ｊ向、（基板（１）
の稜線方向）への移動過程中に実ｆＴＬｋ方が好ましい
。Figure 7 shows another deposition (formation) of the amorphous semiconductor film (4).
In the previous embodiment, that is, the first embodiment, the earth electrode (10) (10) and the sacrificial frequency ′i [pole (
12) The difference is in the state of facing the substrate (1) and the specific structure of the gas supply body (13) that discharges the reaction gas. That is, each arc facing the substrate (1)
SuTJt,! (10) (10) and high frequency electrode (12
>(12>(J) vs. same side (10a)(12a)...
* represents a curved surface of the same shape as the curved surface of the surface of the substrate (1) so as to face the v-row. Therefore, curved surfaces of the same shape are connected to each electrode (
10) (12) Opposing surfaces (10a) (12a)
By adding 4 to the opposite 1fiJ (10a)
(12a) Since the distances between L and the surface of the substrate (5) are equal, it is possible to form a uniform amorphous semiconductor film (4) even when the substrate (1) is stopped. However, when trying to form a more uniform amorphous semiconductor film (4), as shown by the arrow in the figure, the substrate 1) is connected to the ground electrode <10) as in the first embodiment. (10) and high frequency electrode (12) (parallel arrangement of 12>) j direction, (substrate (1)
The actual fTLk is more preferable during the movement process (in the direction of the ridge line).
一方、ガス供給体（１３）は多数の吐出孔（１４）（１
４）が穿たれたガス吐出面（１５）ｅ、アース電極（１
０）（１０）及び高周波電極（１２）＜１２）を挾んで
基板（１）の曲面状表面と対向すへく配置し、ｌ１ｌｉ
るガス吐出面〈１５）と曲面状表面との対向距離を等し
くずべくガス吐出面（１５）も基板（１〉表面と同形状
の曲面状を呈している。吐出上しめられる反応ガスは形
成すべき非晶質半導体により異なるが、例えは非晶質シ
リコンの場合、モノシラン（ＳｉＨ，＞及びまたはシン
ラン（Ｓｉ２Ｈ６）をヘーメに、Ｐ型決定不純物を含む
ンホラン（Ｂ２Ｈ，、）、名しくは８里す決定不純物を
含むボスフィン（ＰＨ：ｔ）か適宜１：１に加される。On the other hand, the gas supply body (13) has a large number of discharge holes (14) (1
4) perforated gas discharge surface (15) e, earth electrode (1
0) (10) and the high frequency electrode (12) < 12) are placed in between and facing the curved surface of the substrate (1),
The gas discharge surface (15) also has the same curved shape as the surface of the substrate (1) in order to equalize the facing distance between the gas discharge surface (15) and the curved surface. It varies depending on the amorphous semiconductor to be used, but for example, in the case of amorphous silicon, monosilane (SiH, > and or silane (Si2H6) is used, and silane (B2H, ), which contains P-type determining impurities, is used. 8. Bosphin (PH:t) containing 8-risu-determined impurities is added at a ratio of 1:1 as appropriate.
尚、断るガス供給体（１３）！こ代つ−ｃ、！Ｉ！扱（
１）をもう一枚装置しても良い。In addition, the gas supply body (13) refuses! Koyotsu-c,! I! Handling (
1) may be used as an additional device.
上記第１・第２の実施例ともほぼ同一の反応条件により
非晶質半導体膜（４）を形成することか（きる。The amorphous semiconductor film (4) can be formed under substantially the same reaction conditions as in the first and second embodiments.
以下にＰ Ｉ Ｎ接合型非晶質ソリコンを形成°りる場
合の基本的反応条件を記す。The basic reaction conditions for forming a PIN junction type amorphous solicon are described below.
０基板塩度 ２５０〜３００℃
Ｏ高周波電ｆＡ１３．５６Ｍ Ｈｚ
Ｏ高周波出力 １００Ｗ
Ｏ反応ガス （組成比）
Ｐ型ｆ＠ Ｂ２ Ｈ６／ Ｓ １Ｈ４＝ ０．１％Ｉ
型（ノント′−ブ）層 Ｓ １Ｈ４＝１００％Ｎ型層
ＰＨ３／５ｉＨ４＝１％
０ガスＪ五 ０．３−ＩＴｏｒｒ
Ｏガス流量 １Ｏ−４０ｃｃ／ｍｉｔ
この様にして基板（１）の曲面状表面に均一に被着形成
された非晶質シリコンの如き非晶對半導（＋膜（４）は
第４図に示したようにＸＹＺスナーシ（６）に載置され
、第８図の工程でその隣接間隔部かレーデビーム（８）
の照射により除去さｔして各光電変換領域＜２）＜２＞
・・毎に分離形成されると共に、該除去された非晶質半
導体膜（４）（４） に覆われていた透明導電膜（３〉
（３） の−Ｂ１；がレーザビーム（８）の走査方向全
長に且って露出ゼしめられる。使用されるレーザは波長
１．０６，１１ｍ、−１−不ルギ密度５ Ｘ １０’Ｗ
／ ｃｍ ２、パルス周波数３ＫＨｚのＮｄ：ＹＡＧ
レーザであり、除去された非晶質半導体膜（４）・の間
隔（Ｂ２）は約２００μｍに設定きれる。0 Substrate salinity 250-300℃ O high frequency electric fA 13.56 MHz O high frequency output 100 W O reaction gas (composition ratio) P type f@ B2 H6/ S 1H4 = 0.1%I
Type (non-type) layer S 1H4 = 100% N-type layer
PH3/5iH4=1% 0 gas J5 0.3-ITorr O gas flow rate 10-40cc/mit Non-crystalline silicon such as amorphous silicon is uniformly deposited on the curved surface of the substrate (1) in this way. The crystal semiconductor (+ film (4) is placed on the XYZ scanner (6) as shown in Figure 4, and in the process shown in Figure 8, the adjacent gap or the radar beam (8)
Each photoelectric conversion region <2) <2> is removed by irradiation with
The transparent conductive film (3) that was separately formed and covered with the removed amorphous semiconductor film (4) (4)
(3) -B1; is exposed over the entire length of the laser beam (8) in the scanning direction. The laser used has a wavelength of 1.06, 11 m, and a -1-ulgi density of 5 x 10'W.
/ cm2, Nd:YAG with pulse frequency 3KHz
The distance (B2) between the removed amorphous semiconductor films (4) can be set to about 200 μm.
斯るレーザビーム（８〉の走査づｊ向は透明４電膜（３
）（３）・・のそれと同様に、対物レンス（９）と被加
工面との距離を一定に保つべく ｘｙｚスフーーン（６
）のＸ軸と一致した基板（１）の曲面状表面に於ける稜
線（７）方向であり、上記ＸＹＺスデージく６）のｘｓ
方向の移動により５０ｍｗｎ ／ ｓｅｃの速度で上記
レーザビーム（８）は走査される。一つの隣接間隔部の
レーザビーム（８）の走査が終了すると、ＸＹＺステー
ジ（６）をＹＩＩＩＩ方向１．コ移動ｌ：！′Ｌ、 Ｉ
ｓつ”Ｃ次に除去すべき非晶質半導体膜（４） と対物
【−ンス（９〉とを対向させ、然る後両者の対向距離を
予め定められた一定値に補正すべくｚ軸方向に移動せし
める。そして再びＸ軸−）５向の移動によりレーザビー
ム〈８）を走査する動作を繰返し実行し、非晶質半導体
膜（４）（４）・ を透明導電膜（３）（３）・の一部
を露出せしめた状態で基板（１）表面のｖ〉二線（７）
と平行にパターニングする。The scanning direction of such a laser beam (8) is a transparent four-electrode film (3).
)(3)..., in order to keep the distance between the objective lens (9) and the surface to be processed constant,
) is the direction of the ridge line (7) on the curved surface of the substrate (1) that coincides with the X axis of
The laser beam (8) is scanned by the directional movement at a speed of 50 mwn/sec. When scanning of one adjacent interval section with the laser beam (8) is completed, the XYZ stage (6) is moved in the YIII direction 1. Move l:! 'L, I
Next, the amorphous semiconductor film (4) to be removed and the object (9) are made to face each other, and then the z-axis is adjusted to correct the facing distance between the two to a predetermined constant value. Then, the operation of scanning the laser beam (8) is repeated by moving in the X-axis (-) direction again, and the amorphous semiconductor film (4) (4) is transferred to the transparent conductive film (3) ( 3) v〉 double wire (7) on the surface of the substrate (1) with a part of
pattern parallel to the
第９図の工程では、裏面電極膜（５）か非晶負半導体膜
＜４）（４＞・・及び透明４電膜（３＞（３） の露出
部（３ａ）（３ａ）・・の表面を含ん−Ｃ全光電変換領
域＜２ ）＜２ ）・・に跨って連続的に被着ｕしのら
れる。In the process shown in FIG. 9, the exposed portions (3a) (3a) of the back electrode film (5) or the amorphous negative semiconductor film <4) (4>... and the transparent 4-electrode film (3>(3))... -C is continuously deposited over the entire photoelectric conversion area <2)<2) including the surface.
斯る裏面電極膜（５）の隣接間隔部は、続く？Δ１０図
の工程で、一つの光電変換領域（２’＞（２）・から延
在した裏面電極膜（５）（５）の延艮部（５ａ）（５ａ
）・・が隣接せる光電変換領域＜２＞（２） の透明導
電膜＜３）（３）・・・の露出部（３ａ ＞（３ａ’
）・・と結合寸へくレー→ノ゛ビーム（８）の照射によ
り除去され、その間隔（Ｌ３〉は５０ｐｍに設ボされる
。使用されるレーザ゛は透明導電膜（３）（３ｍ、−用
晶質゛１′：導体膜＜４＞（４） と同様波！ １．０
６ ／Ａ ｍのＮｄ：ＹＡＧレーザであり、ｘ ｙ ｚ
スＴ−ノ（６）Ｑ）Ｘ軸方向の移動により５Ｑｍｍ ／
５ｅｃｏ′）速度で走査される。Does the adjacent spaced portion of the back electrode film (5) continue? In the process shown in Δ10, the extended portions (5a) (5a
)... are adjacent photoelectric conversion regions <2> (2) exposed portions (3a >(3a') of the transparent conductive film <3) (3)...
)... and the bonding distance is removed by irradiation with a laser beam (8), and the interval (L3) is set at 50 pm.The laser used is a transparent conductive film (3) (3 m, -Crystalline ゛1': Same wave as conductor film <4> (4)! 1.0
6/A m Nd:YAG laser, x y z
(6) Q) 5Qmm / by moving in the X-axis direction
5eco') speed.
Ｘ軸）ｊ向の走査後の動作、即ち対物し・ス（９〉と被
加工面との対向距離の補正等に一ついＣは先のレーリー
バターニング（除去）工程と同しに一つき説明を割愛す
る。One C is used for the operation after scanning in the X-axis (X-axis) j direction, i.e., for correction of the opposing distance between the objective lens (9) and the workpiece surface. I will omit the explanation.
レーザビーム（８）の照Ｊ］、Ｉによる除去に際し、留
、はずへきは除去せんとする膜部分の下に他の膜か存在
しておれば、それに損傷を与えないことである。非晶質
シリコン系の非晶質半導体膜（４）のレーザビーム（８
）の加工しきい値密度は、約４×１０７Ｗ／ｃｉ′１１
２と透明導電膜（３）ノア Ｘ １０’Ｗ ／ ｃｒｎ
２よ゛ り小さいために、非晶質半導体膜（４）の除
去工程に於いてレーザビーム（８〉が透明導電膜（３）
を直撃したとしても損傷を与えない。When removing the film using the laser beam (8), if there is another film under the film to be removed, it is important not to damage it. Laser beam (8) of amorphous silicon-based amorphous semiconductor film (4)
) processing threshold density is approximately 4×107W/ci'11
2 and transparent conductive film (3) Noah X 10'W/crn
Because it is smaller than 2, the laser beam (8) is applied to the transparent conductive film (3) during the removal process of the amorphous semiconductor film (4).
Even if it hits directly, it will not cause any damage.
然し乍ら、裏面電極膜（５）を形成可能な材料、即ち非
晶質半導体膜（・１）とオーミ／り接触する金属は加工
しきい値エネルギ密度か透明導電膜（３）のそれより高
いのが一般的である。例えはアルミニウムにあっては、
該アルミニウムはレーザビーｌ、の吸収率が低く、熱伝
導が優れているため（コシ・−ザビームの照射熱が散逸
する結果、膜厚にも左右きれるが５０００人に於いて約
８ Ｘ １０７Ｗ ／ ｃＩＴＩ ’と透明導電膜く３
）のそれに比して僅かながら高い値を示す。However, the material that can form the back electrode film (5), that is, the metal that is in ohmic contact with the amorphous semiconductor film (1), has a processing threshold energy density higher than that of the transparent conductive film (3). is common. For example, in the case of aluminum,
Since the aluminum has a low absorption rate for laser beams and excellent thermal conductivity (as a result of the dissipation of the irradiated heat of the laser beam, it has a power consumption of about 8 ' and transparent conductive film 3
) shows a slightly higher value than that of .
そこで本発明にあっては裏面電極膜（５）をアルミニウ
ム単体で構成するのではなく、照射熱の散逸を少なくす
へくアルミニウムの膜厚を約数１００人と肉薄にすると
共に、厚み５０００人程度０吸収率の高い材料、例えば
チタン或いはチタン銀合金を表面に積層するこ七によっ
て加工しきい値」−不ルギ密度を２ Ｘ １０’Ｗ／印
２と低減上しめている。よた裏面電極膜（５）を上記チ
タン或いはチタンζ１（合金単独で構成・しても良い。Therefore, in the present invention, the back electrode film (5) is not made of aluminum alone, but the thickness of the aluminum film is reduced to about 100 to reduce the dissipation of irradiated heat, and the thickness is reduced to about 5,000. By layering a material with a high degree of absorption on the surface, such as titanium or a titanium-silver alloy, the processing threshold density is reduced to 2 x 10'W/mark 2. The back electrode film (5) may be made of titanium or titanium ζ1 (alloy) alone.
（へ） 発明の効果
本発明は以上の説明から明らかな如く、基板の非平面状
絶縁表面に直接被着される膜状の光電変換領域に対し、
上記曲面の稜線と平行にＪ−ネルレキれ等の隣接間隔を
極めて減縮した状態で複数の領域に曲面に沿って分割す
ることができ、発電に寄５−する有力面積の上昇が図れ
る。(f) Effects of the Invention As is clear from the above description, the present invention provides a film-like photoelectric conversion region that is directly adhered to a non-planar insulating surface of a substrate.
It is possible to divide the area into a plurality of areas along the curved surface while keeping the adjacent spacing between the J-shaped grooves parallel to the ridgeline of the curved surface extremely small, thereby increasing the effective area contributing to power generation.
図は本発明の実施例を示し、第１図は本発明製造方法に
より製造される光起電力装置の斜視図、第２図は第１図
に於けるＡ−Ａ’線断面図、第３図、第６図、及び第８
図乃至第１０図番Ｊｖ造上程を順次説明するための要部
拡大断面図、第４図はレーザパターニング（除去）工程
の概略的斜視図、第５図は非晶質半導体の被着（形成）
工程の第１実施例を示す概略的斜視図、第７図は非晶質
半導体の被着（形成）工程の第２実施例を示す概略的斜
視図である。 ５
（１） ・基板、（２）・・光電変換領域、（４）・
非晶質半導体膜、（６）・・・ＸＹｚステージ、（８）
・・レーザ５ビーム、（１０）・・・アース電極、（１
２）・・高周波電極。The figures show embodiments of the present invention; FIG. 1 is a perspective view of a photovoltaic device manufactured by the manufacturing method of the present invention, FIG. 2 is a cross-sectional view taken along line A-A' in FIG. Figures 6 and 8
Figures 10 to 10 are enlarged sectional views of important parts for sequentially explaining the Jv fabrication process, Figure 4 is a schematic perspective view of the laser patterning (removal) process, and Figure 5 is amorphous semiconductor deposition (formation). )
FIG. 7 is a schematic perspective view showing a first embodiment of the process, and FIG. 7 is a schematic perspective view showing a second embodiment of the amorphous semiconductor deposition (formation) process. 5 (1) ・Substrate, (2) ・Photoelectric conversion region, (4) ・
Amorphous semiconductor film, (6)...XYz stage, (8)
... Laser 5 beam, (10) ... Earth electrode, (1
2)...High frequency electrode.
Claims (1)
膜状の光電変換領域を、エネルギビームの照射により上
記曲面の稜線と平行にバター−ングし、複数の光ＩＦ変
換領域に分割することを特徴とした光起電力装置の製造
方法。(1); A film-like photoelectric conversion region directly adhered to the non-planar insulating surface of the ISi plate is buttered parallel to the ridgeline of the curved surface by irradiation with an energy beam to form a plurality of optical IF conversion regions. A method for manufacturing a photovoltaic device characterized by dividing it.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58168762A JPS6059786A (en) | 1983-09-12 | 1983-09-12 | Manufacture of photovoltaic device |
| FR8412006A FR2550007A1 (en) | 1983-07-29 | 1984-07-27 | Method for producing a semiconducting film and photovoltaic device obtained by the method |
| US06/899,789 US4670293A (en) | 1983-07-29 | 1986-08-22 | Method of making semiconductor film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58168762A JPS6059786A (en) | 1983-09-12 | 1983-09-12 | Manufacture of photovoltaic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6059786A true JPS6059786A (en) | 1985-04-06 |
| JPH0548633B2 JPH0548633B2 (en) | 1993-07-22 |
Family
ID=15873966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58168762A Granted JPS6059786A (en) | 1983-07-29 | 1983-09-12 | Manufacture of photovoltaic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059786A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115376A (en) * | 1979-02-26 | 1980-09-05 | Shunpei Yamazaki | Semiconductor device and manufacturing thereof |
| JPS5712568A (en) * | 1980-06-02 | 1982-01-22 | Rca Corp | Method of producing solar battery |
| JPS57176778A (en) * | 1981-03-31 | 1982-10-30 | Rca Corp | Solar battery array |
| JPS5811261U (en) * | 1981-07-14 | 1983-01-25 | 長島 正彦 | tile |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5811261B2 (en) * | 1980-04-11 | 1983-03-02 | 新日本製鐵株式会社 | Method for forming thermal spray coating containing solid lubricant |
-
1983
- 1983-09-12 JP JP58168762A patent/JPS6059786A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55115376A (en) * | 1979-02-26 | 1980-09-05 | Shunpei Yamazaki | Semiconductor device and manufacturing thereof |
| JPS5712568A (en) * | 1980-06-02 | 1982-01-22 | Rca Corp | Method of producing solar battery |
| JPS57176778A (en) * | 1981-03-31 | 1982-10-30 | Rca Corp | Solar battery array |
| JPS5811261U (en) * | 1981-07-14 | 1983-01-25 | 長島 正彦 | tile |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0548633B2 (en) | 1993-07-22 |
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