JPS6059774A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6059774A JPS6059774A JP16889883A JP16889883A JPS6059774A JP S6059774 A JPS6059774 A JP S6059774A JP 16889883 A JP16889883 A JP 16889883A JP 16889883 A JP16889883 A JP 16889883A JP S6059774 A JPS6059774 A JP S6059774A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wirings
- wiring
- pattern
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000463 material Substances 0.000 claims abstract description 4
- 230000001681 protective effect Effects 0.000 claims description 12
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 238000006073 displacement reaction Methods 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 4
- 229910052782 aluminium Inorganic materials 0.000 abstract 4
- 239000011521 glass Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体基体表面の金属配線パターンの特に太
い部分において、適当な形状及び寸法で配線″ターンの
一部を取り除く配線構造に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a wiring structure in which a part of a wiring turn is removed in a particularly thick part of a metal wiring pattern on the surface of a semiconductor substrate in an appropriate shape and size.
従来例の構成とその間ＨＨｑ点
集積回路装置の高伺加価イ１ｌ１１化、高集積に伴い、
半導体装置の大電力化が生じており、半導体装置の電源
端子から、内部回路を駆動するために供給する電流量も
増加している。この電流を取り込むＱ：：Ｉ子及び内部
回路配線は、一般にＡ７！もしくはＭ合金材料で構成さ
れている。一方、Ａｌ配線の、１′１容電流電流密設泪
上では０６〜１ｍＡ ／ ／／ ｍ’：＋は決、Ｖ）ら
れており、電流の増加に伴っ一１ｒＡｆ！配線の断面積
を犬きくする必要が生じる。しかじＡｌ配線の厚さが、
一定と考えた場合、電流量↓１１を増すためにはＡｌ配
線幅を広くする必要が生じる・！、／こ、線幅を広げず
に電流容瓜を増ずにはＡｌ配線を厚くしなければならな
い。The structure of the conventional example and the HHq-point integrated circuit device are becoming more expensive and more integrated.
2. Description of the Related Art Semiconductor devices are becoming more powerful, and the amount of current supplied from a power supply terminal of a semiconductor device to drive an internal circuit is also increasing. The Q::I element and internal circuit wiring that take in this current are generally A7! Or it is made of M alloy material. On the other hand, on the 1'1 capacitance current of the Al wiring, the current is 06~1 mA/// m': + is determined, V), and as the current increases, -1rAf! It becomes necessary to increase the cross-sectional area of the wiring. However, the thickness of the Al wiring is
Assuming that it is constant, in order to increase the current amount ↓11, it is necessary to widen the Al wiring width! ,/The Al wiring must be made thicker without increasing the line width or increasing the current capacity.
上記の二つの方法で大電力半導体装置を達成する場合、
次のような問題が生じる。When achieving a high power semiconductor device using the above two methods,
The following problems arise.
その一つは、Ａｌ配線がその上を酸化＋１１４や窒化膜
等のガラス質表面保護膜で覆われて保護されており、一
般にこれら保護膜は、ＣＶＤ、スパッター、プラズマ、
陽極酸化等で形成されるが、月別の有する熱膨張係数の
違いから５表面保護膜を破壊して特に耐湿性における品
質劣化を生じる。この機構はＡｌ配線上にガラス質表面
保護膜を形成して、室温にもどる時に、Ａ７配線とガラ
ス質表面保護膜が有する上記熱膨張係数の違いによって
歪を生じ、異種の材料の接している距離が長くなれば、
大きな変位として現れる。こうして、 Ａｌ配線とガラ
ス質表面保護膜との変位の差がその界面で剪断歪を生じ
る原因となる。そしてＡｌ配線の変位に追従できないノ
ｆ ７ス質表面保ぬ膜は、特にＡｌ配線段差近傍で集中
応力を発生して、ガラス質表面保護膜のクラック′、今
の形で破壊に至る。One is that the Al wiring is protected by being covered with a glassy surface protective film such as +114 oxide or nitride film, and these protective films are generally coated with CVD, sputtering, plasma,
It is formed by anodic oxidation, etc., but due to the monthly difference in thermal expansion coefficient, the 5 surface protective film is destroyed, resulting in quality deterioration, especially in moisture resistance. This mechanism forms a glassy surface protective film on the Al wiring, and when it returns to room temperature, distortion occurs due to the difference in thermal expansion coefficient between the A7 wiring and the glassy surface protective film, and the contact between different materials occurs. If the distance is long,
Appears as a large displacement. Thus, the difference in displacement between the Al wiring and the glassy surface protective film causes shear strain at the interface. A film that cannot follow the displacement of the Al wiring, which does not maintain a high quality surface, generates concentrated stress especially in the vicinity of the step of the Al wiring, leading to cracks in the glassy surface protective film and destruction in the present form.
以下に」二記理由を説明する簡単な式を（１） 、 （
２ｊ式に示す。Below is a simple formula that explains the reason stated in (1), (
It is shown in formula 2j.
△Ｅ＝（ａＭ−（ｌｐ ）△Ｔ ・・・・（１）Ｄ二ａ
△Ｅ ・ ・ （２）
△Ｅ：熱収縮による歪
ａＭ ：配線Ｈ制の膨張係数
σＰ ：表面保護膜の膨張係数
△Ｔ ：膜形成時温度と＆！ ７’ｒ：’ｔのｉ６Ｄ
：変位
ａ ：配線幅の土 の長さ
もう一方の、Ａｌ配線の厚みをｒ−１？、 くする方法
は高集稍化に伴う徽細化パターンを達成するために、厚
さに制約が課せられる。寸たＡ４配線端での段差を大き
くすると、ガラス質表面保護膜の段差部での膜厚が薄く
なったり、段切れを生じたりする。△E=(aM-(lp)△T...(1)D2a
△E ・ ・ (2) △E: Strain due to thermal contraction aM: Expansion coefficient of wiring H system σP: Expansion coefficient of surface protective film △T: Temperature during film formation and &! 7'r:'t's i6D
:Displacement a :Length of wiring width R-1 thickness of the other Al wiring? However, in order to achieve finer patterns due to higher density, restrictions are imposed on the thickness. If the step difference at the end of the A4 wire is increased, the thickness of the glass surface protective film at the step portion becomes thinner or step breakage occurs.
等の問題を生じた。This caused problems such as:
発明の目的
本発明は上記のような従来例にみられた問題を解消する
もので、特に熱膨張特性に関して強い配性を有する大電
流容量のＪ’配線構造を備えた半導体装置を提供するも
のである。OBJECTS OF THE INVENTION The present invention solves the above-mentioned problems seen in the conventional examples, and provides a semiconductor device having a J' wiring structure with a large current capacity and having strong alignment with respect to thermal expansion characteristics. It is.
発明の構成
不発明はカラス質入面保護ルカの一トにある電（”（（
＋４配線の幅内に７．１．ｌ）寸たは隙間状の配線Ａシ
斜除去部分を設けた配線構造である。これによシ、Ｊｆ
：：ｊヤ隙間状バクーンを適当にｌ記ｔＫｆｆｉして変
位か小さくなることを利用した熱膨張吸収効果をもった
ものが実現される。Structure of the invention
7.1 within the width of +4 wiring. l) This is a wiring structure in which a diagonal removed portion of wiring A is provided in the form of a gap or gap. Good luck with this, Jf
::j By suitably adjusting the gap-shaped bag, a thermal expansion absorbing effect utilizing the reduction in displacement can be realized.
火旋例の説ｎ）ｊ
以下、本発明を、図面の火が１例を参照して、訂しく述
べる。Theory of Fire Spiral Example n)j The present invention will be described in detail below with reference to an example of fire swirl in the drawings.
図面は本発明の要部を示す外観斜視図の第１１ン［とそ
の断面図の第２図であり、表ｉｉ’＋ｉ保護膜１、Ａｅ
配線２、層間絶縁膜３、熱酸化膜４、半導体基体５で形
成されている。また表面保護膜１は、ガラス質の酸化膜
、あるいは窒化０３１である。The drawings are No. 11 of an external perspective view showing the main parts of the present invention and FIG.
It is formed of wiring 2, interlayer insulating film 3, thermal oxide film 4, and semiconductor substrate 5. Further, the surface protection film 1 is a glassy oxide film or a nitrided 031 film.
線幅の広いＡ ｌ １１１ｉ！線２と１≧によるガラス
質表面保護＋１＜Ｉのクラ、りを防止する／Ｃめに、配
線内部には隋（間６と７１１１冒〕（７とのＪＪ、−１
込みパターンをイＪするものである。この人きさと、間
隔は、Ａｅ配線２幅の広さと、長さ、及びガラス質表面
保護膜１の膜ｊ！？１、利質を勘案して決めることがで
きる。A l 111i with wide line width! Glassy surface protection by wires 2 and 1≧+1<I, to prevent cracking/C, inside the wiring
This is a pattern that includes patterns. This personality and spacing are determined by the width and length of the Ae wiring 2, and the film of the glassy surface protective film 1! ? 1. You can decide based on interest rate.
この人４配線２の隙間６や’１１’ｌｒ ７のパターン
の形成は、Ａｅ配線２のパターン形成１１．１ｊに、同
１時に行なう。The formation of the pattern 11.1j of the gap 6 and '11'lr 7 of this person 4 wiring 2 is performed at the same time as the pattern formation 11.1j of the Ae wiring 2.
光ＩＩＩ］の効果
本発明によれば、Ａｌ配線内に’）１’；：＋当な間１
原あるいは溝を設けるととて、ガラス）質人面保１免１
挽との間で生ずる歪による保を膜の変位を緩和してクラ
ックを防止することができ、Ｊ、たＩ１１匁厚全厚ぐす
ることもないので酬湿面での信頼性もそこなわずに済む
。さらに、上記パターンをｊｒＦＦ当に配置することで
、ｈ４配線の下のＬ′４間絶縁膜内と」二のガラス質表
面保１逆膜内のＡｄによる残留応力も小さくできて、半
導体装置の特性面での悪影響を小さく４甲えることがで
きる。According to the present invention, ')1';:+1 for the time being in the Al wiring.
If you create a hole or a groove, glass) Pawn's face preservation 1 exemption 1
It is possible to prevent cracks by alleviating the displacement of the film due to distortion that occurs between the ground and the J, I11 momme thickness, so there is no loss in reliability in terms of humidity. It ends up being Furthermore, by arranging the above pattern at the jrFF, the residual stress due to Ad in the L'4 insulating film under the h4 wiring and the second glass surface insulation film can be reduced, thereby reducing the stress of the semiconductor device. The negative effects on characteristics can be minimized by 4 times.
【図面の簡単な説明】
第１図、第２図はそれぞれ本光明欠施例の電１．鉤配線
パターン図の１折面図である。
１・・・・・・ガラス質表面保護膜、２− Ａｌ配線、
３・・・・・層間絶縁膜、４ ・−熱酸化膜、５・・・
・・半導体基体、６・ 隙間状パターン、７・・・・島
状パターン。[Brief Description of the Drawings] FIGS. 1 and 2 are diagrams showing the electric power 1 of the present embodiment. It is a 1-fold view of the hook wiring pattern diagram. 1... Glassy surface protective film, 2- Al wiring,
3...Interlayer insulating film, 4...Thermal oxide film, 5...
...Semiconductor substrate, 6. Gap pattern, 7.. Island pattern.
Claims (2)
線の幅内に、荷または隙間状に配線材料除去部を有する
ことを特徴とする半導体装置。(1) A semiconductor device characterized by having a wiring material removal portion in the shape of a gap or a gap within the width of an electrode wiring disposed under a surface protective film of the semiconductor device.
脣’＋晶求の範囲第１項に記載の半導体装置。(2) The electrode wiring is made of Al or A4 alloy coating.
The semiconductor device according to item 1, in which the range of 脣' + crystal demand is included.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16889883A JPS6059774A (en) | 1983-09-13 | 1983-09-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16889883A JPS6059774A (en) | 1983-09-13 | 1983-09-13 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6059774A true JPS6059774A (en) | 1985-04-06 |
Family
ID=15876606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16889883A Pending JPS6059774A (en) | 1983-09-13 | 1983-09-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6059774A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6424844U (en) * | 1987-08-04 | 1989-02-10 | ||
| US5101261A (en) * | 1988-09-09 | 1992-03-31 | Texas Instruments Incorporated | Electronic circuit device with electronomigration-resistant metal conductors |
| US5185651A (en) * | 1989-07-14 | 1993-02-09 | U.S. Philips Corporation | Integrated circuit with current detection |
| US5289036A (en) * | 1991-01-22 | 1994-02-22 | Nec Corporation | Resin sealed semiconductor integrated circuit |
| US5402005A (en) * | 1989-01-20 | 1995-03-28 | Kabushiki Kaisha Toshiba | Semiconductor device having a multilayered wiring structure |
-
1983
- 1983-09-13 JP JP16889883A patent/JPS6059774A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6424844U (en) * | 1987-08-04 | 1989-02-10 | ||
| JPH0723958Y2 (en) * | 1987-08-04 | 1995-05-31 | 日本電気アイシーマイコンシステム株式会社 | Semiconductor device |
| US5101261A (en) * | 1988-09-09 | 1992-03-31 | Texas Instruments Incorporated | Electronic circuit device with electronomigration-resistant metal conductors |
| US5402005A (en) * | 1989-01-20 | 1995-03-28 | Kabushiki Kaisha Toshiba | Semiconductor device having a multilayered wiring structure |
| US5185651A (en) * | 1989-07-14 | 1993-02-09 | U.S. Philips Corporation | Integrated circuit with current detection |
| US5289036A (en) * | 1991-01-22 | 1994-02-22 | Nec Corporation | Resin sealed semiconductor integrated circuit |
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