JPS6059387A - Display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a display circuit in a character image information system such as Teletext or Videotex.

BACKGROUND TECHNOLOGY AND PROBLEMS First, the outline of a general television teletext receiver will be explained with reference to FIG.

In FIG. 1, (1) shows a tuner circuit including a high frequency tuning circuit to a video detection circuit, (2) a video circuit that performs processing such as color demodulation, and (3) a color picture tube. When receiving normal television broadcasts, the tuner circuit (1
) is supplied to the video circuit (2) to extract the three primary color signals, and this signal is sent to the picture tube (3).
color images are reproduced by °ζ broadcasting.

At this time, the color video signal from the tuner circuit (1) is supplied to the synchronization pulse forming circuit (4), and the vertical synchronization pulse VD, horizontal interphase pulse HD, and clock CK are taken out, and the pulses V, , HD is fed to a deflection circuit (5) to form vertical and horizontal deflection currents, which are fed to the deflection coil (6) of the picture tube (3).

Further, 00) indicates a microcomputer for generating color images from teletext broadcasts, (11) an 8-hit parallel processing CPU, and (1z) a microcomputer for reproducing color images from teletext broadcasts. Written ROM, (13) is RAM for work area, (14)
is a keyboard for selecting teletext, etc., and (15) is an interface for analog human power, and these times + 73 (
12) to (15) are CP through system hash (19)
Connected to U(11).

Furthermore, (18) is a memory for the table file, and (17) is a video RAM for storing data for one page (one screen) of teletext broadcasting. A memory that forms its address signals, read/write signals, etc.:J
71-rat-ra (L8) is a display controller, which are connected to each other and to the system controller (19). Also, the controller (
17) are supplied with pulses Vo, Hl) and CK.

Then, when teletext is selected using the keyboard (14), this is notified to the CPU (11) by an interrupt.
Which teletext broadcast is needed is stored in the RAM (13).

On the other hand, the color video signal from the tuner circuit (1) is supplied to the interface (15), the teletext signal in the vertical blanking period is extracted, this signal is sent to the interface (15) at once, and the teletext signal in the vertical blanking period is extracted. The CPU (11) is notified by an interrupt that the broadcast signal has been buffered. Then, the CPU (11) checks whether it is the buffered teletext signal or the signal of the page selected with the keyboard (14), and if it is not the signal of the page selected with the keyboard (14). Ignored, but the keyboard (1
When the signal is for the page selected in step 4), the buffered teletext signal is processed by the CPU (11) and supplied to the video RAM (16), and the write address signal and write signal are sent from the CPU (11). It is supplied to the RAM (16) through the controller (17).

In this way, the number of characters selected on the keyboard (14) is sent 1
The display data of the bow is transferred to M (16) by the CPU (11) one scanning line at a time. Ru.

At this time, the controller (17)
A 1j7e protrusion address signal and a read signal synchronized with Jj direct scanning and horizontal scanning are formed, and these signals are supplied to the memory (16) in a time-sharing manner and are displayed on the RAM (16). The data is h! synchronized with vertical and horizontal scanning. 11th a) 'i ell is output, and this read display data is sent to the controller 1-1:I-S (18
) are decoded into three primary color signals R, G, B and a luminance signal Y.

And these (ij' bow-R-Y are connected to the video circuit (
It is supplied to the picture tube (3) through the picture tube (3) through the picture tube (2), and therefore a 4Q color image by teletext is generated in the picture tube (3).

Furthermore, when a page is sent via TV teletext,
In the standard V$ mall', one page is shown in Figure 2A as 24', and each field has 248 dots x
It consists of 204 vertical dots, and the "
The other 12 lines are used as a header section and are used for displaying indexes, etc. Also, on one page, 8 dots and 7 dots in the horizontal direction are displayed using l hide display data, so
Target ¥! To receive one page of the mode, the video RAM (16) is set to 3 as a horizontal address, as shown in Figure 2B.
Address 1 and address 204 are required as the vertical address.

By the way, in such a receiver, when data specifying a page etc. is input from the keyboard 1" (14), it is necessary to display (echo hack) the key data on the first page of i! For this reason, generally, the key manual data is stored in an area KDA of 120 dots horizontally x 12 dots vertically on the right side of the header section, as shown in FIG. 2A.
I try to keep my eyes open.

However, when doing this, the area KD is
The original header information displayed in A will disappear, so if you cancel the key input, or when all key input is completed, the display of that key input data will be deleted and the original header information will be returned to the display. There is a need.

However, in order to keep the display of the header section from returning to its original state, it is necessary to update the contents of the video RAM (16) using software. It will take a while.

Furthermore, until the rewriting is completed, the personal data and the original header information are mixed and displayed in a ζ table, making the display unsightly.

Therefore, apart from the video RAM (16), a buffer with the same content as the header section is saved, and the header information (.14 is also included in this buffer section). It has also been considered to determine 16 points. However, if the method
6) Not only does it intrude into the original display area, but it also intrudes into the buffer memory, which has the drawback of requiring extra processing.

Purpose of the Invention This invention solves one of these problems. II L.

SUMMARY OF THE INVENTION Therefore, in the present invention, a buffer memory having the same capacity as the display area KDA for key human input data is provided, and the key human input data is written into this buffer memory. Then, only when displaying that key manual data, the video RAM (
16), the buffer memory is read out for display instead of the address corresponding to the area KDA.

In other words, FIG. 3 shows one example. In this example, for simplicity, the CPU (li) simply stores display data and key input data into the video RAM (16) and buffer memory at CPU timing. Suppose that

In FIG. 3, the video RAM (16) has a capacity of 21' bytes for displaying the standard mode screen, and its addresses are allocated as shown in FIG. 4. Zunawaji, in Figure 4, the area DSP is the area used to display the page that is also blank in Figure 2B, and D4 is the horizontal address to the tenth address (address bit). This will be the range of addresses 0 to 30, and D5 to ΔD12 will be vertical to the binary address.
This address ranges from 0 to 203.

Follow-9, AD.

to D4 − “16J ~ “30”, and
Area RHA of 8 D5 to D12-1-0'' to 111''
corresponds to the key human data display area KDA.

Furthermore, in the above example, a part of the unused area of the video RAM (16) is used as a sofa memory for key human data.
116''~r30J', and to D5~8D12 =
-1-' 224J to 1-235J area BUF is used as its buffer memory. Note that in FIG. 4, the shaded portions are not used.

Furthermore, in FIG. 3, (21) shows a circuit for forming a horizontal address signal for reading. This formation circuit (21)
is composed of a frequency dividing circuit M3 and a 5-bit (-) counter, etc., and the digital clock CK is supplied to the clock manual (counting manual) CLK, and the
The valid display period or "1" within one horizontal period is
When the pulse II l] S P is supplied to the clear manual CLR, as shown in FIG.
A horizontal address signal Ho''H4 is formed which increments by 1-1'' every 8 K clocks.

Furthermore, in this forming circuit (21), the signal Ho
” A read signal RD and a load signal LD are generated every time H4 changes.

Further, (22) includes a circuit for forming a vertical address signal for reading. This forming circuit (23) is constituted by an 8-hit counter, etc., and the pulse lID5P is supplied to the clock power (count power) CLK.
As shown in Figures A and B, the pulse VDSP is cleared manually when there is no valid table period or "1°" within one field period.
As shown in FIG.
-1" vertical address signal VO~
■7 is formed.

Further, (23) blocks a circuit for forming an address signal for reading out when displaying key manual data.

In this example, this formation circuit 1+'8 (23) is constituted by a pull-up resistor R23, and address signals U5 to U7 of a level of 1'' are formed at an angle of 1.degree. Note that when displaying key manual data, there are many readout address signals in addition to the signal '41J5''/Ut.

1. (Signal) is necessary, but please trust me.”
-H4.

■o~■1 are also used (i'tY details will be described later).

In addition, (24) and (25) block the decoder, and the decoder (24) receives No. 14 Ho to H from the forming circuit (21).
4 is supplied and the 5th diagram is closed, so Ho~H4=r1
6J~[Decode signal becomes 1” when 30J HK Y
However, as shown in FIG. 7, the signal H becomes "°1" during the scan 11L period of the area KDA in the horizontal scan period.
KY is taken out. Furthermore, the decoder (25) receives the signals Vo~■7 from the forming circuit (22) and the signal VDS.
P is supplied (as shown in the sixth diagram, VDSP = ”
1”) during the period Vo ~ V? = 1-
Decode signal VK becomes “1°” when 0” to IIIJ
Y, that is, as shown in FIG. 7, after the vertical scanning period, the signal VKY becomes "1" during the scanning period of area KDA.
(Actually, there is a time delay due to signal processing after RAM (16), so the signal HK Y is extracted from the area K
(The position is earlier than the horizontal scanning period of DA).

Furthermore, (26) shows an RS flip-flop (latch), which is connected to the system hash (19) and is connected to the area K
DA is highlighted when the original input information is displayed on A, and set when key manual data is displayed, and its output Q26 is taken out.

And then, formation episode II! Signal from 8 (22) ■5 to ■7
is supplied to the input A o "A2 of the selector (31), and the signals U5 to U7 from the forming circuit (23) are supplied to the human power Bo"32 of the selector (31), and ~ (26) output signal HK Y, V KY
, Q2e are supplied to the AND circuit (27), and its AND output Q2? is supplied to the selection power S of the selector (31), and its selection output Y o -Y2 is supplied to the input B+o''Bx2 of the selector (32).

Furthermore, (j)"l;-V O from the formation circuit (22)
~ ■ Now is supplied to human power B5 ~ I39 of selector (32), and -1 to signal Ho from formation time 11!8 (21,)
-1, + are supplied to the input Bo=B4 of the selector (32), and the 71- loading address signal from CI) U (11) is supplied to the human input A o ''A' x2 of the selector (32). , the memory write signal 1 is supplied from the CPU (11) to the selector S of the selector (32), and the output Yo to YX2 of the selector (32) is the video RA.
Address of M(16).

~ΔD12. In addition, the selector (31).

(32) is when S-“0゛′, Y-Δ, S゛-” 1
”, then Y=B is selected.

In addition, the data of the RAM (16) 1] 1 contains the CPU (
11), and a read signal RD is supplied from the ride forming circuit (21) to the ride human power RD. The data output DO4 of the RAM (16) is an 8-bit parallel manual serial output shift register (28
) is connected, 11. At the same time, the load force of this register (28) 1. A load signal LD and a clock CK from the formation circuit (21) are supplied to the clock input CLK and the clock input CLK.

According to such a configuration, when the flip-flop (26) is reset by the CPU (11), its output Q2
Since G becomes "0", the signal HK Y.

Q2 regardless of VKY? = "Q", therefore, signals V5 to V7 are taken out from the selector (31).

Since the display timing is MEWR-“1”, the signals ■5 to VT from the selector (31) and the signals HO to H4°Vo from the forming circuits (21) and (22)
~■4 is the address AD of the RAM (16) through the selector (32) in the relationship as shown in FIG.

~ AD12. At this time, the signal HO
~H4, Vo ~Vt are changing as shown in FIG. 5C and FIG. 6C, and since the read signal RD is supplied to the RAM (16), the address ( In the area DSP (FIG. 4), display data is read from addresses corresponding to horizontal and vertical scanning positions.

Then, this read display data is stored in the register (2
8) and is taken out in series one by one, thereby obtaining a standard heat screen brightness signal Y.

In other words, if Frisopf 1:J knob (26) is reset, the A1n area DSP of 17AM<16)
The display data is taken out as it is as the luminance signal Y, and therefore the '.soda information is displayed in the area KDA of the page.

On the other hand, the CPU (11)
6) is set, its output Q2+, becomes 1"'. However, when at least one of horizontal scanning and vertical scanning is not performed in line with area K I) A, the signal 1-IKY, Since at least one of VKY is "O", Q27-"0", and iI is "0", and video RAM (
Display data Bee Lh is output in the same manner as described above using signals Ho to H4 and Vo -VT for the area behind area DSI (16) except area RHA, and the luminance signal Y is extracted. . Zunawaji, Q2G-“1
'', display data is read out and displayed in the area DSP of the video RAM (16) other than the area RHA.

L2 mark, both horizontal scan and vertical scan are area K D
Since Q27 = "l" when the signal is being applied to A, signals U5 to U7 are taken out from the selector (31), and the signals □ U? And the signal ■.

~V4 and Ha-H4 are supplied to the video RAM (16) through the selector (32) in the relationship shown in FIG. At this time, the signal Vo"V4.

When U5 to U7 are viewed as one address signal, as shown in FIG. 6E, the signal changes from r224j to r235J every horizontal period during VKY="1". Then, these signals Vo −V4, U5 to U7 are the video R
The signals are supplied to the vertical addresses AD5 to 8D12 of AM (16), and the signals Ho to 1]4Kahiteo RAM<
16) are supplied to the horizontal addresses ADo to Alas.

Therefore, when horizontal scanning and vertical scanning are performed on area KDA? , Koba, area BUF of RAM (16)
Each time the data is read out by being addressed, the read data is used as the luminance signal Y.

That is, when the flip-flop (26) is set, the area KDA of one page has R
The data of area BU F of AM<16> is displayed, and 1
In the remaining area "C" of the page, the data of the area excluding areas RIi and A of the area DSP of the RAM (i6) is displayed.

Therefore, when displaying a teletext image, if the screen information including the header information is loaded into the area DSP of the video RAM (16) and the solve flop (26) is reset, the header information <-V All of the information on screen 11' including the above information is displayed normally.

And when you have the key manpower, flip-flop (
26) and the key manual data in RA.
If ¥1 is written into area B tJ F of M(16), the key manual data will be displayed in area K IJ A of the page. Furthermore, the teletext image 4) is displayed in the remaining page area.

Then, when all the key forces are finished or when the key forces are canceled, the Free Knob Flop (26
), the original header information is displayed in area KDA, and the original teletext screen is displayed.

Thus, according to the present invention, when the area KDA of the head/noda section is used for displaying key human power data, when there is no key human power, the original head/noda information can be displayed;
If you have key human power, you can display that key human power data, and when you no longer need to display the key human power data,
Although the original header/noder information can be displayed, the header information or key manual data only needs to be entered once, and furthermore, the header information or key manual data for the area KDA can be displayed simply by flip-flop (26). St.
Since the reset can be controlled, processing can be performed extremely easily, quickly, and instantaneously. and,
There is no increase in the load on the CPU (11) or an unsightly screen in which header information and key manual data are mixed.

Key Effects of the Invention After displaying the human-powered data, the original screen information can be displayed easily and instantaneously. In addition, screen information and key human data may be recorded for 1 hour: t > 1 degree.

[Brief explanation of the drawing]

1, 2, 4 to 1] are diagrams for explaining this invention, and FIG. 3 is a system diagram of an example of this invention. (16)' is a video RA'M, and (21) to (23) are address signal forming circuits. 8N Figure 9

Claims (1)

[Claims] In a display circuit, display data written in a display memory is read in correspondence with horizontal and vertical scanning, and the read display data is supplied to a picture tube and displayed as one page of images, A buffer memory with the capacity necessary to display the key human input data is provided, and when the key human input data is not displayed, ζ is read from the display memory to display the original screen information and the key human input data is displayed. At times, 3j6Jj is read out from the memory for the table 71e, and the key human data is read from the 1+knee+- batho memory during a period corresponding to the display area of the key human data on the display screen, A display circuit that displays the key manual data as part of the screen information.4