JPS6057972A - Insulated gate field effect transistor - Google Patents
Insulated gate field effect transistorInfo
- Publication number
- JPS6057972A JPS6057972A JP16590583A JP16590583A JPS6057972A JP S6057972 A JPS6057972 A JP S6057972A JP 16590583 A JP16590583 A JP 16590583A JP 16590583 A JP16590583 A JP 16590583A JP S6057972 A JPS6057972 A JP S6057972A
- Authority
- JP
- Japan
- Prior art keywords
- film
- dirt
- effect transistor
- polycrystalline silicon
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 230000000694 effects Effects 0.000 claims abstract description 5
- 238000009413 insulation Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000002356 single layer Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、絶縁ダート型％不効果トランジスタに関する
。DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to an insulated dart type percent ineffective transistor.
従来、絶縁ゲート型電界効果トランジスタのゲート１ｉ
Ｌ極とじ１は、砒素、鱈ｒロン等の不純物を含んだ多結
晶シリコン膜が使用されている。Conventionally, the gate 1i of an insulated gate field effect transistor
For the L-pole binding 1, a polycrystalline silicon film containing impurities such as arsenic and cod oxide is used.
而して、不純物は、例えはリンを拡散にＬクグートｔ＆
中に導入する場合扛、ダート電極中の不純物製度は、不
純物の拡散条件にもよるか一般には３ Ｘ １０ 〜５
ＸｌＯｃＩｎ の範囲で設足している。Therefore, impurities, for example, diffuse phosphorus,
When introducing the impurity into the dirt electrode, the degree of impurity concentration in the dirt electrode depends on the impurity diffusion conditions, but is generally 3 x 10 to 5.
It has been established within the range of XlOcIn.
また、そのゲート絶縁膜としては、厚さが２５０〜３０
０Ｘの二酸化シリコン族が一般に使用されている。近年
、集稼回路素子の微粗化を達成するために、ダート絶＃
膜である二酸化シリコン膜の膜厚も小さくする方向にあ
る。−万、ダート電圧は、ダート絶縁膜の膜厚の縮小率
に対応しては小さくならない。従うて、ダート電界（ダ
ート電圧／ダート絶縁膜圧）が大きくなる傾向にある。Moreover, the thickness of the gate insulating film is 250 to 30 mm.
OX silicon dioxide family is commonly used. In recent years, in order to achieve finer roughening of integrated circuit elements, dirt
There is also a tendency to reduce the thickness of the silicon dioxide film. - 10,000, the dart voltage does not decrease in accordance with the reduction rate of the film thickness of the dart insulating film. Therefore, the dart electric field (dart voltage/dart insulating film pressure) tends to increase.
〔背景技術の問題点〕
而して、ダート絶ＩＩｉ＆膜とダート電極である多結晶
シリコンの界面は、決して平坦ではなく、凹凸が存在す
る。この状態を図示したのが第１図である。図中１は、
例えはｐ形のシリコン基板である。３は、このシリコン
基板１上にダート絶縁膜２である二酸化シリコン膜を介
して積層された多結晶シリコン膜からなるダート電極で
ある。多結晶シリコン族中には、例えはリンが３ＸｌＯ
ｃｍ 含まれている。ダート絶縁膜２は、同図から明ら
かなように局所的に薄肉部分があり、その表面は凹凸部
４を有している。その結果、ダート絶縁膜２の耐圧が劣
化する問題があうた。[Problems with Background Art] Therefore, the interface between the dart electrode IIi& film and the polycrystalline silicon that is the dart electrode is not flat at all, but has irregularities. FIG. 1 illustrates this state. 1 in the figure is
An example is a p-type silicon substrate. Reference numeral 3 denotes a dirt electrode made of a polycrystalline silicon film laminated on the silicon substrate 1 with a silicon dioxide film serving as the dirt insulating film 2 interposed therebetween. In the polycrystalline silicon group, for example, phosphorus is
cm included. As is clear from the figure, the dirt insulating film 2 has locally thin portions, and its surface has uneven portions 4. As a result, the problem of deterioration of the breakdown voltage of the dirt insulating film 2 occurred.
なお、同図は、ゲート絶縁膜２とダート電極３との界面
の凹凸部４ｔ−見やすくするために、誇張して拡大した
状態で表現している。凹凸部４の高さは、ダート絶縁膜
２の約１０％である。Note that, in this figure, the uneven portion 4t at the interface between the gate insulating film 2 and the dirt electrode 3 is shown in an exaggerated and enlarged state in order to make it easier to see. The height of the uneven portion 4 is approximately 10% of the height of the dirt insulating film 2.
本発明は、ゲート絶縁膜の膜厚に左右されずに、耐圧の
向上を達成した絶縁ダート型［４効果トランジスタを提
供することをその目的とするものである。An object of the present invention is to provide an insulated dart type [4-effect transistor] which achieves improved breakdown voltage regardless of the thickness of the gate insulating film.
本発明は、ドナー濃度ＮＤまたはアクセプタ濃度Ｎムを
最適値に設足して、ｒ−ト絶縁膜の膜厚に左右されずに
、耐圧の同上を達成した絶縁ダート型電界効果トランジ
スタである。The present invention is an insulated dart type field effect transistor that achieves the same breakdown voltage without being affected by the thickness of the r-to insulating film by setting the donor concentration ND or the acceptor concentration N to an optimum value.
次に、本発明をリン拡散を施したゲート電極ｋｐ形シリ
コン基板上に設けたｎチャネル型の絶縁ダート型’Ｉｌ
ｌ効果トランジスタを例に挙げて詳述する。Next, the present invention will be described in which an n-channel insulated dart type 'Il' is provided on a kp-type silicon substrate with a gate electrode subjected to phosphorus diffusion.
This will be explained in detail using an L-effect transistor as an example.
第２図は、このトランジスタのダートに電圧Ｖｏを印加
したときのノ々ンドダイヤグラムを示している。図中１
１は、ｐ形シリコン基板、１２はダート絶縁膜、１３は
ダート電極である。電位は、第２図中の表面電位ψＢを
基準にして測定し、ダートに印加する電圧ＶＧは正とす
る。通常のトランジスタの場合、動作時にφＢはソース
電位に吟しい。FIG. 2 shows a node diagram when voltage Vo is applied to the dirt of this transistor. 1 in the diagram
1 is a p-type silicon substrate, 12 is a dirt insulating film, and 13 is a dirt electrode. The potential is measured based on the surface potential ψB in FIG. 2, and the voltage VG applied to the dirt is positive. In the case of a normal transistor, φB is equal to the source potential during operation.
このとき、ダート電極は、ｘｄの長さだけ空乏層ができ
る。このｘｄは次式（１）で表わされる。At this time, a depletion layer is formed in the dart electrode by a length xd. This xd is expressed by the following equation (1).
５−
ここで、
ε、は、ダート電極である多結晶シリコン膜の比誘電率
、
＃１ｉｊ、ダート絶縁膜の比誘電率
Ｃ０は、真空の誘電率で８．８６ Ｘ １０ Ｆ／ａｎ
Ｊは、ダート絶縁膜の厚さ
ｑは、素電荷で１．６ＸｌＯＣ
ＮＤは、ダート電極中の不純物の不純物製度Ｖｏは、ソ
ース電位を基準にして測定したダート電位でＶｏ ＞
Ｏとする。5- Here, ε is the relative permittivity of the polycrystalline silicon film that is the dirt electrode, #1ij, the relative permittivity C0 of the dirt insulating film is the vacuum permittivity of 8.86 x 10 F/an
J is the dirt insulating film thickness q is the elementary charge and is 1.6XlOC ND is the degree of impurity Vo of the impurity in the dirt electrode is the dirt potential measured based on the source potential Vo >
Let it be O.
このとき、ｘｄの大きさを二酸化シリコン膜と多結晶シ
リコン膜の界面の凹凸と同程度または、それ以上即ち、
二酸化シリコン膜の厚さの約ｌＯ−以上とすると、第３
図に示すようにダート絶縁膜２２の界面の凹凸部２６を
平坦化するように空乏層ができる。式（１）は、界面は
全く平坦な場合の式であるが、界面に凹凸部がある場６
−
合には、第３図に示すように空乏層がのび、式（１）で
与えられる×ｄは、おおむね空乏層の平均を与える。第
３図中２１はｐ形シリコン基板、２２はその表面に形成
された二酸化シリコン膜からなるダート絶縁膜、２３は
、ダート絶縁膜２２上に形成されたダート電極であり、
２４は空乏層、２５は空乏化していない領域である。At this time, the size of xd is set to be equal to or larger than the unevenness of the interface between the silicon dioxide film and the polycrystalline silicon film, that is,
If the thickness is approximately lO- or more than the thickness of the silicon dioxide film, the third
As shown in the figure, a depletion layer is formed so as to flatten the uneven portion 26 at the interface of the dirt insulating film 22. Equation (1) is for the case where the interface is completely flat, but if the interface has uneven parts6
- In this case, the depletion layer grows as shown in FIG. 3, and xd given by equation (1) roughly gives the average of the depletion layer. In FIG. 3, 21 is a p-type silicon substrate, 22 is a dirt insulating film made of a silicon dioxide film formed on the surface thereof, and 23 is a dirt electrode formed on the dirt insulating film 22.
24 is a depletion layer, and 25 is a non-depleted region.
このように空乏層の厚さＸ４がダート絶縁膜の厚さｔｉ
のおおむね１０％以上であれは、空乏層２４の存在によ
り電界を緩和することができる。In this way, the thickness of the depletion layer X4 is the thickness of the dirt insulating film ti
If it is approximately 10% or more, the electric field can be relaxed due to the presence of the depletion layer 24.
上述の条件を式で表わすと式（１）からとなる。さらに
式（２）の根号内金展開すると近似的に
とかけ、さらにこれをＮＤについて解くととなる。Expressing the above-mentioned conditions as an equation, it is as shown in equation (1). Furthermore, when formula (2) is expanded into a radical, it is approximately solved, and then this is solved for ND.
つまり、不純物ｌｌｉ度ＮＤを式（４）をみたすように
定めれは良い。なお、不純物濃度ＮＤがダート電極２３
内で一足という条件のもとで式（４）を導いたが、ＮＤ
が一定でないときは、Ｎｏとしてダート絶縁８２２とダ
ート電＆２３の界面における値を使用すれは良い。In other words, it is good to set the impurity degree ND so as to satisfy equation (4). Note that the impurity concentration ND is the dirt electrode 23
Equation (4) was derived under the condition that ND
When is not constant, it is better to use the value at the interface between dart insulation 822 and dart insulation &23 as No.
また、不純物としてドナーとアクセプタの双方が存在す
る場合は、
を満足すれば良い。ここで、ＮＤはドナー濃度、Ｎムは
アクセプタ濃度である。式（５）は、最も一般的な条件
である。Furthermore, if both a donor and an acceptor exist as impurities, the following may be satisfied. Here, ND is the donor concentration and N is the acceptor concentration. Equation (5) is the most general condition.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第３図は、本発明の一実施例の要部の拡大図である。こ
の実施例は、本発明ｉｎ−チャネル絶縁ダート型電界効
果トランジスタに適用したものである。図中２１は、ｐ
形のシリコン基板２１″″Ｃある。シリコン基板≧１上
には、９００℃の酸化界囲気中で厚さ１５０Ｘ形成され
た二酸化シリコン膜からなるダート絶縁膜２２が設けら
れている。ダート絶縁膜２２上には、多結晶シリコン膜
を厚さ３０００Ｘ堆積し、これに加速電圧４０ｋａＶ、
ドーズＪｔ８×１０１４ｃｔｎ−２の条件で砒素イオン
を注入してなるダート電極２３が設けられている。なお
、このダート電極２３のパターニング後に、通常のＭＯ
Ｓ ）ランジスタの製造プロセスに従りてソース、ドレ
イン電極等の形成が行われている。ソース、ドレインｉ
ｎへの不純物の導入は、ダート領域をマスクしてダート
領域の不純物濃度が高くならないようにして行りている
。FIG. 3 is an enlarged view of essential parts of an embodiment of the present invention. This embodiment is applied to an in-channel insulated dart type field effect transistor of the present invention. 21 in the figure is p
There is a shaped silicon substrate 21''C. A dirt insulating film 22 made of a silicon dioxide film formed to a thickness of 150× in an oxidizing atmosphere at 900° C. is provided on the silicon substrate≧1. A polycrystalline silicon film is deposited on the dirt insulating film 22 to a thickness of 3000×, and an accelerating voltage of 40 kaV is applied to this film.
A dirt electrode 23 is provided which is formed by implanting arsenic ions at a dose of Jt 8×10 14 ctn-2. Note that after patterning this dirt electrode 23, a normal MO
S) Source, drain electrodes, etc. are formed according to the transistor manufacturing process. source, drain i
The impurity is introduced into n by masking the dirt region so that the impurity concentration in the dirt region does not become high.
ダート１１極２３にイオン注入された砒素は、その後の
熱工程（例えは、窒素雰囲気中での１０００℃で４０分
程度のアニール）で、ダート電極２３内に＃１＃な一定
の濃度分布を呈している。この不純物ｌ１ｌ１１度ＮＤ
は、ＮＤ−２，６Ｘ １０”ｍ−３９−
程度に設定されている。The arsenic ion-implanted into the dirt 11 electrode 23 forms a constant #1# concentration distribution in the dirt electrode 23 through a subsequent thermal process (for example, annealing at 1000°C for about 40 minutes in a nitrogen atmosphere). It is showing. This impurity l1l11 degree ND
is set to approximately ND-2.6×10"m-39-.
このように構成された絶縁ダート型’ＩｔＲ効果トラン
ジスタを、ソース電圧を基準にしてダート電圧を５ｖに
設定して使用すると、上述の式（４）の右辺は次のより
になる＠
１０ｇ。ｇｌＶｏ １ＯＸ８．８６ＸｌＯＸ３．９Ｘ５
ｔ ｌｑ （１５０ＸＩＯ） Ｘｌ、６ＸＩＯ−１９−
４，８ＸＩＯ（ｏ＋＋ ）
つまり、ドナー濃度ＮＤは、２．６ＸｌＯａｎ （４，
８Ｘ１０ ｃｍ を満足する。この結果から明ら〃≧に
ｒ−ト絶縁膜２２の耐圧が向上することが判る。When the insulated dart type 'ItR effect transistor configured in this way is used with the dart voltage set to 5V with the source voltage as a reference, the right side of the above equation (4) becomes as follows @ 10g. glVo 1OX8.86XlOX3.9X5
t lq (150XIO) Xl, 6XIO-19-
4,8XIO(o++) In other words, the donor concentration ND is 2.6XIOan(4,
Satisfies 8x10 cm. From this result, it is clear that the withstand voltage of the r-to insulating film 22 is improved by ≧.
なお、本発明は、ｐ−チャネルの素子にも適用できるこ
とは勿論である。この場合には、シリコン基板としてｎ
形シリコン基板を使用し、多結晶シリコン膜中には、ホ
ウ素を注入する。It goes without saying that the present invention can also be applied to p-channel devices. In this case, as a silicon substrate, n
A polycrystalline silicon substrate is used, and boron is implanted into the polycrystalline silicon film.
また、ダート絶縁膜としては、窒化シリコン膜或は、窒
化シリコン膜と酸化シリコン膜の多層構造のものを用い
ても良い。Further, as the dirt insulating film, a silicon nitride film or a multilayer structure of a silicon nitride film and a silicon oxide film may be used.
また、ダート電極としては、金属膜や金属の１０−
硅化物換金多結晶シリコン膜上に積層したものを用いて
も良い。Further, as the dirt electrode, a metal film or a metal film laminated on a 10-silicide-converted polycrystalline silicon film may be used.
以上説すりした如く、本発明に係る絶縁ダート型電界効
果トランジスタによれは、ダート絶縁膜の膜厚に左右さ
れずに、耐圧の同上を達成できるものである。As explained above, the insulated dart type field effect transistor according to the present invention can achieve the same breakdown voltage regardless of the thickness of the dirt insulating film.
第１図は、従来の絶縁ダート型電界効果トランジスタの
ダートの近傍領域を示す拡大図、第２図は、本発明の原
理を示すバンドダイヤグラム、第３図は、本発明の絶縁
ダート型電界効果トランジスタのｒ−）の近傍領域を示
す拡大図である。
１．１１．２１・・・ｐ形シリコン基板、２゜ノ２，２
２・・・ダート絶縁膜、３，１３．２３・・・ダート電
極、２４・・・多結晶シリコン膜の空乏層、２５・・・
多結晶シリコン族の空乏化していない層。
出願人代理人 弁理士 鮎 江 武 彦１１−
第１図
第２図Fig. 1 is an enlarged view showing the area near the dirt of a conventional insulated dart type field effect transistor, Fig. 2 is a band diagram showing the principle of the present invention, and Fig. 3 is an insulated dart type field effect transistor of the present invention. FIG. 3 is an enlarged view showing a region near r-) of a transistor. 1.11.21...p-type silicon substrate, 2° no 2,2
2... Dirt insulating film, 3, 13. 23... Dirt electrode, 24... Depletion layer of polycrystalline silicon film, 25...
An undepleted layer of the polycrystalline silicon family. Applicant's representative Patent attorney Takehiko Ayue 11- Figure 1 Figure 2
Claims (1)
膜で形成されている絶縁ｆ−）製電外効果トランジスタ
において、ダート電極直下のダート絶縁膜と多結晶シリ
コン膜との界面近傍で該ダート電極を形成する多結晶シ
リコン膜中に含まれるアクセプタ原子密度’ｋ ＮＡ
ｔドナー原子密度をＮＤとし、絶縁膜の厚さをｔｌ、絶
縁膜の比誘電率をεｌ、真空の誘電率をε０．累電荷を
ｑ＝１、６ Ｘ １０ クーロン、ソースとダートの電
位差の絶縁値の最大値ヲｖＧとするとき、不等式を満足
することを特徴とする絶縁ダート型電界効果トランジス
タ。 （２）トランジスタのチャネルはｎ形であり、そのグー
）Ｗ極中にドナー原子を不純物とじて含有する特許請求
の範囲第１項記載の絶縁ダート製電外効果トランジスタ
。 （３ントランジスタのチャネルｒ、ｉ ｐ形であり、そ
のダート電極中にアクセプタ原子全不純物として含有す
る特許請求の範囲第１項記載の絶縁ダート型電界効果ト
ランジスタ。 （４） ダート電極は、多結晶シリコン膜の単層構造、
或は、金属膜または金属硅化物膜と多結晶シリコン膜の
複数層積層構造からなる特許請求の範囲第１項、第２項
、第３項の何れか記載の絶縁ダート型電界効果トランジ
スタ。 （５）ダート絶縁膜は、二酸化シリコン膜、窒化シリコ
ン膜、二酸化シリコン膜と窒化シリコン膜の二層構造体
の何れかである特許請求の範囲第１項、第２項、第３項
、第４項の何れか記載の絶縁ダート型電界効果トランジ
スタ。[Scope of Claims] (1) In an insulating f-) manufactured external effect transistor in which all or part of the dirt electrode is formed of a polycrystalline silicon film, the dirt insulating film directly under the dirt electrode and the polycrystalline silicon film are Acceptor atomic density 'k NA contained in the polycrystalline silicon film forming the dirt electrode near the interface of
The donor atom density is ND, the thickness of the insulating film is tl, the dielectric constant of the insulating film is εl, and the permittivity of vacuum is ε0. An insulated dart type field effect transistor characterized in that it satisfies the inequality where the accumulated charge is q = 1, 6 x 10 coulombs, and the maximum insulation value of the potential difference between the source and the dart is vG. (2) The external effect transistor made of insulating dirt as claimed in claim 1, wherein the channel of the transistor is n-type, and the W pole contains donor atoms as impurities. (The insulated dart type field effect transistor according to claim 1, wherein the channel r, i of the transistor is p-type, and the dirt electrode contains all acceptor atoms as impurities. Single layer structure of crystalline silicon film,
Alternatively, the insulated dart type field effect transistor according to any one of claims 1, 2, and 3, comprising a multilayer stacked structure of a metal film or a metal silicide film and a polycrystalline silicon film. (5) The dirt insulating film is any one of a silicon dioxide film, a silicon nitride film, and a two-layer structure of a silicon dioxide film and a silicon nitride film. 4. The insulated dart type field effect transistor according to any one of Item 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16590583A JPS6057972A (en) | 1983-09-09 | 1983-09-09 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16590583A JPS6057972A (en) | 1983-09-09 | 1983-09-09 | Insulated gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6057972A true JPS6057972A (en) | 1985-04-03 |
| JPH053147B2 JPH053147B2 (en) | 1993-01-14 |
Family
ID=15821221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16590583A Granted JPS6057972A (en) | 1983-09-09 | 1983-09-09 | Insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057972A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286084A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Field effect transistor |
| JPS5339083A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Production of silicon gate mis semiconductor device |
-
1983
- 1983-09-09 JP JP16590583A patent/JPS6057972A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286084A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Field effect transistor |
| JPS5339083A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Production of silicon gate mis semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH053147B2 (en) | 1993-01-14 |
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