JPH053147B2 - - Google Patents
Info
- Publication number
- JPH053147B2 JPH053147B2 JP58165905A JP16590583A JPH053147B2 JP H053147 B2 JPH053147 B2 JP H053147B2 JP 58165905 A JP58165905 A JP 58165905A JP 16590583 A JP16590583 A JP 16590583A JP H053147 B2 JPH053147 B2 JP H053147B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- polycrystalline silicon
- insulating film
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 230000005669 field effect Effects 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 14
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 claims 2
- 239000002356 single layer Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- -1 arsenic ions Chemical class 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、絶縁ゲート型電界効果トランジスタ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an insulated gate field effect transistor.
従来、絶縁ゲート型電界効果トランジスタのゲ
ート電極としては、砒素、ボロン等の不純物を含
んだ多結晶シリコン膜が使用されている。而し
て、不純物は、例えばリンを拡散によりゲート電
極中に導入する場合は、ゲート電極中の不純物濃
度は、不純物の拡散条件にもよるが一般には３×
1020〜５×1020cm-3の範囲で設定している。
Conventionally, a polycrystalline silicon film containing impurities such as arsenic and boron has been used as a gate electrode of an insulated gate field effect transistor. When an impurity, for example phosphorus, is introduced into the gate electrode by diffusion, the impurity concentration in the gate electrode is generally 3×, although it depends on the impurity diffusion conditions.
It is set in the range of 10 20 to 5×10 20 cm -3 .
また、そのゲート絶縁膜としては、厚さが250
〜300Åの二酸化シリコン膜が一般に使用されて
いる。近年、集積回路素子の微細化を達成するた
めに、ゲート絶縁膜である二酸化シリコン膜の膜
厚も小さくする方向にある。一方、ゲート電圧
は、ゲート絶縁膜の膜厚の縮小率に対応しては小
さくならない。従つて、ゲート電界（ゲート電
圧／ゲート絶縁膜厚）が大きくなる傾向にある。 In addition, the gate insulating film has a thickness of 250 mm.
~300 Å silicon dioxide films are commonly used. In recent years, in order to achieve miniaturization of integrated circuit elements, there has been a trend to reduce the thickness of a silicon dioxide film, which is a gate insulating film. On the other hand, the gate voltage does not decrease in accordance with the rate of reduction in the thickness of the gate insulating film. Therefore, the gate electric field (gate voltage/gate insulating film thickness) tends to increase.
而して、ゲート絶縁膜とゲート電極である多結
晶シリコンの界面は、決して平坦ではなく、凹凸
が存在する。この状態を図示したのが第１図であ
る。図中１は、例えばｐ形のシリコン基板であ
る。３は、このシリコン基板１上にゲート絶縁膜
２である二酸化シリコン膜を介して積層された多
結晶シリコン膜からなるゲート電極である。多結
晶シリコン膜中には、例えばリンが３×1020cm-3
含まれている。ゲート絶縁膜２は、同図から明ら
かなように局所的に薄肉部分があり、その表面は
凹凸部４を有している。その結果、ゲート絶縁膜
２の耐圧が劣化する問題があつた。
Therefore, the interface between the gate insulating film and the polycrystalline silicon serving as the gate electrode is never flat and has irregularities. FIG. 1 illustrates this state. In the figure, 1 is, for example, a p-type silicon substrate. Reference numeral 3 denotes a gate electrode made of a polycrystalline silicon film laminated on the silicon substrate 1 with a silicon dioxide film serving as the gate insulating film 2 interposed therebetween. For example, 3×10 20 cm -3 of phosphorus is present in the polycrystalline silicon film.
include. As is clear from the figure, the gate insulating film 2 has locally thin parts, and its surface has uneven parts 4. As a result, there was a problem that the withstand voltage of the gate insulating film 2 deteriorated.
なお、同図は、ゲート絶縁膜２とゲート電極３
との界面の凹凸部４を見やすくするために、誇張
して拡大した状態で表現している。凹凸部４の高
さは、ゲート絶縁膜２の約10％である。 Note that this figure shows the gate insulating film 2 and the gate electrode 3.
In order to make it easier to see the uneven portion 4 at the interface with the substrate, it is shown in an exaggerated and enlarged state. The height of the uneven portion 4 is approximately 10% of the gate insulating film 2.
本発明は、ゲート絶縁膜の膜厚に左右されず
に、耐圧の向上を達成した絶縁ゲート型電界効果
トランジスタを提供することをその目的とするも
のである。
An object of the present invention is to provide an insulated gate field effect transistor that achieves improved breakdown voltage regardless of the thickness of the gate insulating film.
本発明は、ドナー濃度NDまたはアクセプタ濃
度NAを最適値に設定して、ゲート絶縁膜の膜厚
に左右されずに、耐圧の向上を達成した絶縁ゲー
ト型電界効果トランジスタである。
The present invention is an insulated gate field effect transistor in which the donor concentration N D or the acceptor concentration N A is set to an optimal value to achieve an improvement in breakdown voltage regardless of the thickness of the gate insulating film.
次に、本発明をリン拡散を施したゲート電極を
ｐ形シリコン基板上に設けたｎチヤネル型の絶縁
ゲート型電界効果トランジスタを例に挙げて詳述
する。 Next, the present invention will be described in detail by taking as an example an n-channel type insulated gate field effect transistor in which a gate electrode subjected to phosphorus diffusion is provided on a p-type silicon substrate.
第２図は、このトランジスタのゲートに電圧
VGを印加したときのバンドダイヤグラムを示し
ている。図中１１は、ｐ形シリコン基板、１２は
ゲート絶縁膜、１３はゲート電極である。電位
は、第２図中の表面電位Sを基準にして測定し、
ゲートに印加する電圧VGは正とする。通常のト
ランジスタの場合、動作時にSはソース電位に等
しい。 Figure 2 shows the voltage applied to the gate of this transistor.
A band diagram is shown when V G is applied. In the figure, 11 is a p-type silicon substrate, 12 is a gate insulating film, and 13 is a gate electrode. The potential is measured based on the surface potential S in Figure 2,
The voltage V G applied to the gate is assumed to be positive. For a normal transistor, S is equal to the source potential during operation.
このとき、ゲート電極は、xdの長さだけ空乏
層ができる。このxdは次式(1)で表わされる。 At this time, a depletion layer is formed in the gate electrode by the length xd. This xd is expressed by the following equation (1).
ここで、
εSは、ゲート電極である多結晶シリコン膜の比
誘電率、
εiは、ゲート絶縁膜の比誘電率
εpは、真空の誘電率で8.86×10-14Ｆ／cm
tiは、ゲート絶縁膜の厚さ
ｑは、素電荷で1.6×10-19Ｃ
NDは、ゲート電極中の不純物の不純物濃度
VGは、ソース電位を基準にして測定したゲー
ト電位でVG＞０とする。 Here, ε S is the relative permittivity of the polycrystalline silicon film that is the gate electrode, ε i is the relative permittivity of the gate insulating film, and ε p is the vacuum permittivity of 8.86×10 -14 F/cm t i is the thickness of the gate insulating film q is the elementary charge 1.6×10 -19 C N D is the impurity concentration of impurities in the gate electrode V G is the gate potential measured with the source potential as a reference V G > Set to 0.
このとき、xdの大きさを二酸化シリコン膜と
多結晶シリコン膜の界面の凹凸と同程度または、
それ以上即ち、二酸化シリコン膜の厚さの約10％
以上とすると、第３図に示すようにゲート絶縁膜
２２の界面の凹凸部２６を平坦化するように空乏
層ができる。式(1)は、界面は全く平坦な場合の式
であるが、界面に凹凸部がある場合には、第３図
に示すように空乏層がのび、式(1)で与えられる
xdは、おおむね空乏層の平均を与える。第３図
中２１はｐ形シリコン基板、２２はその表面に形
成された二酸化シリコン膜からなるゲート絶縁
膜、２３は、ゲート絶縁膜２２上に形成されたゲ
ート電極であり、２４は空乏層、２５は空乏化し
ていない領域である。 At this time, the size of xd is set to be the same as the unevenness of the interface between the silicon dioxide film and the polycrystalline silicon film, or
more than that, i.e. about 10% of the thickness of the silicon dioxide film.
In this case, a depletion layer is formed so as to flatten the uneven portion 26 at the interface of the gate insulating film 22, as shown in FIG. Equation (1) is the equation when the interface is completely flat, but if the interface has uneven parts, the depletion layer extends as shown in Figure 3, and the equation is given by Equation (1).
xd roughly gives the average of the depletion layer. In FIG. 3, 21 is a p-type silicon substrate, 22 is a gate insulating film made of a silicon dioxide film formed on the surface thereof, 23 is a gate electrode formed on the gate insulating film 22, 24 is a depletion layer, 25 is a non-depleted region.
このように空乏層の厚さxdがゲート絶縁膜の
厚さtiのおおむね10％以上であれば、空乏層２４
の存在により電界を緩和することができる。 In this way, if the thickness xd of the depletion layer is approximately 10% or more of the thickness t i of the gate insulating film, the depletion layer 24
The electric field can be relaxed by the presence of .
上述の条件を式で表わすと式(1)から
となる。さらに式(2)の根号内を展開すると近似的
に
１／10ti＜εpεi／ti・VG／qND …(3)
とかけ、さらにこれをNDについて解くと
ND＜10εpεiVG／ti 2ｑ …(4)
となる。 Expressing the above conditions in a formula, from formula (1) becomes. Furthermore, by expanding the radical in equation (2), we can approximately multiply by 1/10t i <ε p ε i /t i・V G /qN D …(3), and further solving this for N D , we get N D <10ε p ε i V G /t i 2 q (4).
つまり、不純物濃度NDを式(4)をみたすように
定めれば良い。なお、不純物濃度NDがゲート電
極２３内で一定という条件のもとで式(4)を導いた
が、NDが一定でないときは、NDとしてゲート絶
縁膜２２とゲート電極２３の界面における値を使
用すれば良い。 In other words, the impurity concentration N D may be determined to satisfy equation (4). Although formula (4) was derived under the condition that the impurity concentration N D is constant within the gate electrode 23, when N D is not constant, N D at the interface between the gate insulating film 22 and the gate electrode 23 Just use the value.
また、不純物としてドナーとアクセプタの双方
が存在する場合は、
｜ND−NA｜＜10εpεi｜VG｜／ti 2ｑ …(5)
を満足すれば良い。ここで、NDはドナー濃度、
NAはアクセプタ濃度である。式(5)は、最も一般
的な条件である。 Furthermore, when both a donor and an acceptor exist as impurities, the following may be satisfied: |N D −N A |<10ε p ε i |V G |/t i 2 q (5). Here, N D is the donor concentration,
N A is the acceptor concentration. Equation (5) is the most general condition.
以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
第３図は、本発明の一実施例の要部の拡大図で
ある。この実施例は、本発明をｎ−チヤネル絶縁
ゲート型電界効果トランジスタに適用したもので
ある。図中２１は、ｐ形のシリコン基板２１であ
る。シリコン基板１上には、900℃の酸化雰囲
気中で厚さ150Å形成された二酸化シリコン膜か
らなるゲート絶縁膜２２が設けられている。ゲー
ト絶縁膜２２上には、多結晶シリコン膜を厚さ
3000Å堆積し、これに加速電圧40keV、ドーズ量
８×1014cm-2の条件で砒素イオンを注入してなる
ゲート電極２３のパターニング後に、通常の
MOSトランジスタの製造プロセスに従つてソー
ス、ドレイン電極等の形成が行われている。ソー
ス、ドレイン領域への不純物の導入は、ゲート領
域をマスクしてゲート領域の不純物濃度が高くな
らないようにして行つている。 FIG. 3 is an enlarged view of essential parts of an embodiment of the present invention. In this embodiment, the present invention is applied to an n-channel insulated gate field effect transistor. 21 in the figure is a p-type silicon substrate 21. A gate insulating film 22 made of a silicon dioxide film formed to a thickness of 150 Å in an oxidizing atmosphere at 900° C. is provided on the silicon substrate 1 . A polycrystalline silicon film is formed on the gate insulating film 22 to a thickness of
After patterning the gate electrode 23 by depositing 3000 Å and implanting arsenic ions into it at an acceleration voltage of 40 keV and a dose of 8×10 14 cm -2 ,
Source, drain electrodes, etc. are formed according to the manufacturing process of a MOS transistor. Impurities are introduced into the source and drain regions by masking the gate region to prevent the impurity concentration in the gate region from becoming high.
ゲート電極２３にイオン注入された砒素は、そ
の後の熱工程（例えば、窒素雰囲気中での1000℃
で40分程度のアニール）で、ゲート電極２３内に
ほぼ一定の濃度分布を呈している。この不純物濃
度NDは、ND＝2.6×1019cm-3程度に設定されてい
る。 The arsenic ion-implanted into the gate electrode 23 is heated through a subsequent thermal process (for example, at 1000°C in a nitrogen atmosphere).
After approximately 40 minutes of annealing), the gate electrode 23 exhibits a substantially constant concentration distribution. This impurity concentration N D is set to approximately 2.6×10 19 cm −3 .
このように構成された絶縁ゲート型電界効果ト
ランジスタを、ソース電圧を基準にしてゲート電
圧を5Vに設定して使用すると、上述の式(4)の右
辺は次のようになる。 When the insulated gate field effect transistor configured as described above is used with the gate voltage set to 5V with the source voltage as a reference, the right side of the above equation (4) becomes as follows.
10εOεiVG／ti 2ｑ＝10×8.86×10-14×3.9×５／（150
×10-8）2×1.6×10-19
＝4.8×1019（cm-3）
つまり、ドナー濃度NDは、2.6×1019cm-3＜4.8
×1019cm-3を満足する。この結果から明らかにゲ
ート絶縁膜２２の耐圧が向上することが判る。10ε O ε i V G /t i 2 q＝10×8.86×10 -14 ×3.9×5/(150
×10 -8 ) 2 ×1.6 × 10 -19 = 4.8 × 10 19 (cm -3 ) In other words, the donor concentration N D is 2.6 × 10 19 cm -3 <4.8
×10 19 cm -3 is satisfied. This result clearly shows that the breakdown voltage of the gate insulating film 22 is improved.
なお、本発明は、ｐ−チヤネルの素子にも適用
できることは勿論である。この場合には、シリコ
ン基板としてｎ形シリコン基板を使用し、多結晶
シリコン膜中には、ホウ素を注入する。 It goes without saying that the present invention can also be applied to p-channel devices. In this case, an n-type silicon substrate is used as the silicon substrate, and boron is implanted into the polycrystalline silicon film.
また、ゲート絶縁膜としては、窒化シリコン膜
或は、窒化シリコン膜と酸化シリコン膜の多層構
造のものを用いても良い。 Further, as the gate insulating film, a silicon nitride film or a multilayer structure of a silicon nitride film and a silicon oxide film may be used.
また、ゲート電極としては、金属膜や金属の硅
化物膜を多結晶シリコン膜上に積層したものを用
いても良い。 Further, as the gate electrode, a metal film or a metal silicide film stacked on a polycrystalline silicon film may be used.
以上説明した如く、本発明に係る絶縁ゲート型
電界効果トランジスタによれば、ゲート絶縁膜の
膜厚に左右されずに、耐圧の向上を達成できるも
のである。
As explained above, according to the insulated gate field effect transistor according to the present invention, an improvement in breakdown voltage can be achieved regardless of the thickness of the gate insulating film.
第１図は、従来の絶縁ゲート型電界効果トラン
ジスタのゲートの近傍領域を示す拡大図、第２図
は、本発明の原理を示すバンドダイヤグラム、第
３図は、本発明の絶縁ゲート型電界効果トランジ
スタのゲートの近傍領域を示す拡大図である。
１，１１，２１……ｐ形シリコン基板、２，１
２，２２……ゲート絶縁膜、３，１３，２３……
ゲート電極、２４……多結晶シリコン膜の空乏
層、２５……多結晶シリコン膜の空乏化していな
い層。
FIG. 1 is an enlarged view showing the region near the gate of a conventional insulated gate field effect transistor, FIG. 2 is a band diagram showing the principle of the present invention, and FIG. 3 is an insulated gate field effect transistor according to the present invention. FIG. 3 is an enlarged view showing a region near the gate of a transistor. 1, 11, 21... p-type silicon substrate, 2, 1
2, 22... Gate insulating film, 3, 13, 23...
Gate electrode, 24... Depletion layer of polycrystalline silicon film, 25... Non-depleted layer of polycrystalline silicon film.
Claims (1)
ドナー原子を含有した多結晶シリコン膜で形成さ
れているｎチヤンネル形絶縁ゲート型電界効果ト
ランジスタにおいて、ゲート電極直下のゲート絶
縁膜と多結晶シリコン膜との界面近傍で該電極を
形成する多結晶シリコン膜中に含まれるドナー原
子密度をNDとし、絶縁膜の厚さをti、絶縁膜の比
誘電率をεi、真空の誘電率をεO、素電荷をｑ＝1.6
×10-19クーロン、ソースとゲートの電位差の絶
対値の最大値をVGとするとき、不等式｜ND｜ ＜10εOεiVG／qti 2 を満足することを特徴とする絶縁ゲート型電界効
果トランジスタ。 ２ ゲート電極は、多結晶シリコン膜の単層構
造、或は、金属膜または金属硅化物膜と多結晶シ
リコン膜の複数層積層構造からなる特許請求の範
囲第１項記載の絶縁ゲート電界効果トランジス
タ。 ３ ゲート絶縁膜は、二酸化シリコン膜、窒化シ
リコン膜、二酸化シリコン膜と窒化シリコン膜の
二層構造体の何れかである特許請求の範囲第１項
または第２項記載の絶縁ゲート電界効果トランジ
スタ。 ４ ゲート電極の全部または一部が不純物として
アクセプタ原子を含有する多結晶シリコン膜で形
成されているｐチヤンネル形絶縁ゲート型電界効
果トランジスタにおいて、ゲート電極値下のゲー
ト絶縁膜と多結晶シリコン膜との界面近傍で該電
極を形成する多結晶シリコン膜中に含まれるアク
セプタ原子密度をNAとし、絶縁膜の厚さをti、絶
縁膜の比誘電率をεi、真空の誘電率をεO、素電荷
をｑ＝1.6×10−19クーロン、ソースとゲートの
電位差の絶対値の最大値をVGとするとき、不等
式｜−NA｜ ＜10εOεiVG／qti 2 を満足することを特徴とする絶縁ゲート型電界効
果トランジスタ。 ５ ゲート電極は、多結晶シリコン膜の単層構
造、或は、金属膜または金属硅化物膜と多結晶シ
リコン膜の複数層積層構造からなる特許請求の範
囲第４項記載の絶縁ゲート電界効果トランジス
タ。 ６ ゲート絶縁膜は、二酸化シリコン膜、窒化シ
リコン膜、二酸化シリコン膜と窒化シリコン膜の
二層構造体の何れかである特許請求の範囲第４項
または第５項記載の絶縁ゲート電界効果トランジ
スタ。[Claims] 1. In an n-channel type insulated gate field effect transistor in which all or part of the gate electrode is formed of a polycrystalline silicon film containing donor atoms as impurities, the gate insulating film directly under the gate electrode and Let N D be the donor atom density contained in the polycrystalline silicon film that forms the electrode near the interface with the polycrystalline silicon film, t i be the thickness of the insulating film, ε i be the dielectric constant of the insulating film, and vacuum. The permittivity of is ε O and the elementary charge is q=1.6
×10 -19 coulombs, and when the maximum absolute value of the potential difference between the source and the gate is V G , an insulated gate characterized by satisfying the inequality |N D | <10ε O ε i V G /qt i 2 type field effect transistor. 2. The insulated gate field effect transistor according to claim 1, wherein the gate electrode has a single layer structure of a polycrystalline silicon film, or a multilayer stacked structure of a metal film or a metal silicide film and a polycrystalline silicon film. . 3. The insulated gate field effect transistor according to claim 1 or 2, wherein the gate insulating film is any one of a silicon dioxide film, a silicon nitride film, and a two-layer structure of a silicon dioxide film and a silicon nitride film. 4. In a p-channel type insulated gate field effect transistor in which all or part of the gate electrode is formed of a polycrystalline silicon film containing acceptor atoms as impurities, the gate insulating film and the polycrystalline silicon film below the gate electrode level Let N A be the acceptor atom density contained in the polycrystalline silicon film forming the electrode near the interface, ti be the thickness of the insulating film, ε i be the dielectric constant of the insulating film, and ε be the permittivity of vacuum. O , the elementary charge is q=1.6×10−19 coulombs, and the maximum absolute value of the potential difference between the source and gate is V G , then the inequality |−N A | <10ε O ε i V An insulated gate field effect transistor characterized by satisfying G /qt i 2 . 5. The insulated gate field effect transistor according to claim 4, wherein the gate electrode has a single layer structure of a polycrystalline silicon film, or a multilayer stacked structure of a metal film or a metal silicide film and a polycrystalline silicon film. . 6. The insulated gate field effect transistor according to claim 4 or 5, wherein the gate insulating film is any one of a silicon dioxide film, a silicon nitride film, and a two-layer structure of a silicon dioxide film and a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16590583A JPS6057972A (en) | 1983-09-09 | 1983-09-09 | Insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16590583A JPS6057972A (en) | 1983-09-09 | 1983-09-09 | Insulated gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6057972A JPS6057972A (en) | 1985-04-03 |
| JPH053147B2 true JPH053147B2 (en) | 1993-01-14 |
Family
ID=15821221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16590583A Granted JPS6057972A (en) | 1983-09-09 | 1983-09-09 | Insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6057972A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286084A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Field effect transistor |
| JPS5339083A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Production of silicon gate mis semiconductor device |
-
1983
- 1983-09-09 JP JP16590583A patent/JPS6057972A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5286084A (en) * | 1976-01-12 | 1977-07-16 | Hitachi Ltd | Field effect transistor |
| JPS5339083A (en) * | 1976-09-22 | 1978-04-10 | Hitachi Ltd | Production of silicon gate mis semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6057972A (en) | 1985-04-03 |
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