JPS6057751A - Overlap processing system - Google Patents

Abstract

PURPOSE:To improve the flexibility in constituting functions by dividing a processing unit at a point being convolution of sample value operating formula in performing parallel processing with n-multiplex overlap and connecting processing units assigned at each division by a common memory. CONSTITUTION:A processing circuit calculating the sample value operating formula obtained numerically is constituted and the processing of the operating formula with lots of processing steps is subject to parallel processing with overlap. In such a device, it is divided at a point being the convolution of the operating formula, plural procesing units A, B, C, C1, C2 and C3 are assigned to each division and each processing unit is communicated through the common memory RES. The plural procesing units A-C, C1-C3 have a modulation/demodulation function, and blocks at the processing unit at each division are connected by constituting plural layers through minute processing and etching.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an overlap processing method, and in particular to overlap processing when a digital signal processing circuit is used in a modulator/demodulator for data transmission or facsimile transmission via a telephone line. It is related to the method.

Prior Art Facsimile 41J transmission performed using voice telephone lines;
Alternatively, in other data transmissions, a modulator/demodulator is used for code transmission.The modulator/demodulator number can be configured by a digital signal processing circuit.

When performing digital signal processing, functions are expressed as sample value operation formulas, and if these operation formulas consist of, for example, n steps, parallel processing is performed by overlapping them n times, making it possible to perform high-speed processing. becomes.

In this case, it is important to note that there is a feedback loop, and in this case it is necessary to make predictions, etc.

However, when the operational equation takes the form of a convolution of two terms, mutual processing delays may appear only in the form of transmission delays. This should be used when configuring functions, but conventionally,
has not been clearly stated and no compensation has been taken.

The modulation and demodulation method that converts the sample value operation equation into multiple overlapping parallel processing to perform high-speed processing is:
This method was proposed by the inventor of the present invention in Japanese Patent Application No. 56-147188 entitled "Modulation/Demodulation System".

Purpose The purpose of the present invention is to clarify the points that were previously unclear as described above, and to clarify that even when the operational equation is expressed in the form of a convolution of two terms, the mutual processing delay is only the transmission delay. Instead, it is an object of the present invention to provide an overlap processing method that can widely apply digital signal processing that is highly flexible in terms of functional configuration.

Configuration The configuration of the present invention will be explained below by explaining the principle and examples.

The present invention enables a divided configuration by dividing a mathematically determined sample value operation formula at points that result in convolution, assigning a processing unit to each division, and communicating between each unit via a common memory. The details are described in the explanation of "Digital Signal Processing Circuit" in Section 5 and in FIGS. 5A to 5C.

The principles and examples will be explained in the following order.

(1) Sample value operation formula for modulation function, e) Sample value operation formula for detection, O) Sample value operation formula for synchronous control, (4)
Operation establishment function and digital processing peripheral circuit, ■) Digital signal processing circuit, structure by fine processing.

In order to perform a sample value-based modulation/demodulation function with one modulation function, the modulation/demodulation function is processed in real time by a sample value processing unit. On the modulation side, an operating formula is created to create a modulation waveform that can be transmitted over a line whose frequency band is limited to the voice band and has frequency fluctuations.

The modulation waveform is expressed by the following equation (see the specification of the above application).

f(t)=A(t) a o sω. 't-Qt)s
inω,′t, , (1, o). Here ω. ′ is the carrier frequency, which is almost at the center of the transmission bandwidth, and A(t)j
B(t) is an envelope waveform.

When this is created by a sample value processing unit, it is necessary to appropriately allocate sampling intervals for each function. First, it is clearly unreasonable to make the sampling intervals of the carrier part and the baud signal part the same in the above-described operational formula. Suppose that sampling intervals T and T are allocated to these, respectively. Furthermore, in considering where to set the boundaries between these parts, it is appropriate to set a baseband part with a sampling interval T□ in the middle of the image part.

Here, if the sampling numbers for sampling the baud signal, baseband signal, and carrier signal are i, m, and n, respectively, the following is assumed. Here, the symbol 〔〕 means the largest integer that does not exceed the value of I. In order to be able to evaluate the transmission characteristics of the carrier part using the transmission characteristics seen from the baseband, the modulated carrier is the real part of the cosine term amplitude, and Jl! is the sine term amplitude. ! It should be treated as a complex number with several parts. This is expressed as F (t). There is a deformation of the transmission characteristics due to the connection of parts with different sampling intervals, and to clarify this, one transformation of F(mTl) will be considered. That is, Z(F(
mT, ))−F(o)+Fσl) x−” + F (
2TI) z40miF←) ...(1,2). When sampling the carrier signal, F (
MITI) is held and F' (nT) is obtained, then Z CF' (ZLT) )=F(o)Hω)+F
(TI) H(p)p-”+F (2T,) H#)p
+ to -2...-F (p-") H(p)-F'
φ) ... (1, 5) Here, it is expressed as "-z, hsmT□/T. u(t) is the spectrum of the modulated carrier wave with the angular frequency F!"1 < w <, s d□ is a complex number as shown below.

d1, a1+j bl ai, and b are determined corresponding to each logical value combination of data bits included in modulation element 1. By performing two transformations of equation (1, 5), F(・)−1X, ,! , u (mT, -1T,)
dlz-”-,z.

Substituting this into equation (1, 3), p'(,1/k), , J' , , -1T,/rl
peak) H (zl/'Ic) 1- to -M i ... (L 7) H is clearly a modification of the characteristic in the case of creating 〆(n T ) by holding F (mT) to zero order. It represents. From the idea of compensating for this, consider the rJIJ number, ) (!IITI):E Σ and (mT, -1T,)d
□ ---(1,9) Multiply the father-in-law by 1-. Then, instead of holding F (mT□) to zero order, if F (m Tl ) is held to zero order, the original transmission characteristic with compensation for the deformation Hω) can be obtained. That is, U'
(z)I-1(g1/”) -F(4---(+, 1
o) is derived by using equations (1, 6) to (1, 8). Considering taking the inverse of the 2 transformation of equation (1, 10), F (nT) −H(nT) OF (mTx) *
+ * (1-11). Here, 0 represents a combination of both sides. Is this simply '? ”
This means that the value of (mT□) is held in the register.

The sampling interval of the gear rear signal is T.

The angular frequency of T is ω. The modulated carrier wave cannot be expressed unless the period is smaller than one period of the carrier wave.

To express this accurately, sideband waves generated by the carrier signal distributed around the sampling frequency mix into the band of the carrier signal. This can be avoided by increasing the sampling frequency, but
Apart from this, components due to high-order waste waves generated by sampling the baseband signal are distributed around the carrier frequency, and these components mix into the baseband region. This is done by converting the baseband signal to 0 in the carrier signal processing section.
Next hold and made '? "CrhT), and to avoid this contamination, F 0 (nT)
-G (nT) 0'? ” (nT) ・= (1,
122 filtering is required. G (M
The cutoff frequency of T) is ω. ', but normally it will be about 1800H. FIG. 1A shows an arithmetic circuit that outputs a modulated carrier wave f (nT) at the output end.

f (nT) is f (nT) − A6 (nT) 0011 #, as shown in the right part of the ffllA diagram. '
nT-Bo(nT) 5izt m. ' nT1・(1
, 13). Here, Fo (nT) - Ao (21T) 1 B, (nT)
To create a signal, process the equations (1, 12). This process is indicated by G in FIG. 1A, and G(nT)=Gl(nT)+jGs(nT). However, this form is a general form, and in practice Os (n
It is convenient to set it as T ) -0. The pull H in FIG. 1A exhibits a holding action expressed by equation (1, 11). The input signal to this bulleter is the second term on the right side of equation (1, 11). To explain the processing steps of H (1,
a) Expression growth (mT □) - P' (mT,) + jQ' (mT,) -
(1, 14), and further, F (mT l) - A (mT z ) + j B
(mT1), T (mTx)-Σ (P'(mT, -iT,) al
-Q'(mT, -tT,)su1-ni-in-lawBt7! IT,)-5(P'(mT,-tT,)b,+
Q'(mT, -1Ts)a? In other words, in the above equation, P' and Q' are derived from the equation (1,0) and are modified U. U has an imaginary part in double-sideband transmission. However, it can be seen that not only the real part but also the imaginary part is required to correct the deformation of the characteristics due to the hold processing, as shown in equation (1.15).

The ROM of FIG. 1A is a read-only memory that stores cosine and sine II values. AI, A, in Figure 1A.

B1 and Bs are the 1st and 2nd of the first equation (1, 15) and the 1st and 2nd of the second equation, respectively. It performs the operation of the second term, and the variables of the function of this term are λ (m, i) = mT, -1T, = (1, 16)
This function is defined by a table that takes this as an argument. The contents of this table are prepared by recording the calculation results in a read-only memory or the like in advance based on the required spectrum of U and its correction formula (1.a). The argument for drawing the table is determined by the process represented by the block λ and its peripheral symbols in FIG. 1A.

This process converts Equation (1, 16) into differential form as λ(ml i) asλ(m-1, i) +T1p λ
-1) -λ (%1-1) -T@whip... (B17) Determined by. &1 + bl in the (tls) equation can be found from Table C in FIG. 1A. This table C is indexed by the number formed from the sequence of transmitted data bits that enter the modulation element. Vector d□−a + i bl
Let N be the number of discrete values that can be taken by , then the transmission data bit sequence is divided into j og s N bits, and each bit in one division is equal to 1 in the number created by the combination of logical values. The difference is taken by the memory R□ in FIG. 1A, and a lookup of C is performed using it as an argument. The contents of this table are set so that the demodulator is less likely to misidentify the discrete values of d□.

Figure 1B is a detailed view of the parts B, , A, in Figure 1A.
-11 to ke' is a shift register that stores the output of Table C. Furthermore, the block Q/ indicates that the input values are used to index the function tables P' (mT□) and Q' (T).

The sampling rate distribution for the baud signal, baseband signal, and carrier signal is l/T, , 1/T, respectively.
□ and l/T, but since the baud signal will be processed by 2.4KH, which is determined from the modulation speed,
Other sampling rates will be integer multiples of 2-4 KHz. To prevent sidebands generated by baseband sampling around the carrier frequency from entering the baseband band, use G(nT) as described above.

Therefore, the problem is to find conditions under which sideband waves distributed around the carrier signal sampling frequency and the baseband signal sampling frequency can be avoided.

The distribution of sampling rates that are considered appropriate for implementation is (1) 2.4KH, ,2,4KH, and o,eKH for the baud signal, baseband signal, and carrier signal, respectively.
x(2) 2.4KH, 4,8KHi, and 9.6K
H.

There are two possibilities. Under the condition α), m - k in the equation (t, 1S)? '<xT,>-U' (kT,) o dOc>
U'(kT, ) can be realized as a digital filter. However, in order to separate sideband waves distributed around the baseband signal sampling frequency from the baseband signal, the digital filter described above becomes close to an ideal filter. Furthermore, the above-mentioned sideband waves exist close to the baseband signal, which is a factor that makes it impossible to realize the condition α). In case (2), an idle area can be provided between the sideband wave and the required band of the baseband signal. 100H like them! It is possible to create a margin for setting a backward channel with a certain bandwidth.

Note that in FIG. 1A, the sampler intervals are T, T, and T, respectively.

indicates that it is a sample value processing unit. Also, T,
The input from the processing unit T8 to the block λ of the processing unit T8 is shown, which means that it is cleared every time the contents of λ are T. For λ (1, 17)
I mentioned that it is for formula calculation, but actually (
1, 1S) etc., when calculating rA, the current time is set to -Q. To match this, λ may be set to O for every T. In Figure 1B, %
al(#' to -4#......g& The shift register that is ff41fia is updated at an interval of T, which is a different interval from the other parts of FIG. 1B. In order to be able to process all the circuits shown in Figure 1B in the same way, it is necessary to insert a dummy in each stage of the shift register in Figure 1B as in Figure 1C. This is the case of rate distribution. In Figure 1C, the part (,) is 2.4KH, and the part (b) is 5KH.

and sample each.

A modulated carrier wave output from a two-detection sample-value modulator is received by a demodulator through a line. If there are no frequency and phase variations in the line, the received wave at the demodulator input is R'%) - r□(t)
oos←o' t) -rs (t) s in (”
o' t). However, because there are variations in general, it does not take this form. In order to formulate the sample value operation equation for detection, it is necessary to establish a theorem for the received wave based on the standards of the receiving side. Therefore, the received wave is R(t)-r□(t)c
oo (a+, t+αo (t)) −r −)s L
n (mo = 1αo(t))...(2,1). This is ω. In order to treat this as a signal close to the baseband with a spectrum distributed around the center, first, @'(t)-R(t). j(ay.t+Jt))-e
(t) e””) --- Make (2, 2). Here it is. When performing the operation (2, 2), harmonics are generated. It is necessary to exclude this and limit the spectrum to -2W to 2πW. For this, ξ
(1) Perform filtering with a unit response.

2←)-6&)*ξ(1) where z(t)= ”(t)+ 1y (t) e ξ(1)
-η(t)+jζ(1), then x(t)-v(t) O@. (t)+ζ(t) Oe8
(t)) ...(2,4) y(t)-η(t,) Os, (t)-God) Oeo(
t). The purpose of detection is r (tJ, r, (t)
For this purpose, θ(
1) as α. It is necessary to approach (1). This requires control, which will be described later.

To calculate the operating equation for detecting the received wave, use α in equation (2, 1). (1) is an unmeasurable quantity, R(t) is measured and aosω. t, sinω. Consider that t is produced by the demodulator. e by the sample value generated by the sample value processing circuit. ,・6 is expressed as follows. On the demodulating side, there is a carrier signal part and a baud signal part, just like on the transmitting side, and it is unreasonable to process them all at the same sampling interval, so it is still necessary to consider the appropriate distribution of sampling rates. However, when using a multi-rate system on the demodulation side, skip sampling is performed, and unnecessary waves are generated due to skipping.

The question is whether there is an allocation method that satisfies the conditions for avoiding this shadow O. For this reason, in (2, 4), first, da etc. and l, and η. Let's look for possible conditions when allocating 1/T to η' and l/T□ to η'. First, as an example, the first term on the right side of equation (2,4) is x'(t)-ηo(t) O5o(t)+η'(t)
O' c (t) ...(2-6), and in the first term on the right side, t-nT and z, (nT) at
). (nT) O@1゜(XLT) ---(2,7)
Let n ”Ki (K, i is a number), and let U (nT) be a unit 5top function,
x, (iT,)=U(nT:n-Ki) z, (nT)
...(2,8) Narusuki No. 7146 x, (1T,)
think of. Here, the notation method (nTsn-Kt) means that n t- is 1, or the value is 1, which is an integer. Applying the skip sampler theorem to this x z (t T z ), we get (iT,)
The 2 conversion of is...-(2,P). Here, z-pk. On the other hand, if we take the two transformations of equations (2, 7), we get xx (pl-'lo fp) ・aai) ---(
2, 1o), but in each term on the right side of equation (2, 9), instead of p. A term set as 52πλA will appear. j61 in these formulas
By setting p-· at 'j, the spectral distribution due to the skip signal is rounded. In these spectral distributions, the component λ-0 is the desired wave, and in addition to this, an unnecessary wave λNO is generated at intervals of 1/of the sampling frequency. Therefore, in order to be able to distinguish between unnecessary waves around the sampling frequency of the baud signal and the required band of the baud signal, the required band of the baud signal must be created by an ideal filter whose cut-off frequency is the baud rate. must be equal to In order to satisfy this condition with smooth transmission, the sampling rate distribution method is 2, 4.4.8.9.
In the case of 6KH, it is necessary to make the baseband close to Nyquist band transmission. However, when allocating the sampling rate on the demodulation side, the skip sampling theorem shows that it is meaningless to use the same allocation as the modulator, so 2.4, 2.4, 9.6KH,
It is necessary to do so. In this case, the part corresponding to the baseband on the modulation side, that is, the sampling of η' in equation (2, 6) is the same as the sampling of the baud signal, so the processing of ' is performed by the automatic etc. connected to the next stage. This will be done using the transversal filter of the converter. In this case, the input signal of the transpersal filter becomes the following equation, which is expressed by the sample value of equation (2, 4).

Let L-T, /T, x QcT,) -U (nT; n-Lk) ((
η, (nT) O@a (nT))+(ζ.(XIT
)0・, (nT)))y (kT,) −U (nT
; *-Lk) ((7゜(nT) Os, (nT)
)-(ζ.(nT) Oeo(XIT)))...(
2, 11) Of course, in this signal, unnecessary waves are closely distributed in the required band of the baud signal. However, this unnecessary wave can be removed by the automatic equalizer connected next.

That is, as will be described later, the transparsal filter in automatic equalization processing is performed to provide Nyquist band transmission. this is! As long as there is a signal outside the area, a detection signal of 3 ``x (kTa) # t Y (kT s) is generated, and M (kT,) fitx2 (k'r,) l,''
This is because the tap system is automatically adjusted in the direction in which (hT, ) becomes smaller.

Figure 2A shows a processing circuit for processing equations (2, 11), and the signal circuit (h
T, ) # y (hT,) is 9. in FIG. 2A. It is obtained by referring to the output of a register lO every interval T. The section (0) in FIG. 2A is a sample value processing circuit with a sampling interval T. The section (IL) is the sample value processing path at the sampling interval T, and the section 8 performs the convolution indicated by * in equation (2, 11) and the related display processing.

Reference numeral 7 denotes an input terminal of a demodulation circuit on the receiving side, and 6 converts the A4SP signal of 7 into a digital signal. l, 2°δ, 4.
The circuit indicated by 5 processes the equation (2, 5), and outputs e, (nT) to the input, and e, (nT) to the circuit 5.

The sampling rate distribution on the modulation/demodulation side is 2.4.4-8-9.6KH2, $3 and 2.4.2, respectively.
4.9.6KH, Nyquist band transmission and all digital sample value processing,
A circuit that can be applied even if the transmission is not necessarily in the Nyquist band is shown in FIG. 2B.

In Figure 2B, 6 is the receiving side demodulation circuit input terminal and 1
．． 2.3.4. The circuit denoted by δ processes equation (2-5). However, the part shown in figure (b) of flI2B is a linear analysis processing circuit. ζ etc. indicate those in equation (2, 4). On the other hand, the section carrier signal sample value processing circuit (a) is a digital processing circuit.

The numeral 5 is an analog pi digital multiplier whose input and output are analog sections. Figure 2B (Q) is
In a digital sample value processing circuit with a sampling interval T, the analog interval part of Ru.

The operating formula for automatic equalization can be determined by setting t - hT in the formula described in the above-mentioned hIDA specification. However, if this is calculated by a processing circuit, an expression with -0 will be calculated. First, in the case of a transversal filter that goes in series with the transmission line,
QcT, ), Y (kT,) is the value of the output signal of the transversal filter, then X (kT,)-Σ (aos# QcT,) (il
x((k-1)T,)-δ1yi-0 ((k-1)'rs))-O1nθQcTs) (117(>-t)'r,)+
δ, x (oc-t)T,)))Y(kT,)-Σ (
c o aaQcTs) Jy (Oc i) Tl)
+δ1x1 Makoto0 ((k-1) T,) 10 sinθ(kT,) (7□X(Oc-1)T,)-
617(HT, ))), , @<2.12) In this formula, x and y are (2,4) or (2,11
). Therefore, the automatic equalization processing circuit is as shown in Fig. 2C, but the inputs of this circuit are those shown in Fig. 2A, and the first and second B.
The output will be as shown in the figure. It is necessary to input θ, etc. to the processing circuit shown in FIG. 2C. This variable is also shown in equation (2, 12). These are discussed in the next section. In FIG. 2C, the block T is the signal register of the taps of the transversal filter, γ6tδ6trz*
δ1 v ””'1M-1'δ)I-1 is a tap coefficient. The formula for determining the tap coefficient is determined from the signal error of the detected signal. In this case, the detected signals are X', Y' which have been further corrected by a parallel automatic equalizer, which will be described later, on the values determined by equations (2, 16).

It can be determined by That is, yi(h+Q −r, >)−a t IQcTs) z
(Qc-1) Ts) +a g s (kT,)y
(Oc-') Ts) δ, (k+1)-61, to->aa I QcTs)
y ((k-1) Tl) +ag @ (k'r,
)x ((kt) Ts) . . . -(2,14) This is a differential operation formula. where a □QcT,) −g, (kT,) o osθ(
kT,) +g Js inθQcT,)a, QcT
,) w-s, QcT,) sinθQcT,)-#
JaoeθOcT, )...(2,1s). 4x and lx are predicted values of the signal error (2, 1is) equation. The equations (2, 13) to (2, 16) are the adjustment equations for the transversal filter, and the processing circuit is
Shown in Figure 2D. Terminal γ in FIG. 2D. δ0. γ
,δ,.

. . , γ, δ, −□, the register T, and the adder circuit + represent the processing of the differential operation formula (Z, t4). Also, x in Fig. 2D
The shift register consisting of the register T connected from the terminal (bT,) l 7 ("s) is a re-presentation of the one in Fig. 2C. In the part indicated by the block L in Fig. 2D, , 3,4.5".

6 is an input terminal to which each term on the right side of equation (2, 15) is input. The vertical lines extending from these terminals and the X marks shown at the light points on the horizontal line are used to multiply the right side of equation (2, 15), and the vertical line signals input to the two X marks on one horizontal line are multiplied. 1i, and the result appears on the horizontal line. Further, the two perpendicular lines descending from the output terminal 1.2 of the L block represent the left side of equation (2, 15), and the signals on the horizontal line input to the + marks on each line are added. Addition input with a minus sign (-) indicates that subtraction is to be performed. The block M in FIG. 2C also uses a method similar to the processing method for the L clock described above, and calculates a large term on the right side of equation (2, 12).

In addition, when writing a sample value operation formula like the one above,
Although the sampling time t - * T, etc. are substituted into variables in a continuous equation, there is a phase shift in the sampling clock, so t - hT, +△.

and t-2LT+△/L (LT, /T)
It is correct to say. However, when creating a processing circuit, Δ
Since it has no effect, I will omit it here. However, since it is necessary to accurately control the phase of the baud signal sampling circuit, we will restore the variables omitted in the section dealing with this control function.

Due to unitization, the phase of the sampling circuit of the carrier signal also changes with the above control, but this does not affect the characteristics.

The modulator generates a modulated signal 11k every time a fixed number of transmission data bits are collected. The basket is a complex number, and these discrete values having a given finite number of a values are scattered on the complex plane. The detected signal in the demodulator is the sampling value at t - kT, which is the restored value of the modulated signal, and this value is d
Determine k.

The sampling value at t −k T of the detection signal is
Let '(kT,) and Y'(kT,) be considered, and let us consider complex numbers whose real and imaginary parts are respectively. That is, Z'
Qc T , )miX'(kT, )+ , IY'(kT,
). Z'(kT,) is located around each discrete value of the cage, but does not match the discrete value of dk due to distortion. However, if Z'(hT,) located near the ° point corresponding to each discrete value of dk is obtained, then
m) wo sending ivy change an signal Lt Z'(k T s
) L is determined to be a discrete value of near i dk. Therefore, on the complex plane of %Z'(kTl), there is a judgment area centered on each discrete value of the cage, and the discrete value at the center of the judgment area containing Z'(kT,) is output as a judged modulated signal. I will do it.

In the modulation/demodulation unit, this judgment area is circuitized as a table, and the input of this table is Z' (kT,), that is, X
By inputting ', Y', the above # value will be output. &z t bk in equation (2, 15) is obtained by further correcting these X (kT,) and Y (kT,). Equation (2, 12) is a transversal filter that enters the transmission line in series, and correction of its output is performed by a transversal filter that enters the transmission line in parallel. Appropriate function allocation is performed for these two types of automatic equalization. That is, the second term on the right side is X' QcT, ) - Σ2 (g, ak 7 - h
The determined modulation code is input to the transversal filter as shown in Figure 2E. The number of threads of the Transpar 9 filter for this judgment feedback is ~゛g7(k10-gl'k)+α(aJdB) 63. −
7-γX (kTri b)c-4...(2,19) ＠计、billion、is given by equation (2,16). (2,18) , (2,1
A signal graph for performing the process of 9) is shown in FIG. 2F.

In FIG. 2E, the block %T is a register that is updated every sampling interval T, and the shift register created by these registers records a and b of each term on the right side of equation (2, 16). This forms a transversal filter, whose tap coefficient g. k(1r gl
hly ...gM-1 hM-1 is obtained °The circuit is the second
This is a diagram F. TA in FIG. 2E is a block detection signal x
: ocx,), y' ocx,)e This is a table recording determination areas for restoring bk to the input toshi, modulated signal &. X' (kr,), Y' (kr,) are shown at the bottom of Figure 2E. xlQcr, ), Y' (hT, )
is obtained.

Figure 2F shows g, which is the input for Figure 2E. hOeJhl,
. . gM-1hM-1 is outputted to the terminals represented by these symbols, and the predicted value of the signal error of the output signal of the serial automatic equalizer is calculated. The lower part of the fn2F diagram performs the former, and the upper part performs the latter. In the former, the block T is a register that is updated every sampling, and the shift register configured by this block is f
This is a re-presentation of the one in figure f12E. Also, the block N used for each stage of the shift register is the second G block.
The circuit shown in the figure is L in Figure 2D, except for the integrating circuit by the register T connected to the output terminal of this block.
The same symbology is used as for the part that becomes. Next, the latter processes equation (2, 16). The reason why the above circuit is shaped like this is explained in the above-mentioned specification of the prior application.

Note that when allocating functions to a serial automatic equalizer and a parallel automatic equalizer, the parallel automatic equalizer is highly dependent on the judgment result, so it mainly depends on the serial automatic equalizer,
For the parallel type, there may be a method in which the frequency differential distribution of the transmission characteristic is used to correct distortion components that are subject to large delays at both ends of the transmission band. In this case, in the circuit that creates the coefficients of the transversal filter that feeds back the determination results ak and bk in Fig. 2F,
Coefficients of taps with small delay should not be used.

In order to complete the comprehensive operation of the three-synchronous control sampled value-operated modulation/demodulation, the synchronous control must be fixed. On the demodulation side, the detection signal X' (kr
, ), Y' (kT,), and input them into TA of FIG. 2E, which is a sign determination table, to obtain ak and bk.

In order to perform these calculations, θ(kT,) must be determined as shown in FIGS. 2D and 20', but this is also undetermined. Also, as mentioned in the previous section, when the operational equation on the demodulation side is in sample value form, the sampling time t-kT, etc. is substituted into a continuous variable of the equation, but this sampling time is the same as the modulation unit. 71 from the system! It has the form t-kT, +Δ, where Δ changes due to the synchronization difference. On the demodulation side, it is necessary to bring Δ to the appropriate position of the modulation element by automatic control.

First, θ(kT,) is controlled by α in equation (2, 1). (1)
However, since % ao(t) is an immeasurable quantity, another method is used. Regarding this,
As shown in the specification of the prior application, the deviation from the state in which the detection signal can be detected in an optimal state is proportional to . This formula can be calculated using the determination results lLk and bk. x0'Qct',) -0 state is θ
(k−)−α. OcT, ) cannot necessarily be said to be true. (3. As can be seen from the formula, xo(k'r,) becomes 0 when both detection signals become equal. Therefore, %X.

Control may be performed so that (hT,) becomes 0. First,
This signal is x (k'ji)-Σa1p Xo'(k-p)''
B) -1'fu(12yμpus0 νdoor0 x(h-ν)T,) ...(5,2) is input to the filtering process and the high frequency components contained in x, (kT,) are removed. @ Stabilize the situation. For this filtering process, parameters must be selected to pass fluctuations of 50 Hz or less. However, this process introduces a delay into the control loop of θ(kT,). If this delay is not compensated for, control will not be performed properly. For this reason, x (
As a prediction of kTa), in Qc, ) , 2 (2z QcT, ) - k
-1)Ts)-(2xt(k-1)T,)-x,(k
-zl)T, ) -@(s, I) Here, 1 is the number of skips in the predicted amount, indicating that it is a predicted value one element ahead.The range in which such prediction is valid is (
It is considered that the operating time constant of the filtering in formula 3,2) is less than ten times the modulation element length T. Under such conditions, in order to make appropriate predictions, consider a linear combination of sub-monitors with different numbers of skips, set this to 1 (kT,), and optimize the combination coefficient.

θ(kT,)-Σ hlXl (yt-'j a) ・
...('')1 error 1 a 1(k+t) praise a 1(ic)-a lxt
(h Ts ) If it is not necessary to take a large number of discrete values of the modulation vector signal, a low-pass filter may not be necessary. In this case, the high frequency components of the control loop are removed by a multiple lag filter. In this case, there is a control delay of one modulation element due to the sampling process to feed back the control signal, which is θ(hT,) −2(2x (kTS) −z(h−1
) T.

-(2θ(h-1) Ts)-θ(k-2) T, )
---Compensate by prediction processing of (5, 5). This person waste (kT,) is z (kT,) town 2x, (1
y, )+ asβx(k-1) T s )X□(k'
fs)-01Xs (iTs) + OsβxJk-1
)T,)xnQcr,) −0sXo'(kTs) +
o, βxn(k 1) rm)...(g, 6) It is obtained by the processing of a multiple lag filter. (3,su, θ(k
T, ) are input into a trigonometric function table prepared in advance to obtain aosθ(kT, ), s1nθ(kT,
) and input it into the circuits shown in FIGS. 2C and 2D.

FIG. 3A shows that when a low-pass filter is used, the overall four-way circuit and its output circuit are the first . The purpose is to calculate the second equation, and its input x'(kTs) is (3
, 1) and (L 2). This is calculated by the click LP and the block TB and their peripheral circuits in FIG. 3A. m3
The inputs of the circuit in Figure A are x' (kT,) and y'
(kT, ), ak, bk, etc. are obtained from the circuit of FIG. 2E. The output of the circuit of FIG. 3A is obtained by inputting θ(kT,) into the trigonometric function table indicated by the click TC in the figure. The contents of the table TB, TC may be calculated in advance. The click LP in FIG. 3A shows the processing of the digital filter of equation (5, 2), and its internal circuit is shown in FIG. 3B (b). In addition, the blocks xl, . . . , Figure 3B(b)
The low-pass filter is expressed in a general form, and by optimization it can be made into an economical digital filter. When the automatic phase control loop does not require a low-pass filter and uses a multi-lag filter, the processing circuit is shown in FIG. 3C. In Figure 3C (→
is a multi-lag filter circuit, and its output is inputted into a trigonometric function table TC by correcting the processing delay with a one-step prediction circuit (b), and the output is 008θ.
Create a signal (kT@)*sinθ(hy,). Also, when compensating for the delay of the low-pass filter in the control loop, (L
In the prediction formula of equation 3), the feedback term on the right side is used as (s
, 4) can be considered to be used when adaptive i4[ is not performed, as in equation 4), and when performing adaptive lI adjustment, the above feedback term is eliminated, and xiQc'l',) -2x (kT,) −x(k−
4) T, )---(5,7), it is considered appropriate to use equation (5,4).

In this case, the process in FIG. 3D can be used in place of the N part in FIG. ff13A, making the process simpler than the process in FIG. 3C. In Figure 3D, 1.2. . . . The blocks numbered L and T are registers that are updated at the sampling interval T, and these constitute a shift register. The cross at the intersection of each horizontal line of the shift register is output on that horizontal line by summing the input from the vertical line connected to it and the input from the vertical line of the other cross on the same horizontal line. It means to do.

In the descriptions 1 to 3, the sampling time for each modulation element was set as t - kT, but if there is a timing shift in the clock, t - is set to 'L', +
It is necessary to set it as △. On the automatic phase side -, the detected carrier wave ω. It has been described that the phase shift e (kr,) of nT can be controlled by equation (3.1) based on the detection signal. Therefore, when the detection is not Δ−〇, the carrier wave ω. (nT+△
/L) can also be corrected using the same operation formula. It is also possible to adjust the timing deviation Δ using a method similar to this. For this purpose, in addition to a timing processing circuit based on the detected signal, it is necessary to configure a master clock oscillation circuit as shown in FIG. 3E. In FIG. 3E, DEM is shown in FIG. 2A~! 2F, 3A to 3C, and a demodulation circuit that processes the above-mentioned timing processing circuit, etc., and CL in FIG. 3E is a p-clock generation circuit that supplies a sampling clock to the above-mentioned DEM. Two of the output lines of CL have a clock interval of T.

A polyphase clock of 1 is a multiphase clock of 1 and a corner number T between n and p clocks. The DEM also produces the output of the timing processing circuit described below, which is available on output line 3. This is proportional to the ptsuk deviation Δ.

2 CO in the figure is a voltage-controlled oscillator, and its output line 4 receives a periodic wave having a frequency that is an integral multiple of the above-mentioned clock, thereby driving CL. Input 3 of vCO is four steps off from the above△
As long as this signal exists, yco+ shifts the oscillation frequency, and this signal maintains the oscillation frequency in a state close to O. When performing control to change the oscillation frequency, the click deviation is △(k+1) −△(Le−oz (kT s) ψ・
・It will be controlled according to the formula (L8). Here, Z(ht,) is the DEM output 3 in FIG. 3E and is an analog signal. This analog signal is obtained by digitally processing the following adjustment operation formula and converting the output from DA.

Z QcT,) Tan gl Tei-1) T,) 10g〆Qcr,
)+g',"Y'(h-1) T,)+g'4Y'(k
T, ) ψ・−(L 9) g x fog 1 /2 &+1
m g am-1/2 'ni' gzl■1/2
bke g'r-bk-1/zbk” ,, (3,
1o) Figure 3F is a circuit that processes equations (5, 9) and (5, 10), and TD, , TD are tables whose contents are set by calculating equations (3, 10) in advance.

The timing information Z (kT,) is obtained as the output of the circuit shown in Fig. 3F, which is DA converted and obtained as one of the outputs of the DEM shown in Fig. 3E. is applied to the frequency control terminal of

This method is possible when the vCO is the main oscillator for the clock, but cannot be used if there is a moderator whose clock is input externally rather than from the VCO of FIG. 3E. In this case, it is necessary to automatically adjust the delay of the transmission line rather than the main oscillator.

Even in this case, since the output Z (kT,) in Figure 3F is 0, there is no need to change Figure #3F.

To automatically adjust the delay of the transmission path, a transversal filter used for automatic fixtures can be used. The automatic equalization operation is based on γ1 in equation (2, 12)
．． δ1 is adjusted using equation (2, 14), but in order to perform clock timing using this transversal filter, the disc motion equation of equation (2° 14) needs to be modified. The transversal filter is adjusted in the direction of reducing the square of the signal error of the detection signal (2, 17), but if the timing is also adjusted, E (kr,) w=a, "Qcr ,)
+a,”Qcr,) +z' (kT,) −(s
, 11). Here, 6d and 61 are given by equation (2, 13).

In this case, Z(hx,) is (s, 9) adjusted by the process
Use the formula. When adjusting using equations (5, 12), the error of the detected signal, that is, the first error on the right side of equation (g, 11). The adjustment term for the tap coefficient based on the second term is the second on the right side of equation (2,14).
．． This is the same as the third term, with a term for timing adjustment added to it. In order to include this term, we need to include...0.11. In this formula, for ax'7aγ1 etc., from formulas (2, 12) and (2, 17), aX'(hT,)/ay, -ooaoQcr,) z
(k-i) T,)-stnθi,)y(k-1) T
,) ax: (hr, >7aδ, cost (IC!,) y
(k-1-)Ts)-sinθQcT,)x (k
-1) T H) aY' (kT,)/ai, -cost (kT,)
3r(k-1) T, ) +sinθQc? , )x (
k-1) T s ) ar(kT, )7aδ, smQO8θQcTg) x(
k-1) Ts) -glnlP (jcTJy(k-
1) T,) Gamaru. It is best to calculate using this formula and substituting -1 for k in this formula. Now, person (no k)-
gl-, oogθ(c-n)? ,) ”g'2-n
sinθ(k-n) Ts)B (n, k) mg
2-, g 1nθ(k-n) TI) ”-g'2-
n Q O8θ(k-,) T,), then B (0+ h) y(k-i) T, )A (o,
d y(k-1) Ill, )■・(s, 14). Transversal filter f) Operation equation for adjusting tap coefficients The term for timing adjustment added to the adjustment term on the left side of equation (2, 14) is proportional to equation (3, 1), and the processing circuit for this term is is as shown in Figure 3G, and its output is from the output terminal r δ in Figure 81\2D...
p ry~, δ1-1 are calculated by jM, respectively.

6 In Fig. 3G, the portion above the dashed line AB is commonly used for the taps of transversal filters, and the terminals l, 2, and 3.4 have terminals (5, 14), respectively.
The formula A(oth)tB(o*k), A(1°k),
Output B (1, k). The part below AB is (S
, j4) Calculate each term on the right side of the equation. cl outputs the calculation result of the first e of equation (L14) and DI of the second equation of equation (5, 14). This part is 1”” Oe l r・−
- Calculated for each tap according to N~°1. The overall flow of the above processing is shown in Figure 3H.

In this figure, the shift register consisting of registers T is 8.
This is a re-presentation of the transversal filter in Fig. 20, where A is the part above AB in Fig. ff13G, and is provided for each tap.

The internal circuitry of the stomach is shown below AB in FIG. 3G. Also, QOIIθ(k
T,), ainθ(k'I,) has m
It is connected to the terminals with the same name in Figure 3A or Figure 3C.

g□* glZ gB s g4'a '! l (kT
The terminal named l) is connected from the terminal with the same name in Fig. 3F.

4 Operation establishment function and digital processing peripheral circuit In modulation and demodulation systems that transmit modulation vectors that take a finite number of discrete values, in order to make the reception and demodulation side functions capable of highly efficient transmission, it is necessary to It is necessary to optimize the modulation vector by m, and this is as described in Section 2.3.

In order for this optimization operation to be performed normally, the above determination must be correct. However, there is a kind of dilemma in that in order for this determination to be made correctly, various i&optimization operations must be normal. In actual equipment, when there is a carrier disconnection on the demodulation side using a backward channel, an OFF signal is sent to the modulation side.
When the disconnection is restored, an ON signal is sent and a start operation is started. Then, a start sequence is specified for transmission and reception. Decision-dependent optimization functions include automatic equalization in FIGS. 2C-2F, automatic phase control in FIGS. 3A-3D, and automatic timing control in FIGS. 3E-3H. Now, assuming that the decision is incorrect, each of these functions will scan the normal state. This scanning will continue indefinitely unless a normal state is found. If the champion performs random scanning at the same time,
It takes time to find normalcy. Therefore, first of all,
It is necessary to stop the automatic equalization function and restore the automatic phase control and automatic timing control to normal operation. Now, it is assumed that the allowable value for the distortion of the transmission line is two-phase without automatic equalization, or a phase modification method for each phase. In this case, a sufficient operating area of 11° should be obtained without automatic equalization, so first, under these conditions, only the automatic phase control and automatic timing control functions are brought into normal operation.

If the timing shift and phase shift are larger than a certain value, there is a range of shift where the sign cannot be determined correctly. If there is no distortion in the transmission line, the range of deviation as described above is 2 phases, and in the case of palm reading, it is 0.
It becomes close to. If the number of phases is 8 or more, this will not happen. Therefore, 2 phases, and 4. In the case of phase control, no matter what condition the operation is started in, it can be brought to the center of control without scanning for abnormal conditions. Due to distortion in the transmission path, interference in the amount of code occurs, and a range in which code determination is not performed correctly occurs, making it difficult to restore the system to a normal state. Conversely, distortion in a transmission line that can be easily brought to a normal control state in two-phase and four-phase can be treated as false distortion. This defines the application area for two-phase and palmistry without automatic equalization.

Therefore, in the start sequence, two-phase or palm-reading transmission is performed, the first phase is a state in which automatic equalization is completely stopped, automatic equalization is applied in the second phase, and the modulation state is increased in the third phase. By doing this, depending on the application area of 2-phase and 4-phase phase modulation, it becomes possible to transmit information at an information rate 8 times or 4 times that of the 2-phase or 4-phase phase modulation method.
It is necessary that the phase and two-phase timings are almost the same between the variable tjlN devices. This is made possible by signal transmission using the backward channel, as described above.

Next, using the backward channel, iBM't+! We will clarify the state relations on the modulation side and demodulation side for how the signal is set.

FIG. 4A is a state transition diagram of the start sequence on the demodulation side. The number of states is five, and they are distinguished by three bits as shown in the register S in FIG. 4B. 111.
110, 101, and 100° 011 indicate carrier disconnection, the first phase, second phase, @3 phase of the start sequence, and the transmitting state, respectively. In contrast, the events that cause the transition between these states are the carrier's OFF, ON, first, and
This is a signal indicating that the output of the clock counter that determines the time in the 1 to 3 phases has completed the predetermined count number H1. The carrier disconnection state may be artificially created on the modulation side to start communication, or if the line is 111
″:I It may also occur due to harm.The state changes from 111 to 11 when the carrier is turned on.
0 and receive in 4-phase form, the TA in Figure 2E,
TB in FIG. 3A, and TD in FIG. 3F, and TD,
address. At the same time, time is monitored by a counter constituted by a register C shown in FIG. 4B, and by obtaining an ON signal indicating that a predetermined time has elapsed, the state changes from 110 to 101 and automatic equalization is started. At step 110, the coefficients of the automatic equalization transversal filter are inputted to the output T of FIG. 2D, 1 is input only to the appropriately selected coefficient ri, and 0 is input to the others. δ1 is all O. At 101, the addressing change of each of the above tables continues. When the counter output turns ON, the state changes to 100, the addressing change of each table is restored, and when the counter output turns ON again, the communication state becomes 011. FIG. 4B shows a circuit implementing the above-mentioned control. The processing of this circuit is variable! This is done for each Niremen Y. C in FIG. 4B is a register, which measures time by accumulating l for each modulation element. K is a predetermined value and is subtracted by C. Whether the result is positive or negative is determined by a table called T1, and output lines indicated by ON and OFF respectively display whether or not the count exceeds a certain value.

The contents of C are reset by the table output Tb. The reset) signal, ie 0, is gated by the table Tb and input to C. The gate signal applied to Tb is input to the register S in FIG. 4B.

and 011. As a result, C is reset in this state. Counting shall be performed in the 1st to 3rd phases, 110. That is, as soon as the first phase is entered, the reset of C is removed and counting starts. 101
, 100, but when the failure value of C exceeds K, it is detected by the matrix M, and a reset signal is sent to C. M. The diode matrix detects the state of the register S, and the diode matrix M detects the state that the register S should take next. These are s
[fit' in Figure 4 A, as defined by the figure. This transition is performed by the connection DR. The 1 input in FIG. 4B is produced by the automatic gain adjustment circuit described below and indicates whether a modulated signal is being received. Also, 2
, 3 is a signal for changing the table address already mentioned and changing the automatic equalization JI'J) run parsersal filter coefficients. In the i4B diagram, the T& content is set so that the T output turns ON when the count value of C is greater than or equal to 110, 10.
In the state of 1,100, C is reset by turning on the T& output. On the other hand, this ON signal causes 110→101, 101→1001 or 100→0
11 must occur. To allow sufficient time for the effect of turning on to appear, it is necessary to reset C at the 4th B in any modulation element.
This is the final step in processing the diagram. For this purpose IJ3!3
It is necessary to temporarily record the reset signal in the work memory of 1i. FIG. 4B shows double-line processing and single-line processing, and while double-line processing is signal processing in byte units, single-line processing is logical processing in one-bit units. Also, in the f31+2 phase, the second
The contents of each block marked 1 in diagram F are set to 0 and parallel equalization is stopped.

Next, a start sequence on the modulation side for the above-mentioned I side is determined.

The start sequence on the modulation side is determined corresponding to the start sequence on the demodulation side, and the state diagram becomes as shown in No. 4011. That is, it enters the first phase state due to the backward signal signal returned from the demodulation side through the backward channel. When the backward signal is turned ON, it means that the demodulation side is already in a 2-phase or 4-phase reception state. On the modulation side, 2-phase or 4-phase variable W, 1 is also transmitted in the first phase. As shown in C and its attached circuit in FIG. 4D, the same count number n1' as on the demodulation side is performed. Reverse W'4 (Count the same number as II, change from the 1st phase to the 2nd phase t, +,, from the 2nd phase to the 3rd phase, and from the 3rd phase to the letter of communication. The second phase does not need to be distinguished from the other in terms of operation, but it is divided into two for time adjustment with the demodulation side.In the 1st and 2nd phases, data signals are prohibited and input to the modulator. Activate only the scrambler for a certain data code, change the address of the table that creates the modulation code shown in C in Figure 1A, and make sure that double codes are output to each of the two output terminals of C.Third. In the phase, the automatic equalizer is operating on the demodulation side, and since this is the time when demodulation is ready in multiple states, the address of C in the @I person figure that was used up to the second phase is Cancel the changes,
Perform multi-state modulation while inhibiting data signals.

The communication state is entered by C in FIG. 4D counting out. Of course, the demodulator side is already ready for communication. The reason why the demodulation side causes the canonical transition first in this way is to take into consideration the fact that there is a delay in transmitting the ON-OFF signal through the back read channel, and that there is also a transmission delay of the data channel. This delay is desirable for proper operation. FIG. 4D is a processing circuit diagram created according to the state transition diagram of FIG. 4C. This is the 48th
It performs almost the same function as the start sequence circuit on the demodulation side shown in the figure. The symbols in FIG. 4D that are the same as the symbols in FIG. 4B perform the same role or function. The backward signal, which is the input signal in FIG. 4D, is 0N-O
This is an FF type circuit, and the circuit near the baraqua signal terminal in Figure 4D detects the rise and fall of the above signal, and uses a register T to compare the value before l modulation F. The difference is taken, and the difference signal is sliced according to a table called To and converted into 0N-OFF.Only the rising time of the crossword signal is turned on, and the rest are turned off.Also, as shown in Fig. 4D. A table address change command is added to the input side of the table C in FIG. 1A to act to change the address.

Further, the data input inhibit terminal is used to prevent a terminal to which a data signal is input, and to operate only the data code scrambler.

The carrier ON-OFF signal develops the start sequence as described in FIG. 4A, and the detection of this signal is closely related to the automatic gain jJM adjustment function. The automatic gain adjustment function, ie, AGC, amplifies the signal input to the demodulation circuit, and the amplification factor of the AGC signal is automatically adjusted so that the level of the detected signal becomes an appropriate value. The relationship between the processing circuit related to AGC and the analog amplifier circuit is as follows. First, if the signal gain of AGC is α←), then α(Suke's comment! #, Wb formula becomes.Here, B
r, )---(4,2), ...(4,s). The block indicated by the dashed dotted line AGC in Fig. 4E is
The received modulated wave applied to the terminal IN is converted into a digital quantity by an analog-to-digital converter called A/D. The conversion characteristics of the A/D are designed such that the logarithm of the corresponding output digital value is proportional to the input analog value. The output of the A/D addresses a read-only memory called I' (OM). In this ROM, the relationship between the address value and the output value read to the output path is the logarithm of the address value and the output value. R so that the values are directly proportional
The recorded contents of OM are defined. This is a known method for preventing the quantization noise of the A/D output from increasing in a very small signal with a 4G value.

The number of processing bits in the AGC block is 3 to 4 bits larger than in the non-AGC portion.

■ in this block is ROM by the output of T.
The output value is multiplied and outputted to the OUT terminal at a level suitable for the demodulation type processing connected after this processing block. In the processing blocks after the 0LIT terminal, the lower 3 to 4 bits of the α block output logic value are removed to perform operational processing.

Digital signal processing is performed by a processing unit made up of logic devices, and the input/output signals thereof must undergo analog-to-digital or digital-to-analog conversion. In particular, even when the input signal is received at a low level, it is necessary to use the method described for AGC in FIG. 4F above to avoid quantization noise.

Each processing circuit number explained in Section 1N4 is executed by digital signal processing, and in addition, filter processing to separate the backward channel and data channel in the transmission/reception ink face of the line, and 2-wire Balance processing to eliminate crosstalk between transmission and reception due to unbalance that occurs when converting a 4-wire system to a 4-wire system is similarly implemented using digital signal processing. FIG. 41 shows the connections among these processing blocks and the peripheral circuits necessary for digital signal processing.

First, on the modulation side, the transmission code circuit is shown by S in Figure 4F. This is the circuit that creates the circuit in Figure 1A, and if f7'
The terminal accepts the transmitted code, which is the output of the data terminal equipment. The inside of S is the scrambling of the SD code and Ki
SD by the "data human power connection" signal in Figure 4D of the double signal
Signals are prohibited.

(b) Transmission wave output path: Digital signal processing to create the transmission wave is performed by the MOD shown in Figure 4F, and its output signal is input to the SFD that performs transmission filtering processing for combination with the backward signal. . BL is LIN, as described below.
This is a circuit that converts the 2-wire line E from 2 wires to 4 wires, and this circuit performs balancing processing to compensate for the lack of return loss between transmitting and receiving caused by unbalance in the 2H4 block. The output signal Bl of the SFD,
It is input from 4 terminals and output from 2 terminals. This signal is converted to an analog signal and sent to LINE via 2H4.

(c) Backward circuit: Receive data channel and RFB
5 and RI"B by a frequency division method through digital signal processing of filters.

RFB is also F received from the backward channel.
Detection of the M signal is also performed by digital signal processing, and its output is applied to two terminals of MOD.

Next, on the utility side, (a) Modulated wave receiving circuit: The process of detecting a detection signal from the received modulated wave and reproducing the modulation code is performed in the DEM shown in FIG. 4F. The input signal is input to the AGC from the 2'tfj type circuit called -LINE together with the own station transmission signal suppressed by 2444. The inside of AGC is AG in Figure 4E.
aT as shown in C 4. 3 of DEM in AGC of figure F
The output from the DEM that has undergone processing other than the AGC shown in FIG. 4E is added to the terminal that is input from the terminal. Among the bits processed by AGC, the low-order 3 to 4 bits are added to the BL 1 terminal, and the local modulation signal leaked from the transmitting side is removed from the BL, and filtering for the data channel called RFD is performed. The data variable leap wave is input to the DEM separately from the bank word channel.

(b) Backward circuit: This circuit is constructed by processing the FMS block shown in FIG. 4F. FMS4DEM
Digital signal processing is performed to perform FM modulation to create a backward signal using the carrier detection signal in the process of FIG. 4B in the process shown in FIG. added to.

(/Now received code circuit; The circuit indicated by R in Fig. 4F takes the difference between 'klbk' in Fig. 2F and reproduces the transmitted code. This part is as shown by the line 1 in Fig. 4F. It is necessary to connect to the automatic equalization change terminal shown in FIG. 4B.

This is to inhibit data reception and output before operation is established in the start sequence.

The BL shown in FIG. 4F is used as a circuit for maintaining a sufficient return loss between transmitting and receiving, and the operational formula for the function of this part is as follows.

tlS4G Figure (a) is a diagram of the principle of this signal processing, and 2-
The transmitted signal Xj applied to the lip transducer is TR3
Add to the transversal filter. y- is 244
The output of the four circuits includes components leaked from Ij. X′
yj-k' is created by 0 at the output of TR8, but at this time, the tap of the transversal filter is adjusted so that j' is equal to the value subtracted from Xj by 7j. This adjustment algorithm is created as follows. Assuming that the transmitted signal is X and the tap coefficient of TR8 in Fig. 4G (a) is Cθ), the output of TR8 is
= 1''.Here, we create a correlation function of God) - (y -) C') x Then, the component Ij is not included in 7j-"j' in FIG. 4G (&). Here, xj(r) is a function obtained by delaying Xs by 2 seconds. In this case, when minimizing 83 while keeping τ fixed, the following points need to be noted.

That is, when removing the component proportional to town from 1jX3', if τ remains fixed, -1 can become 0 even when controlled to be delayed by the transversal filter. At this time, litansis does not improve at all. To eliminate this concern, it is necessary to consider a function that integrates - within a range of τ that is larger than the delay that may occur in the transversal filter. In other words, consider an algorithm that minimizes . First of all, it becomes. Here, since axj'/a an(j)=xj-n, it becomes as follows. Here, α1 no xj(τ)2 aτ can be considered a constant, and after all, τ does not affect the alprism. Therefore, the adjustment operation formula for the tap coefficient is: a, (j+1) = o, (j%βCyz -x:>
x*, -m (4, y). m4G diagram (
b) shows the internal structure of the block BL in the m4F diagram and the connection between AGC and D/A. M in Fig. 4G (1)) is a terminal of 1,2°3.4, and TR
A memory shared by processing units 3 and TAP, which exchanges information bytes between them, and each exchange is performed by time-divisionally allocating slots for accessing M. be exposed.

TR3 processes the equation (4, 4), and TAP processes the (4
, 7) Calculate Eq. The eastern line is 籟(j)(n=1～
N) represents the transfer.

Note that the details of the peripheral configuration of the common memo IJM in FIG. 4G(b) are the same as in the case of DEM and MOD, which will be described later, and will not be described in detail here.

Next, the RFD and SFD measures shown in Fig. 4F use a known digital filter method, which allows 6
A transmission channel for data signals of 00 to 3000 Hz is created. FMS and RF for backward channel
B performs filtering and processing using a low-speed FM modulation method. Of these, for filtering, 300~
This constitutes a backward transmission channel for 600H. Among these, the operating formula of the FM modulation and demodulation method is that on the modulation side, that is, on the FMS, the transmitted modulated wave is sample m.
(nT')m oosφ(nT')φ han')−φ(
n-1) T')-HatoT'+ μI, IC-TI
))...(4,8). Here, a'(n'll'') is the DEM of Fig. 4F.
This shows the signal on the input line from to the FMS in the same figure.

The sampling interval of this formula is (4,7) I (4,6
), and then it becomes an integer fraction of T. town.

is the carrier frequency of the bank word channel.

It is appropriate that the operating equation on the demodulation side be of the VCO type, and the detected signal S (n'l'') is generated using the following sample value operating equation.

The received wave, that is, the output wave of RFB filtering! If T'), then it becomes. (4, s> t When the equation (4, 9) is expressed in a processing graph, it becomes as shown in Fig. 4H (&), (1)).

The device circuit configurations of RFD, SFD, FMS, and RFB in Figure 4F are the same as those in Figure 4G (b), but the configuration method for these is the same as in the case of DEM and MOD described later. Therefore, it is omitted.

CL shown in FIG. 4F is supplied with four clocks from a voltage controlled oscillator indicated by CO in the same figure, thereby supplying the other pullers with a loop for digital signal processing and logic processing. It is necessary to establish timetables for each of these four tasks. There are quite a number of these timetables. These timetables can be realized using a small number of LSI elements. Figure 41 shows OSC and -■C
A high-frequency main clock source such as O is provided. This corresponds to ■CO in FIG. 4F. A counter is provided to count the output, and in the output value read from the read-only memory using the output gU value as an address signal, the timetable of the logical value of each digit is added to DBMl or MOD in Fig. 4F. It is possible to set up the self-answers in read-only memory so that a timetable of timetables is obtained. Be in FIG. 4 is the counter of the above-mentioned main oscillator, ROM is a read-only memory, RR is an output register, terminals 1, 2 . ...
N is a clock line taken out from each digit bit of RR. In the case of a gain adjuster, the main four sources are the voltage controlled oscillator■C
Using the clock terminals 1, 2t, . 11 and 2 of CL in FIG. 4F are multiphase clocks having the period of the modulation element, and 3
The clock is a higher frequency polyphase clock.

The operation of the 5-digital signal processing circuit modulation/demodulation system can be expressed in the form of an operational equation by analysis as shown in the specification of the prior application. Weird 0! The adjustment function is performed by processing such a motion equation into IPi. It is necessary to rationalize these operating equations by mathematical means, ignoring the feasibility of using modulator/demodulator components and device circuits. Next, various means can be considered when attempting to realize a modulation/demodulation function by processing these operational formulas. When considering an application to a voice telephone line, the above-mentioned processing does not need to be particularly fast, and it is advantageous to use a computational zero-type processing unit that allows flexibility in the execution of the operational formulas. In this case, the above-mentioned operating equation cannot be used as is; it is necessary to convert it into a sample value operating equation. This is as described in each section above.

If the modulation/demodulation function is to be performed by calculating the sample value operation formula, it is necessary to implement the apparatus shown in FIG. 5A.

FIG. 5A shows the internal structure of the MOD of FIG. 4F. 5th A
Terminals 1.2.3.4- in the figure correspond to the same numbered terminals in FIG. 4F. The terminal numbered 3 in Figure 5A is (1, 1S)
The transmitted wave determined by the equation is outputted through the interface circuit 5.

A signal for inhibiting and opening the transmission code circuit is outputted to the terminal 1 in accordance with the state diagram of the start sequence on the transmission side shown in FIG. 4C. Click D relays this signal. The terminals ヰ are terminals for inputting the output signals of the transmission code circuit, that is, a□ and b□ of equations (1, 15) to the DEM. Further, the terminal 2 is a terminal for inputting ON-OFF (i) of the bank word channel necessary to control the transmitting side start sequence in the fg4C diagram.

The clocks A, B, and C in Figure 5A are for executing the modulated wave creation) graph shown in Figure 1A, where A is (a) in Figure 1A, B is (b), and C is (c ) and processes the start sequence on the transmitting side shown in FIG. 4C. The east line 5 in Fig. 5A indicates the output line 5 of the clock generation circuit CL shown in Fig. 4F, which supplies operating clocks to each block from A to G in Fig.
9.6.4.8.2.4KH and real-time interleaved clocks are supplied to B and C, respectively. RES in Figure 5A
This block is a common memory and is a temporary memory for information for exchanging information between each block called ANG. In order for each block of A to G to access the RES in order to exchange information with other blocks, it is allocated access slots by a gas cut allocator operated by an operation called MPX. conduct. The output line of MPX consists of several bits, and each clock is designated by its code structure.

A common line called BUS is used for each block to address the RES in a given time slot and exchange its contents.

The line that addresses RES is the output line of MPX, and BUS
is used to transfer information.

Blocks A, B, and C in FIG. 5A are computer-type processing units, and A is 9-6K.
R every time a Hz real-time clock interrupt occurs.
The information content corresponding to the clock H in Figure 1A recorded in a specific address of the ES is read and the information content in Figure 1A (
Process the &) part and RESO the resulting f(-T)
Record to another specific address. The contents of this record are as follows:
When G in the figure is given a slot, it is read out, converted to an analog signal, and sent to the line. In humans, the execution of the last command causes the next 9.6
KH enters real-time clock waiting state.

Next, B executes a program that calculates the part (b) in FIG. 1A by being interrupted by a 4-8 KHz real-time clock. The execution result is fX
This corresponds to block H in the IA diagram, but its contents are R
It is recorded at the address specified for BS H. The input data used by this program are λ in the whistle IA diagram and "kZ bk" in Figure 1C, and the RES address specified for these data is determined by the processing in block C in Figure 5A. The last instruction of the program for the above processing in B is updated at the following 4-8 KHz
This function waits for four interrupts.

Next, C in FIG. 5A is 2.4KI-1, the part (0) in FIG.
Run a program that executes a start sequence represented by a diagram. The 0 function of this program is expressed by the flow of logical processing and arithmetic processing.
This is diagram D. Of the program executed by C in FIG. 5A, the 10 input in FIG. 1A (0) corresponds to the feeding terminal in FIG. This is recorded at the designated address of RES in the slot given to G from MPX.

Next, the digital processing circuit on the demodulation side will be described. Figure 5B shows the internal foam formation of the DEM of Figure 4F. Terminals 1, 2, 3, 4, 5, and 6 in FIG. 5B correspond to the same numbered terminals in FIG. 4F. The output of the data channel reception filter indicated by RFD in the i4F diagram is applied to the terminal 4 in the 8\5B diagram.

Also, the signal output from terminal 2 is A in the g5B diagram.
The timing signal calculated by the computer-type processing unit lCl-5, ie, Z(kT,) in FIG. 3F, is converted into an analider by F and output. In the switch S shown in FIG. 4F, the above Z(kT,) is as shown in FIG. 3G,
As shown in Figure 3H, it is disconnected when used to adjust the delay of the automatic equalization filter. The terminal 1 in FIG. 5B sends a signal that inhibits receiving data in the 1st and 2nd phases generated by executing the receiving start sequence shown in FIG. 4A, that is, by the output 2 in FIG. 4B. put out. Terminal 5 in FIG. 5B is the signal that initiates the start sequence described above, namely
It is connected to the terminal with the symbol A, which indicates carrier disconnection in the figure. The carrier disconnection in FIG. 4E and the process for creating the AGC control signal are shown in A in FIG. 5B.

01~. It is calculated by the processing unit of The terminal numbered 6 in FIG. 5B contains the modulation code determined by the demodulation process at A, C, . . . , ak in FIG. 2E.

A signal bk is output. Also, the terminal numbered 3 is A
, C1 to C3, which output the processing results of the parts other than the AGC in the @4E diagram, and this signal is processed by the AGC in the ff14F diagram.
The signal is input to an automatic receiving gain adjustment circuit including D conversion.

0, E, F, G, H, J connected directly to the above terminals
etc., includes a temporary register for signals input and output from the above terminals.

For example, relay registers and processing units A, C, ,C,.

C1 shares a common register called RES in a time-sharing manner,
This makes it possible to transfer byte signals between them.

Each block accesses the RES in order to exchange information with other blocks using the MPX shown in FIG. 5B. The method is the same as in FIG. 5A.

At A in FIG. 5B, a real-time clock interrupt of 9.6KH is performed. This time, read the signal at point 6 in Figure 2A that is recorded at a specific address in the RES, perform the processing in the part (,) in Figure 2A, and then
Record the signals 9 and 10 in Figure A to another specific address in the RES. This recorded content is read when 01 in the m5B diagram is given a slot. At A in Figure 5B, the last instruction is executed, resulting in the next 9.6K
Enter the waiting area of the Hz real-time truck. next,
C in FIG. 5B executes a program that calculates the portions in FIGS. 2c to 2F by 11 in response to a real-time clock interruption of 2.4 KH.

The execution results are input to the designated address of the RES that records the signal values ak and bk in the m2E diagram.

When C1 is given a slot to access IIES, 608θ and s necessary for the processing in FIGS. 2C to 2F
Inθ is read from the specified address of the RES where each is recorded. This record is created by the processing of C8. The last instruction in the above processing in the CX is to wait for the 2.4KH interrupt.

Next, C8 in FIG. 5B is processed by a 2.4 KHz real-time clock interrupt. The processing contents are automatic phase control shown in Figures 3A to 3D, and 3F.
3F to 3H. The input/output signals of automatic phase control are X'(kx,), Y as shown in Figure 3A.
'(kT,) and &kT bkt? It is transferred from C0 via a specific address of RES and -aos (I and sin θ are also transferred to C□ via another specific address of RES. Also, the program that automatically controls the timing is as described above. &, Y'e ake
2(kT, ) produced by bk is transferred to the clock H connected to terminal 17 in FIG. 5B via a specific address of RES. C6 in Figure 5B is also processed by the 2.4KH clock interrupt, resulting in the state 91 shown in Figure 4A.
The start sequence represented by ¥1 and the AGC function shown in FIG.

FIG. 4B shows the 44 functions of the program shown in FIG. 4A in terms of logical processing and arithmetic processing. E,
F, G, J Naru Pussytsuku tokoro! 1! The processing unit in the above description of communication between units is 08. In addition, x' and y' from C.

ILk and bk are transferred.

Figure 5C is A, B, C of Figure 5A, A of Figure 5B *
``C1t''B, C11 shows the internal structure of each processing unit.The structure of the processing unit shown in FIG. .When using the processing unit as shown in FIGS. 5A and 5B, the so-called I10
Although the connection file is not used as in the case of a general-purpose computer, it is connected to the external data bus and control lines shown on the left side of FIG. 5C. In the case of Figures 5A and 5B, these I10 devices will be temporarily connected to perform some processing before operating as a modem.

In the conventional system configuration method, the microcode block, controller block, data bus block, memory management block, system path interface, etc. shown in FIG. This is what is being done.

Therefore, in the conventional method, as shown in FIG. 5C, the tangents M and lines between each block create many intersection points. However, since these wirings were performed by wiring outside each monolithic structure, there was no problem.

The present invention realizes all the blocks shown in FIG. 5C with a "monolithic structure."
%9. The above-mentioned crossover point makes it extremely difficult to implement with d-circuit technology. In the present invention, the 6th A
The method of the present invention is applied not only to the internal structure of each block shown in FIG. That is, the method shown in FIGS. 6A to 6■ is! It is formed by filling in the part removed by etching the sea urchin of 1 with another material. For example, each block shown in FIG. 5C is not connected in the same layer. , the connection lines of each block are grown to a different processing layer, and the above-described etching process is performed in that layer to connect the blocks. If crossover occurs again during this connection, that wiring is stopped, another layer is stacked, and the terminals that could not be wired are grown up to this layer to make the connection. According to this method, it is not necessary to form each block in FIG. 5C on the same layer, and it is possible to connect the blocks even if they are formed on different processed layers as described above. According to the method shown in FIGS. 1 to 6A, it is considered that the small stop can be improved more than the conventional method, and therefore, the number of integrated circuit devices in one layer can be increased. Furthermore, if each block is formed in different layers, it is possible to reduce the number of devices in each layer.
More devices can be accommodated on a monolithic integrated circuit.

The outline of each block in FIG. 5C is as follows.

The data bus block provides the data manipulation functions required by the processing unit and is operated by a series of microcode instructions retrieved from memory in the microcode block. In this case, the address of the memory to be fetched is specified by the controller. The main subsystems of the data bus block include register array shifters, arithmetic circuits, etc.

The controller block includes a microprogram counter that stores the address of the microcode memory and a counter that controls flashing of the microcode memory loop. It also includes a stack for storing the values of my clip quadrature counter and loop control counter.

The memory management block specifies the 71 address of the data memory and manages communication between blocks on the data bus. Also, some simple data structures ν1 can be formed in the data memory. In this case, this block divides the memory into areas of 1/) < iJl, and a different data structure can be realized in each area. There you will find stacks, queues, linked lists,
Another basic data structure called an array can be realized. When performing transversal type processing, the microcode G uses an array as a memory as a data structure.By specifying whether to shift data on the array to the management block or read the value of an element on the array, the management block can be performs various operations on the shift register.

The system bus interface communicates with other processing systems through the illustrated system bus.

The system bus enable in FIG. 5A is connected to the BUS in FIG. 5A, and the system bus enable in FIG. 5C is connected to the MPX in FIG. 5A. Of the outputs, − can be made to correspond to those wired to each processing unit. i5A figure glue,
E, F, G, and @5B figure glue, B, F, G, H, I
, J, etc. have the same structure as the system bus side of the system bus interface block in FIG. 5C. The above also applies to FIG. 5B.

The RIP clock block generates the operating clock signals necessary for the system, but when it can be driven from each part as shown in the operating clock lines in FIGS. 5A to 5B, the external flag terminal in FIG. 5C is used. are 2, 4, 4.8 in Figure 5A
, 9.6KHz terminal, and 2 in Figure 5B.
4, 9.6KH, is connected to the terminal.

Next, a microfabrication method and an etching method applied to connections between blocks in each processing unit of the present invention will be explained.

6. The steps involved in making a 4.1-piece integrated circuit by microfabrication include etching a film-like material. To perform etching,
An original plate called a mask is required to create a resist image. A mask works like a photographic plate, and is produced by reducing the size of the object to be processed by obtaining a photograph from an original drawing that has been enlarged to a size that is 10 to 100 times larger than the object to be processed.

To perform this processing, first, a resist agent is applied to the surface of the wafer to a uniform thickness, and after hardening,
Irradiation of light, electron beams, or generally radiation through a mask. A resist agent is a material whose solubility in a specific chemical solvent changes when irradiated with radiation. Mask C
A window corresponding to a pattern of a specific processing device is drawn using a well-known electron beam lithography method or the like. Next, the portions of the resist agent that have been irradiated with radiation or electron beams that have passed through the window of the mask are altered by radiation or electron beam transfer. When positive-type coating is performed, only the altered parts are dissolved away, creating a film pattern of resist agent on the wafer. Next, by a wet or dry etching process that dissolves or removes the wafer, the portion of the wafer to which the resist agent is not attached is removed to form part of the planar fine structure of the intended device.

The present invention enables a layered fine structure, and the necessary conditions for this are the above-mentioned process of forming a second wafer to fill in the portions removed by etching the first wafer. must be possible. Now, if another material is grown on the etched first wafer to form the material for the second wafer, the surface of this second material will be covered by the material of the first wafer. A depression will appear in the removed area. The material on the second wafer other than this edge is removed. For this reason, the following processing is performed. A resist agent is again applied onto the second material, and a maintenance process is performed in which the resist agent on the second wafer is irradiated through the mask used when processing the first wafer. Kneading becomes a negative development. That is, the resist agent in the portions that have not been irradiated and has not changed in quality is removed, and the material in the removed portions is etched. Thereafter, the resist agent is removed. At this time, if a reverse pattern of the mask used for the first wafer is used, a positive developing process is performed.

That is, the resist agent in the portion that has been altered by irradiation is removed, and the material in that portion is etched.

FIG. 6A shows an example of forming a structure consisting of three-dimensional distribution of two different materials by the above method, in which devices 20 are formed on the surface of the semiconductor wafer 10 using microfabrication technology or the like. A protective film 30 is usually formed on its surface. FIG. 6A (g) shows this situation.

The protective film 30 contains %S, 0. An oxide film such as the above is used, but an insulating film such as a resin may also be used. Next, the 6th A
As shown in Figure fl), an opening 40 is formed in a desired portion of the barrier film 30 by the method described above. After that, as shown in Figure C), another forest material 50 is formed on the upper surface of the protective film 30 including the openings 40. Next, as shown in FIG. 6A0, this material 50 is added to the material 50 in FIG.
), only the opening 40 that has been etched is removed by etching. At this time, it is necessary to consider the combination of the protective film 30 and the material 5o so that the protective film 30 and the material 50 are not etched at the same time. Next, as shown in FIG. 6A (1), a protective film 31 is again formed on the surface. Below, this protection M31
By repeating the same steps as those used in FIGS. 6A (A) to (D), a structure as shown in FIG. 6A (F) can be obtained.

Each processed layer in the multilayer process shown in FIG. 6A has its own thickness. This causes side etching. In FIG. 6A, this side etching and raised development on the sides are ignored.

When side etching is performed, the 011j plane of the processed layer pattern is etched from the edge of the resist, and the finished dimension L becomes smaller than the resist dimension LR. 6th B
Figure (A).

(13) shows this situation, where θ is the resist, ■ is the processed layer, and the exposed substrate. (A) is etching el,
(B) shows the state after etching. The magnitude of side etching is expressed by the conversion difference LR-Lp, which increases in proportion to the thickness of the processed layer 41. Therefore,
With the process of the present invention, bulges may occur at the material seams, the magnitude of which depends on the magnitude of this side etching. The dimensions of the mask are determined in consideration of the size required to eliminate protuberances by utilizing these side etchings. Figure 968 (C), C
D).

(E) shows the results of the steps shown in FIGS. 6A, (B), (C), and (D) performed by performing side etching as described above, and thereby adjusting the protrusions that occur at the joints of the materials. Therefore, the interface between the two structures shown in m6AI'21(F) is actually not as smooth as shown in the figure. From this, the dimensional accuracy of these three-dimensional structures is determined by the size of the side etching.

According to the above method, it is possible to create a three-dimensional distribution of multiple types of materials. In the present invention, these methods can be used to construct a multilayer system in which a plurality of planes are stacked, and FIG. The two structures shown in Figure (F) allow connection with an electronic circuit device system that is further laminated on the top surface.

If the material of the structure 2 in FIG. 6A (F) is conductive, it is possible to couple the upper and lower layer systems by light,
Electrical coupling is possible with conductive materials.

Next, regarding the internal structure of the device, p-type and n-type
distribution of shaped semiconductors is required. For this reason, the method shown in FIG. 6A cannot be used as is, but by modifying these methods depending on the material used, a three-dimensional distribution of pn junctions can be created. First, when using a single-crystal semiconductor such as single-crystal silicon, the single-crystal semiconductor is grown in vapor phase on a conductor substrate, and then an oxide film is grown in vapor phase thereon. Apply a resist film on top of it,
Particle beam irradiation is performed on the part to be made into n-type conductor 0, and the unirradiated acid ([1) is etched to thermally diffuse the n-type impurity.

The remaining oxide film is dissolved and an oxide film is again grown in a vapor phase over the entire surface, and a similar process is performed on the portion to be the p shadow region to perform p-type diffusion. This method lacks flexibility in terms of three-dimensional construction because it is necessary to remove the conductor substrate by etching, as will be described later. To provide flexibility in construction methods, the substrate may be a MAR material. In this case, if an attempt is made to form a pn'lj (junction) using the method described above, the semiconductor part will become polycrystalline, making it impossible to diffuse impurities. To create a three-dimensional distribution, an amorphous semiconductor is used instead of a single crystal semiconductor.This is formed by direct current glow discharge decomposition, and contains PHIg as an n-type impurity.
B, H, etc. are used as P-type impurities, and to dope these, SH, H, etc. are used as in the case of single crystal silicon.
PH, or B.

This is done by mixing Ho.

6C and 6B show that the method of FIG. 6A is applied to the case where a MOS device is constructed using a semiconductor such as amorphous silicon. In Figure 00, (A)
is 2 on the insulating substrate 10 by the above glow discharge.
The results of a process for forming a semiconductor containing a p-type impurity of zero are shown. Next, (B) is obtained by etching 20 of (A). This is done by a dry etching method using a resist image, and etching gases such as CF, CF, +O, CF, +N, etc. are used. In (C), vapor phase growth of oxide is performed on the entire surface of (B) to form an insulating film 11. In (D), the part above 20 of 11 is etched. In this case, the insulating film is 8□0. In this case, an etching gas different from that used for etching semiconductors is used, such as HF gas. (E) In (
Vapor phase growth is performed on the entire surface of the structure of (F) such as a m-oxide film.
), a window is opened above the p-type semiconductor 20, and (G)
The same p-type semiconductor 21 is grown and etched by the above method to form a structure (H). Here, in (H), 12
The portion of the insulator above the p-type semiconductor 20 is etched. Leave the resist section used at this time as it is, and (
The structure of (K) is obtained by growing an n-type semiconductor of 30 as shown in J) by the same method as that of the p-type semiconductor and removing the etching resist film. ff16
The processes shown in FIG. 3(b) (L) to (0) show the steps of making a MOS device and its electrodes using an insulating film 40 and a conductive material 50. FIG. 6C CP') is a MOS device constructed by the above steps, and O, θ, and O are its electrodes as also shown in FIG. 6C (0). ■ of e),
@ is a conductor shown by 2 in FIG. 6A (F), for example, and is connected to a lower layer electronic circuit device. The process of making (P) with O is shown in Figure 6C (A) to (0).
is not included. If the above electrode process is included, (A) ~
In addition to (0), four steps are added.

In the present invention, as described above, processing is performed so that the portion removed by etching of the WS I wafer is filled with a second wafer, and the spatial distribution of p-type and n-type semiconductors is is controlled by layers. As shown in 10.20 of FIG. 6A (F), when applied to devices made by conventional microfabrication techniques, it is possible to interconnect integrated circuits consisting of a plurality of layers. In this case, the layers other than the bottom layer become an integrated circuit including a system of devices as shown in FIG. 6C (P).

An example of the method for making an integrated circuit using the device shown in FIG. 6C (P) is as follows.

In other words, the configuration of the shell 1 (P) in the same figure (upper force) is as shown in the figure (Q
) The result will be as shown in the upper row (Q)■.

@, θ, ■, ■ correspond to the configuration shown by the same symbol in (P), and are electrodes of a device made at the same time as O20, ■, ■ [ma (P) in (Q). If this device is, for example, a diode, the pm of this diode is
The structure of the joint part is enlarged at the same time as each process from (F) to (0) in Fig. 6C. It is carried out once in parallel with the steps A) to (E), and is formed by growing an insulator in the same way as the parts other than the semiconductor part 20 in this step.

In addition, in the electronic circuit diagram using the MO8 type element, the resistor corresponding to the resistor is composed of the same elements as in Fig. 6C (P), and is configured in each step in Fig. 6C (P). , its terminal has the same configuration as Q, (2), θ, 0.0 in (Q). Connections between these differential chairs (li, Figure 6C (Q)
This is done by connecting the terminals shown in (Q) with a conductor, by growing only one layer of a protective film and a terminal conductor on the connection surface as shown in (Q), and depositing a metal conductor on the top surface. Etching is performed using a mask with the wiring pattern connecting the terminals shown in (Q) as a window. If cross-wiring occurs, the terminals and the protective film are grown in another layer, and the wiring is performed in the same manner.

According to the present invention, connections between devices are made by providing a layer that serves as a connection surface. If a situation occurs where the connecting lines cross,
Furthermore, since it is only necessary to create a layer that forms a connection surface, the problem of 1/1 so-called F-bodimentality does not occur as in the case of conventional integrated circuits. However, in order to reduce the number of steps as much as possible, connections between devices need to be made internally.

Another consideration for reducing process steps is the need to use a large number of devices in each layer to reduce the amount of material involved. In particular, when it is necessary to reduce the thickness of a layer such as the layer 40 in FIG. 6C, ie, the absolute ITJ layer in the MO84R structure, it is necessary to match the layers for other devices as well. FIG. 6D shows an example of such a process. ...5 is the layer number, and ■, @, and θ are bipolar transistors and circuits that use them, respectively, and devices that play the role of resistors.

Diode, and M for multiplication in Anamitsu circuit
It is an OS device. The three layers are, in the MOS device θ,
It is an insulating layer that serves as a base, and in (2), it becomes a semiconductor part that serves as a base in a bipolar structure. The diode @ does not require a particularly thin layer like θ, but in order to match the process with other devices, a p-type semiconductor layer process is included. 1 is an insulator and p
The conductor 2 consists of a conductor, a p-type semiconductor, an n-type semiconductor, and an insulator, and the other layers have fewer materials than the two layers. Therefore, the process shown in FIG. 6E is the same as that shown in FIG. 6D (P). With the above thinking, NAN
The basic device fabrication method required to create a logic circuit based on the D circuit is shown in Figures 6F and 6G. (
A), (B).

(C) are an inverter, NAND, and NOR circuit, respectively, and in each figure C, ■.

2 and θ respectively show a circuit diagram, a plan view of a multilayer structure, and a side view of the same multilayer structure. The numbers on the right side of the side view are the numbers of the chips. These devices are constructed in the same process, and a Wj 86 surface is formed on the top surface, and an etching stop for wiring is provided. If crossover occurs, the connecting surface will have two or more layers. Furthermore, memory circuits such as flip-flip are configured in the same manner, and the 6th G
The result will be as shown in Figure (D). Here, it is a MOS device such as Q641mQD diagram CP), and ■, @, and θ are a circuit diagram and a plan view, respectively. In the case of this circuit, in order to match the layers with those shown in FIGS. 6F (A) to (C), the configuration was such that the crossing or healding was turned around.

A similar basic circuit for logic circuits can be considered for bipolar transistors as well. This is Figure 6E C)
If the multiplication device shown in Fig. 6E is not used, the wiring is performed by nf of 5 layers of the ma number shown on the left side of the same figure.
A basic circuit can be created with four layers, which is fewer than a MOS device. FIG. 6H16■ is a basic NAND circuit using bipolar transistors corresponding to the MOS type NAND basic circuits shown in FIGS. 6F and 6G.

In the following description regarding FIGS. 68 and 61, the MOS device in the description regarding FIGS. 6F and 6G is replaced with a bipolar device.

Effects As explained above, according to the present invention, when parallel processing is performed by overlapping nf, it is divided at points that result in convolution of the sample value operation formula, and a processing unit is assigned to each division. Since the processing units are communicated through a common memory, digital signal processing with great flexibility in functional configuration is possible. As an example, a case where the present invention is applied to a modulator/demodulator is shown, but other devices can also be widely applied.

[Brief explanation of drawings]

FIG. 1A is a block diagram of an arithmetic circuit used in a modulation/demodulation unit showing an embodiment of the present invention, and FIGS.
Shift register A1 in the figure. Detailed view of part B, 2nd
Figures A and 2B are block diagrams of a circuit that processes equations (2, 11), Figure 2C is a block diagram of an automatic equalization processing circuit, and Figure 2D is a block diagram of a transversal filter adjustment processing circuit. Figure 2E shows (2,18), (2,19)
Figure 2F is a block diagram of the equation processing circuit, Figure 2F is a diagram of the circuit that calculates the predicted value of the output error of the serial automatic equalizer, Figure 2G is the circuit diagram of block N of the shift register, and Figure 3A is the low frequency A circuit diagram using a pass filter, Figure 3B, is a digital
Figure 3C is a diagram of the filter processing circuit, Figure 3C is a block diagram of the multi-lag filter circuit, Figure 3D is the m component of the circuit that replaces the clock N in Figure 2G, and Figure 3E is a block diagram of the mask clock oscillation circuit. , Figure 3F shows (3,9), (3,+
o) A diagram of the circuit that processes the equation, Figure 3G is a diagram of the timing adjustment processing circuit, Figure 3H is a diagram of the calculation processing circuit of the equation (3°14), and Figure 4A is the state of the start sequence on the demodulation side. The transition diagram and m4B diagram are block diagrams of the control circuit of the demodulator,
FIG. 4C is a state transition diagram of the start sequence on the modulation side, FIG. 4D is a block diagram of a processing circuit that performs the control in FIG. 4C, FIG. 4E is a block diagram of a received modulated wave AGC circuit, and FIG. 4F is a The overall system diagram of the processing circuit and peripheral circuits, Figure 4G is a signal processing diagram of the circuit that maintains return loss between transmission and reception,
Figure 4H is a processing flow diagram of equation (4,8) + (4,9), and Figure 41 is a block diagram of the clock supply circuit. F,
Figure 5A is an internal diagram of the modulation unit (MOD) in Figure 4F,
Figure 5B is an internal configuration diagram of the demodulator (DEM) in Figure 4F;
Figure 5C is A, B, C, C, ~C of Figures 5A and 5B.
8. FIG. 6A is a cross-sectional view of a toga structure consisting of three-dimensional distribution of different materials. FIG. 6B is a diagram of the multilayer process before and after etching. FIGS. 6C and 6D are 6
In Fig. A, a MOS device is constructed using a semiconductor material such as amorphous silicon, Fig. 6E is a cross-sectional diagram of cross wiring of O resistance transistor, @ diode, and θ calculation device, and Fig. 6F is a cross-sectional diagram of cross wiring of O resistance transistor, @ diode, and θ calculation device. The 6G diagram shows (A) an inverter and (B) a NAND. (C) NOR, (D) Planar and side views of multilayer configurations for storage devices, Figures 6H and 61 are (A) inverter, (B) NAND, (C) N. R, (D) is a circuit configuration diagram using bipolar transistors for a storage device. 10: semiconductor wafer, 20: device, 30 = protective film,
402 open bottom. ,? ? 11111 Figure 20 goh. 3rd A Figure X' (kT2) Y' (kT2) 3B (a) 3c (a) 3D Figure 4 B Figure 4c Figure 4 E Figure ρ ← Ω ← = = prisoner f Figure 4-G (a) Figure 4 H (a) Figure 6 A Figure 30 Figure 6 B Figure 6C Figure 6 D Figure 0 6th F E(8)

Claims (2)

[Claims] (1) In a device that composes a processing circuit that calculates a mathematically determined sample value behavior formula and performs parallel processing by overlapping the processing of behavior formulas with a large number of processing steps, the convolution of the behavior formulas and An overlap processing method characterized in that the data is divided at certain points, a plurality of processing units are assigned to each division, and communication between each processing unit is performed through a common memory. (2) The plurality of processing units are equipped with a modulation/demodulation function, and the connections between the four and the vines in the processing units for each division are made by thinly etching the plurality of layers by microfabrication and etching. An overlap processing method according to claim 1.