JPH06120990A - Orthogonal modulation circuit - Google Patents

Abstract

PURPOSE:To provide a QPSK signal with an image frequency component eliminated by providing a multiplier, adder, and subtracter and supplying the output of an oscillator and the output phase-shifting the output of the oscillator by 90 deg. to the multiplier. CONSTITUTION:When a signal string I, low-frequency carrier component fL, and phase shifter 13 output shifting it by 90 deg. are multiplied by multipliers 10 and 12, I(t)cos(2pifLt) and I(t)sim(2piLt)can be obtained. When a signal string Q, carrier component fL and phase shifter 13 output are multiplied by multipliers 14 and 15, Q(t)cos(2pifLt) and Q(t)cos(2pifLt) can be obtained. A QPS signal which is obtained by multiplying the output with an adder 16 by adding the output of the multipliers 10 and 15 frequency components (fc-fL) by a multiplier 19, multiplying the output subtracting the output of the multipliers 12 and 14 by a subtracter 17 by the output of a phase shifter 20 phase shifting the frequency component (fc-fL) by 90 deg. by a multiplier 21, and adding this by an adder 22 becomes 2(I(t)cos (2pifct)+Q(t)sim(2pifct). Then, no image frequency component is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quadrature modulation circuit used in a digital modulation system.

[0002]

2. Description of the Related Art Conventionally, as a digital modulation method, QPSK as described on pages 156 to 161 of "Spread spectrum communication system" published by Science and Technology Publishing Company.
(Quadri-Phase Shift Keyin
g) Modulation or the like is used.

A conventional example of this QPSK modulation circuit is shown in FIG. The I and Q signals, which are binary data series, are the first L
The band is limited by the PF1 and the second LPF2. First LPF
The output and the carrier wave cos (2πfct) are multiplied by the multiplier 3. On the other hand, the quadrature component s of the second LPF output and the carrier wave
in (2πfct) is multiplied by the multiplier 4. And
The outputs of both multipliers are added by the adder 5 and output as a QPSK modulated signal.

When the modulator circuit is to be constructed entirely of digital signals, it is difficult to realize it when the carrier frequency becomes a high frequency of about 1 GHz. Therefore, conventionally, the first and second LPs
Digitally configured up to F output, D / A converted
A method of constructing a multiplier with a balanced modulator as described above has been adopted.

However, since this balanced modulator has the transformer T, the DC component is not transmitted, and when the I or Q data series are all the same (all 1 or -1), no output is obtained.

To solve this, as shown in FIG. 4, the multiplier 7 multiplies the output of the low frequency QPSK generator 6 by a single frequency component of frequency fc-fL to obtain a predetermined carrier frequency fc. Up-convert. Then, the bandpass filter 8 centered on the carrier frequency fc removes the image frequency component generated by the frequency conversion.

[0007]

However, in the above method, if the frequency of the low frequency QPSK generator 6 is too low, the image frequency approaches the carrier frequency, and the band pass filter 8 cannot cut the image frequency component. As a result, the frequency of the low-frequency QPSK generator 6 has to be increased to some extent, which is not possible when the QPSK data rate is high.

The present invention solves the above-mentioned drawbacks and provides a quadrature modulation circuit which is not affected by image frequency components even if the frequency of low frequency QPSK is lowered.

[0009]

SUMMARY OF THE INVENTION The present invention is a first multiplication of a first signal sequence and a first single frequency component of a first frequency.
A second multiplier for multiplying the first signal sequence and a second single frequency component orthogonal to the first single frequency component; a second signal sequence and the first single frequency component; Or a third multiplier for multiplying by, a fourth multiplier for multiplying the second signal sequence by the second single frequency component, and addition of the first multiplier output and the fourth multiplier output, or A first adder / subtractor for subtracting, a second adder / subtractor for adding or subtracting the second multiplier output and the third multiplier output, a third single frequency component of the first adder / subtractor output and a second frequency A fifth multiplier for multiplying by, a sixth multiplier for multiplying the second adder-subtractor output by a fourth single frequency component orthogonal to the third single frequency component, and the fifth multiplier output. A quadrature modulation circuit comprising an adder for adding the output of the sixth multiplier.

[0010]

The first signal train I (t) and the first single frequency component f
Multiplying L and the second single frequency component obtained by phase-shifting it by 90 ° by the first and second multipliers, respectively,

[0011]

[Equation 1]

[0012]

[Equation 2]

When the second signal sequence Q (t) is multiplied by the first single frequency component fL and the second single frequency component by the third and fourth multipliers, respectively,

[0014]

[Equation 3]

[0015]

[Equation 4]

[0016]

Then, the output obtained by adding or subtracting the output of the first multiplier and the output of the fourth multiplier by the first adder-subtractor and the third single frequency component are multiplied by the fifth multiplier, and the second multiplier is added.
A sixth multiplier multiplies an output obtained by adding or subtracting the output of the multiplier and the output of the third multiplier by the second adder / subtractor, and a fourth single frequency component obtained by phase-shifting the third single frequency component by 90 °, If you add these with an adder,

[0018]

[Equation 5]

Therefore, the image frequency component is not generated.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a quadrature modulation circuit in this embodiment.

First, the input I and Q signals are band-limited by the LPFs 1 and 2, respectively. One of the LPF1 outputs is multiplied by the first multiplier 10 with the output of the first oscillator 11 that generates a low frequency carrier of frequency fL. The other output of the LPF 1 is multiplied by the second multiplier 12 with the output obtained by shifting the output of the first oscillator 11 by 90 ° by the first phase shifter 13. Further, one of the outputs of the LPF2 is connected to the third multiplier 14
Then, the output of the first oscillator 11 is multiplied, and the other output of the LPF2 is multiplied by the output of the first phase shifter 13 by the fourth multiplier 15.

The outputs of the first multiplier 10 and the fourth multiplier 15 are added by the first adder 16. Further, the output of the second multiplier 12 and the third multiplier 14 are the subtractor 1
Subtracted by 7.

Further, the output of the first adder 16 is the output of the second oscillator 18 which generates a frequency (fc-fL) component for converting the low frequency carrier component fL into the carrier frequency fc in the fifth multiplier 19. Is multiplied. The output of the subtracter 17 is multiplied by the output of the second oscillator output, which is phase-shifted by 90 ° by the second phase shifter 20, in the sixth multiplier 21.

The outputs of the fifth and sixth multipliers are added by the second adder 22 and output as a QPSK-modulated signal by the carrier fc.

Next, the operation of the above apparatus will be described.

When the first signal train I (t) is multiplied by the low-frequency carrier component fL and the output of the phase shifter 13 which is obtained by phase-shifting the low-frequency carrier component fL by the first and second multipliers 10 and 12, respectively,

[0027]

[Equation 6]

[0028]

[Equation 7]

It becomes Further, when the second signal sequence Q (t) is multiplied by the low frequency carrier component fL and the output of the phase shifter 13 by the third and fourth multipliers 14 and 15, respectively,

[0030]

[Equation 8]

[0031]

[Equation 9]

It becomes

Then, the output obtained by adding the output of the first multiplier 10 and the output of the fourth multiplier 15 by the first adder 16 and the frequency component (fc-fL) are multiplied by the fifth multiplier 19.
An output obtained by subtracting the output of the second multiplier 12 and the output of the third multiplier 14 by a subtractor 17 and a frequency component (fc-fL)
QPS obtained by multiplying the output of the phase shifter 20 which is phase-shifted by 90 ° by the sixth multiplier 21 and adding them by the second adder 22.
The K signal is

[0034]

[Equation 10]

Therefore, the image frequency component is not generated.

Therefore, the low frequency carrier fL can be set near DC.

In the above embodiment, the first adder 16
The output up to the output of the subtracter 17 and the output of the subtracter 17 may be digitally configured and these outputs may be D / A converted. It is also possible to make this digital part a ROM.

Needless to say, the present invention can be applied to other quadrature modulation circuits other than QPSK modulation.

[0039]

As described above, according to the present invention, even if the frequency of the low frequency carrier is lowered, it is not affected by the image frequency component. Therefore, the low-frequency part can be digitized even when high-speed transmission is performed.

Further, since the clock of the digital part can be lowered, the power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a QPSK modulation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a QPSK modulation circuit in a conventional example.

FIG. 3 is a circuit diagram of a general balanced modulator.

FIG. 4 is a block diagram of a conventional low frequency QPSK circuit.

[Explanation of symbols]

 10 First Multiplier 12 Second Multiplier 14 Third Multiplier 15 Fourth Multiplier 11 Fourth Oscillator 13 First Phase Shifter 16 First Adder 17 Subtractor 18 Second Oscillator 20 Second Phase Shifter 19 2nd multiplier 21 6th multiplier 22 2nd adder

Claims (1)

[Claims] 1. A first multiplier for multiplying a first signal sequence by a first single frequency component of a first frequency, and a first multiplier orthogonal to the first signal sequence and the first single frequency component. A second multiplier that multiplies two single frequency components, a third multiplier that multiplies a second signal sequence by the first single frequency component, and the second
A fourth multiplier for multiplying the signal sequence of No. 1 by the second single frequency component, a first adder / subtractor for adding or subtracting the first multiplier output and the fourth multiplier output, and the second multiplier A second adder / subtractor for adding or subtracting an output and the output of the third multiplier, a third adder / subtractor output and a third of the second frequency
A fifth multiplier for multiplying a single frequency component, a sixth multiplier for multiplying the output of the second adder / subtractor by a fourth single frequency component orthogonal to the third single frequency component, and the fifth A quadrature modulation circuit comprising a multiplier output and an adder for adding the sixth multiplier output.