JPS6057753A - Modulation-demodulation unit - Google Patents

Abstract

PURPOSE:To improve the permissible value for distortion and variation of a transmission characteristics by assigning each unit processing the operating formula by function, performing communication among units through a common memory and connecting the blocks to form plural layers by means of the minute processing and etching method. CONSTITUTION:The plural procesing unit A-C performing modulation-demodulation by operating and processing the smaple value operating formula assigned by function and obtain numerically and a common memory communicating the said units are provided. The block in the processing units A-C are connected by constituting plural layers through the minute processing and etching.

Description

TECHNICAL FIELD The present invention relates to a modulation/demodulation unit, and more particularly to a modulation/demodulation unit (modem) used for data and facsimile transmission over a telephone line.

BACKGROUND OF THE INVENTION In facsimile transmissions or other data transmissions carried out using voice telephone lines, modulation of 1'l'! utensils are used.

For modulators, the operating formula for creating the modulated waveform sent to the line and the operating formula for extracting the modulation code from the received modulated wave have been clarified, and the transmission characteristics of the line, compensation for fluctuations, and tracking of fluctuations have been clarified. Although it is required to calculate diagonal conditions, in the past, it was only possible to introduce these operating formulas, and the above-mentioned compensation and follow-up were not completely performed.

Therefore, the present inventor substituted the sampling timing into the time variable for the modulation/demodulation operation formula, automatic equalization adjustment operation formula, and demodulation clock timing automatic adjustment operation formula C, and created a sample value modulation/demodulation operation formula obtained by substituting the sampling timing into the time variable. , a sample value filter operation formula that separates the unnecessary wave distribution band and signal distribution band generated by sampling, and a sample value automatic equalization operation formula that suppresses the unnecessary waves are calculated at each sampling time. proposed a modulation/demodulation unit equipped with means (see Japanese Patent Application No. 56-147188).

However, there is a demand for further miniaturization and higher efficiency of the modulation/demodulation unit.

OBJECTIVES An object of the present invention is to provide a modulation/demodulation unit that satisfies such conventional requirements, has flexible wiring arrangement, and enables highly efficient transmission in a small occupied space.

Configuration The configuration of the present invention will be explained below by explaining the principle and examples.

The principles and embodiments of the invention will be explained in the following order. α)
Sample value operation formula for modulation function, C2) Sample value operation formula for detection, et) Sample value operation formula for synchronous control, (ex) Operation establishment function and digital processing peripheral circuit, (5) Digital signal processing circuit, (6) Fine Structure by processing.

The modulation/demodulation unit of the present invention has an operation formula that creates a modulation waveform,
Each processing unit that processes the operating formula for extracting the modulation code from the received modulated wave is assigned to each function, communication between each processing unit is performed through a common memory, and connections between blocks in each processing unit are made using microfabrication and etching methods. By forming a plurality of layers, the tolerance for distortion and variation in transmission characteristics is increased.

In order to configure a sampled value-based modulation/demodulation function with 1 variable and 11 functions, the C1 modulation/demodulation type is processed in real time by the sampled value processing unit. On the modulation side, an operating formula is created to create a modulation waveform that can be transmitted over a line whose frequency band is limited to the voice band and has frequency fluctuations.

The modulation waveform is expressed by the following equation (see the specification of the above application).

f(t)-A(t)ooss,'t-B(t)sinω
. 't...(1,0). Here ω. ' is the carrier frequency, which is the center of the transmission bandwidth, and A(tL B
(t) is an envelope waveform.

When this is created by a sample value processing unit, it is necessary to appropriately allocate sampling intervals for each function. First, it is clearly unreasonable to make the sampling intervals of the carrier part and the baud signal part the same in the above-described operational formula. Suppose that sampling intervals T and T are allocated to these, respectively. Furthermore, when considering where to set the boundaries between these parts, it is appropriate to set a baseband part with a sampling interval T0 in the middle of the image part.

Here, the sampling numbers for sampling the baud signal, baseband signal, and carrier signal are i, m, !, respectively. Let l be . Here, [X
] means that it is the largest integer that does not exceed the value of X.

In order to be able to evaluate the transmission characteristics of the carrier part using the transmission characteristics seen from the baseband, the modulated carrier wave should be treated as a complex number with the cosine term amplitude as the real part and the sine term amplitude as the imaginary part. This is expressed as F (t). There is a deformation of the transmission characteristics due to the connection of parts with different Sun and bling intervals, and to clarify this, consider two transformations of wmmTl and F (m Tl ). That is, Z
(F (mT, ) )=F(o)+F (T,) z
−'+F (2T,) Z ”+=Hp (de)...
(1, 2). When sampling the carrier signal, F(m
If the value T□) is held and 〆(nT) is obtained, then 2(〆(nT) )−F(o)H(p)+F(rl)
+F (2T,) H(p)p ”+ to H(p)p-
...-F(p”)Hω)=F'(p)...(C
5) Here pyc-,, xmT, / T and F(t)-, L, , u (t i Ts ) 6s
... is expressed as (1, 5). u(t) is a function for limiting the smoothness of the modulated carrier wave to the stratum corneum wave number range "1"< w < Ws ', and di is a complex number as shown below.

dl'''&1+ j bl a□, b□ are determined corresponding to each logical value combination of data bits included in modulation element 1. By performing two conversions of equation (+, S), F(z)-, l1lA, □A, n (mT, iTm
) eL□-1Σ1-x-M +11. -1'l', , /Tl, (1) , , (4
,,) Substituting this into equation (1,5), F'(,1/[) = Σt −j, t, /l□ u(
1) H(,x/x)1,... to -M″i″...(1,7) H obviously creates F'(nT) by holding F(m Tl) to the zeroth order. It represents the deformation of the characteristics in the case. From the idea of compensating for this, we consider the function F (mT 1) Mi□'', U' (mT1-1 T
s) a□00. (, -p). And F
(mTt). Next instead of holding F (mT engineering)
By holding 0-order, the original transmission characteristic with compensation for the deformation Hω) can be obtained. That is, (1,6) to (1,
8) is derived by using Eq. Considering the inverse word transformation of equation (1, 10), F' (nT) −H(nT) o7(mT,)
... is expressed as (1, 11). Here, 0 represents the second position between the two sides. This is simply F (m
This means that the value of T > ) is held in the register.

The sampling interval of the carrier signal is T.

The angular frequency of T is ω. The modulated carrier wave cannot be expressed unless the period is smaller than one period of the carrier wave.

To express this accurately, sideband waves generated by the carrier signal distributed around the sampling frequency mix into the band of the carrier signal. This can be avoided by increasing the sampling frequency, but
Apart from this, components due to higher harmonics generated by sampling the baseband signal are distributed around the carrier frequency, and these components mix into the baseband region. This is done by converting the baseband signal to 0 in the carrier signal processing section.
Next hold and made? (nT), and in order to avoid this contamination, Fo(nT)-G(nT)0
It is necessary to perform filtering of 7'(nT)...(1, 12). The cutoff frequency of G (n T) is ω. ′
It is usually about 1800H. FIG. 1A shows an arithmetic circuit that outputs a modulated carrier wave f (nT) at the output end.

, f (nT) is f (2LT)-Ao(!IT) oos ω, as shown in the right part of FIG. 1A. ' n
T-Bo(nT) sin a+. 'nT...(1
, j 3). Here, F, (nT) = A, (nT) + J Bo(n
To create the signal T), the processing of equations (1, 12) is performed.

This process is indicated by G, ,G in FIG. 1A, and G (nT) G 1 (nT) ”j G @ Cn
T). However, this form is a general form, and in practice it is convenient to write it as G * (nT) -Q. 1st
The box labeled H in Figure A indicates the holding effect expressed by the equation (1, N). The input signal of this block is the second term on the right side of equation (1, 11). To explain the processing steps up to H, U in equation (1, 8) is changed to U' (mT,) - P' (mT,) + JQ' (mT□
) ...-(1,14), and furthermore, F (m T l ) -A (m T l ) +
When j B (mT x ), U'll, the above equation P', and Q' are obtained by transforming υ using the (1,8) equation. U does not need to have an imaginary part in double-band transmission. However, it can be seen that in order to correct the deformation of the characteristics due to the hold processing, not only the real part but also the imaginary part is required, as shown in equation (1°15).

The ROM of FIG. 1A is a read-only memory that stores the cosine and sine distance 'Ikm. AI, A, in Figure 1A.

Bo and B are the (1g+s) acids 1st and 2nd of the first formula, and 1st and the second of the second formula, respectively. It performs the operation of the second term, and the variable of the function of this term is λ(m, t) I"" m71 ""' i T @
...(L 16), and this function is defined by a table using this as an argument. The contents of this table are prepared by recording the calculation results in a read-only memory or the like in advance based on the required spectrum of U and its correction formula (1.a). The argument for drawing the table is determined by the process represented by the plotter λ and its peripheral symbols in FIG. 1A. This process is λ (weight, t) -1-J G1-1. t) +T
, r λ ('+ i)-λ θt+ 1-1) -T
It is determined by @1・(1,17). &11 bt in the equation (1, 1!l) can be found from Table C in FIG. 1A. This table C is indexed by the number formed from the sequence of transmitted data bits that enter the modulation element. Vector L1-a + j b
If the number of discrete values that l can take is N, the transmitted data bit Y sequence is divided into log N bits, and the number created by the combination of the logical values of each bit in one division is 1. The difference is taken by the memory R□ of the first person figure, and a lookup table of C is performed using it as an argument. The contents of this table are set so that the demodulator is less likely to misidentify the discrete value of d1.

Figure 1B is a detailed view of the parts B, A□ in Figure 1A.
j' to 1'... is a shift register that stores the output of Table C; Also, the blocks P#, Q/ are P' (mTt) -Q' (誼T
, ) represents the operation of indexing the function table.

The sampling rate distribution for the baud signal, baseband signal, and carrier signal is 1/T, , 1/
TI and l/T, but since the baud signal will be mii'd by 2,4 KH2 determined from the modulation rate, the other sampling rays will be integers of 2-4 KHz. In order to spin out the band wave generated by the linear baseband summation of the carrier frequency into the baseband band, G(mT) is used as described above. Therefore, the problem is the carrier signal sampling frequency,
It is sufficient to search for conditions under which sideband waves distributed around the baseband signal sampling frequency can be avoided.

Sampling rate distributions that are considered appropriate for implementation are α) 2.4KH, 2.4KHM, and 9-6KH9 for the baud signal, baseband signal, and carrier signal, respectively.
-6KH,4KH,,4,8KH,,OJ:H9.6 and H2 are possible. In the condition α) (1, 15)
In the equation, m=-χ, and it is expressed by a convolution of F(kT,)-σ(kT,)O1, and σ(kT,) can be realized as a digital filter. However, in order to separate sideband waves distributed around the baseband signal sampling frequency from the baseband signal, the digital filter described above becomes close to an ideal filter. Furthermore, the above-mentioned sideband waves exist close to the baseband signal, which is a factor that makes it impossible to realize the condition α). In the case of 2), an idle region can be provided between the sideband wave and the required band of the baseband signal. As will be described later, it is possible to create a margin for setting a bettower Y channel with a band of about 100 t-t.

In addition, in the first person figure, (a), (1=), and (
0) have sampling intervals of T, TI, and T, respectively.
.

Indicates that the sample value processing unit is . Also, T
The input from the processing unit T1 to the block λ of the processing unit T1 is shown, which means that the contents of A are cleared every T. For λ (1, 1)
I mentioned that it is for formula calculation, but actually (
When calculating the equation 1, 1S), etc., the current time is set to -Q. To match this T
, it is sufficient to set λ to 0. In Figure 1B, %”
The shift register created by k# & -11..., ak-M is updated at an interval of T, which is a different interval from the other parts of FIG. In order to be able to process all the circuits shown in FIG. 1B with the same clock, it is necessary to insert a dummy in each stage of the shift register in FIG. 1B as shown in FIG. 1c. This is the case for the sampling rate distribution e]. In Fig. 1C, the part (c) is 2.4KH, and the part (b) is 4.8KH.

and sample each.

The modulated carrier wave output from the sample value operated modulator of dual detection is received by a demodulator through a line. If there are no frequency and phase fluctuations in the line, the received wave at the input of the demodulator is expressed as R'(tl-r, (
t) eos (alo' t) -rll(t) t
It has the form a in (#o' t). but,
In general, it does not take this form because there are fluctuations. To formulate the sample value operation formula for detection, it is necessary to define the received wave based on the standards of the receiving side. Therefore, the received wave is R(t)
−r, (t)cos ((11° to 1α, (t))−
r, (t) sin←. 1+α, (1))...(2,1
) becomes. This is ω. In order to treat this as a signal close to the baseband with a spectrum distributed around the center, first, -(t)-R(t)a j ("o t+θ(t))-
Create e(t)ej#(t), -(2,2). Here e (t) - e 0 (t) + J e , (t). .

0. ) −08°. □t), e, (t)-ai. . . ,
. , ))-(2,5). When performing the operation (2, 2), harmonics are generated. It is necessary to eliminate this and limit the spectrum to -2πW to 2πW. For this purpose, filtering with a unit response ξ(1) is performed as follows.

M (t)-e(t) *ξ(1) Here, if z(t)-x(t)+j y(t) +ξ(1)-da(t)+jζ(1), then ! (t)-17(t) O@0(t) 10ζ(t) Oe
, (t)y(・)−η(1)0・8(1)−η(1)0
・. ( becomes self°−゛(2, “).The purpose of detection is r
, (t), r, and (t), but for this purpose, θ(1) in equation (2,2) is replaced by α. It is necessary to approach (1). For this purpose, brightness control is required, which will be discussed later.

To calculate the operating equation for detecting the received wave, use α in equation (2, 1). (1) is an unmeasurable quantity, and R(t) is measured as ooeω. t, E+inω. Consider that t is produced by the demodulator. If eQ and es are expressed by the sample values generated by the Sansil value processing circuit, the following is obtained. On the demodulating side, there is a carrier signal part and a baud signal part, just like on the transmitting side, and it is unreasonable to process them all at the same sampling interval, so it is still necessary to consider the appropriate allocation of sampling rates. However, when using a multi-rate system on the demodulation side, the question is whether there is a distribution method that satisfies the conditions for avoiding this effect of performing a skip sampler. For this reason (2,4)
In - first η etc. η. and divided into η, ? Let's look for possible conditions when allocating 1/T to O and 1/T to η'. First, as an example, the first term on the right side of equation (2,4) is x'(t)-y+. (t)Os. (t)+v'(t)O
Divide as eo(t) −・−(2,6), and in the first term on the right side, set ・t = n T, x, (nT) = +7o(nT) Oe, (nT)
...-(2,7), *-Ki (K, i are integers), let U(nT) be a unit 5top function, and x
, (4T,)=U (nT s n-Ki)xl(nT
)...(2,8) skip signal x, (tT,)
think of. Here, the representation method (nT:n=Ki) is n
It means to take 1 which is an integer among the values divided by K. Applying the skip sampling theorem to this x, (IT□), the 2 transformation of xl (iT□) is 1 λ
Bo-1 XI (a)-; , J'-v-(pej2”/k)
・e, (p, 52y2/h.

becomes. Here, z m p . On the other hand, (2,7
) by taking two transformations of the equation xlo)-η. ω)・eoω) ...(2,10)
However, on the other hand, in each term of the (2,0 force side, instead of p, a term set to .j2πλ/ appears.By setting p = ejalT in these equations, The spectral distribution is perfect.In these spectral distributions, the λ−〇 component is the required wave, and in addition, λ+
Unnecessary waves of 0 are generated at intervals of l/ of the sampling frequency. Therefore, in order to distinguish between unnecessary waves around the sampling frequency of the baud signal and the required band of the baud signal, the required band of the pol signal must be equal to the Nyquist band of an ideal filter with a cutoff frequency half the baud rate. There must be. In order to satisfy this condition on the transmitting side, the sampling rate distribution method is 2.4.4.8.
In the case of 9.6 KH, it is necessary to make the baseband close to Nyquist band transmission. However, when allocating the sampling rate on the demodulation side, it can be said from the skip sampling theorem that there is no meaning in using the same allocation as the modulator, so 2.4.2.4.9.6KH,
It is necessary to do so. In this case, the part corresponding to the baseband on the modulation side, that is, the sampling of η' in equation (2, 6) is the same as the sampling of the baud signal, so the processing of η' is performed by the automatic etc. connected to the next stage. This will be done using a transpersal filter in the fixture. In this case, the input signal of the transpersal filter becomes the following equation, which represents equation (2, 4) using sample values.

As L−T, /T, x (kT,) −TJ (nT + n−Lk) (
('7゜(nT) 080(nT) )+(ζ.(nT
) Os, (nT)))y (k'l @) -u (
nT + n-Lk) ((η6 (rL”) Oea
(nT) )−(ζo (nT) Oe o bT)
) )...(2,11) Of course, in this signal, unnecessary waves are closely distributed in the required band of the baud signal. However, this unnecessary wave can be removed by the automatic equalizer connected next.

That is, as will be described later, the transparsal filter in automatic equalization processing is performed to provide Nyquist band transmission. This means that as long as there is a signal outside the band, an error in the detected signal x (kTl) + 6.(kT, ) will occur, and M
(hT,)-ri2(kTo) + ,,s (k'r,
) is automatically adjusted in the direction of decreasing the number of taps.

Figure 2A shows a processing circuit for processing equations (2, 11), and the signal x (
kT, ), y(kTl) can be obtained by referring to the output of register 9.10 in FIG. 2A every interval T. The section (0) in FIG. 2A is a sample value processing circuit with a sampler interval T. The section (&) is a sample value processing circuit with a sampler interval T, and the section 8 processes the conpolution index indicated by * in equation (2, 11) and its related display.

Reference numeral 7 denotes an input terminal of a demodulation circuit on the receiving side, and the analog signal of 7 is converted into a digital signal by 6. 1,2゜3.4.5
The circuit shown by is for processing equations (2, 5) and outputs s, (nT) for input and θ8(nT) for δ. The above shows that the sampling rate on the modulation and demodulation side is distributed by 2.
．． 4.4.8.9.6KH, and 2.4.2.4.
9.6 KHM, Nyquist band transmission is performed, and all digital sample value processing is performed, but a circuit that can be applied even if the Nyquist band transmission is not necessarily performed is shown in FIG. 2B.

In Figure 2B, 6 is the receiving side demodulation circuit input terminal and 1
．． The circuit shown in 2.3.4.5 processes equation (2,5). However, the part (1+) in FIG. 2B is a line-carved analog processing circuit, and l, ζ, etc. are those of equation (2, a). On the other hand, the section carrier signal sample value processing circuit (&) is a digital processing circuit.

Numeral 5 is an analog-pi-digital multiplier whose input and output are analog-pi-digital multipliers. Figure 2B (0) is
In the digital sample value processing circuit with the sampler interval T, the analog section part of (,) is converted into a digital value by the analog-to-digital converter shown by 8.9, and the automatic equalization process becomes (c). is input.

The operating formula for automatic equalization can be determined by setting t-kT in the formula described in the above-mentioned application WAIIIll. However, if this is calculated by a processing circuit, an equation with −Q will be calculated. First, in the case of a transversal filter that enters in series with the transmission path, if X (hT,) and Y (hT,) are the values of the output signal of the transversal filter, then X (kT,) −J (oos # (kT,) (7
, x ((k-1) T,)-δ1a00 ((k-1) T,) ) -gin# QcTa) (y□y ((k-1) T
,)+δ,! ((k-1) T,)))Y (kT,
)−Σ (a o e# QcT,) (rly ((
k-1) T,) +J,
Tl) -a,y (Oe-1) T,)))...(
2,12) XIF in this formula is (2,4) or (2,10
It is. Therefore, the automatic equalization processing circuit becomes as shown in FIG. 2C, but the input of this circuit becomes the output as shown in FIG. 2A or 2B. It is necessary to input -, etc. to the processing circuit of FIG. 2C. This variable is also shown in equation (L12). These are discussed in the next section. In Fig. 2C, T is the signal register of the tap of the transversal filter; r@w'6irzsδl
#"" 1141-δto1 is a tap coefficient. The formula for determining the tap coefficient is determined from the signal error of the detected signal.

In this case, the detected signal has a value calculated by equation (2, 16),
Furthermore, x' has been corrected by parallel automatic fixtures as described below.
, y'.

It can be determined by That is, γ1(k+1)−γ1 rectangle αa □(kT,) ” ((
k') Ts)+αε, QcT,)y (0c-1)
Tl) δ1(k+1)−δ1(k＞+a a□QcT,) y
(Oc-1) T,) +a g, (kT, 1)X
This is a differential operation formula: (伽−1)T, ) ...(2, 14). Here, 1 (2, 15). 6X and 81 are predicted values of the signal error equation (2, 1g). The equations (2, 1s) to (2, 16) are the adjustment equations for the transversal filter, and the processing circuit is
Shown in Figure D. In FIG. 2D, terminal r. δ. , γ, δ,
.

, . . + 1l-16) The register T and the adder circuit connected to I-1 represent the processing of the differential operation equation (2, 14). Furthermore, the shift register consisting of the register T connected from the terminal x (kT,) ry ocT, ) in FIG. 2D is a re-presentation of the one shown in FIG. 2C. In the portion shown by the curved block in FIG. 2D, 3, 4, and 5°6 are input terminals, and each term on the right side of equation (2, 15) is input. The X mark shown at the intersection of the vertical line extending from these terminals and the horizontal line is used to multiply the (2, 15) force side, and the signals of the vertical line input to the two X marks on one horizontal line are multiplied. This means that the result appears on the horizontal line. Also, two perpendicular lines descending from the output terminal 1.2 of the L block represent the left side of the (2,1s) equation, and the signals on the horizontal line input to the + marks on each line are added. Addition input with a minus sign (-) indicates that subtraction is to be performed. Block M in FIG. 2C uses a method similar to the processing method for block L described above, and calculates a term with a large force side (2, 12).

In addition, when writing a sample value operation formula like the one above,
Although the sampling time t - kT, etc. is substituted into a variable of a continuous equation, there is a phase shift in the sampling clock, so t - kT, +△.

and t = n T+Δ/L (L-T, /T
) is correct. However, when creating a processing circuit, Δ has no effect, so I will omit it here. However, since it is necessary to accurately control the phase of the sampling clock of the baud signal, the variables omitted in the section dealing with this control function will be restored.

Due to unitization, the phase of the sampling quadruple of the carrier signal also changes with the above control, but this does not affect the characteristics.

In the modulator, every time a fixed number of transmission data bits are collected, 1114 (88 dk) are generated. dk is a complex number and has a given finite number of discrete values. These discrete values are scattered on the complex plane. Demodulator The detected signal at is t −k
The sampling value at T is the restored value of the modulated signal, and dk is determined from this value.

The sampling value at t - kT of the detection signal is
(hT,) Y' (kT,) t, 1. , consider a complex number whose real part and imaginary part are cholera. That is,
Z'(kT,) = X'(kT,) + jY'(
kT, ). Z′ (kT,) is located around each discrete value of dk but does not coincide with the discrete value of dk due to distortion. However, if Z' (kT,) located near the point corresponding to each discrete value of dk is obtained, the modulation signal that sent that Z' (kT,) will be Z' (kT,
) is determined to be the 1111 loss value of dk. Therefore, there is a judgment area centered on each discrete value of dk on the complex plane of Z' (kT,), and the discrete value at the center of the judgment area containing Z' (kT,) is determined as a modulated signal. Output.

In the modulation/demodulation unit, this judgment area is circuitized as a table, and the input of this table is Z' (hT,), that is, X
By inputting ', Y', the above discrete values are output. &□, bk in equation (2, tg) are obtained as the output of this table. X'(kT,).

The detected signal Y' (kT,) is obtained by further correcting X (kT,) and Y (hT,) obtained by processing equations (2, 12). Equation (2, 12) is a transversal filter that enters the transmission line in series, and correction of its output is performed by a transversal filter that enters the transmission line in parallel. Appropriate function allocation is performed for these two types of automatic equalization. That is, the second term on the right-hand side is
-t)! The determined modulation code is input to the transversal filter as shown in the signal flow graph shown in FIG. 2R. The number of threads of this transversal filter for judgment feedback is g/Oc+1)-
g7(”)+α('z (1cTg)' to 7'YO
”J bk-4ht (k10-h, (k)-α (a
X QcT,)bk, -gY QcT,)bk,)
・−(2,19) ε, 8Y is given by equation (2, 14). (2,18) , (2,1
A signal graph for performing the process of 9) is shown in FIG. 2F.

In FIG. 2E, the block T is a register that is updated every sampling interval T, and the shift register created by these is a of each term on the right side of equation (2, 18).
, and b are recorded. This carves a transversal filter and its tap coefficient g. 11g l gl
A circuit for obtaining hll "" gM-1hMl is shown in FIG. 2F. The block TA in FIG. 2E is the detected signal x' (
kT, ), Y' (kT,) are input, and the modulation signal &1. This is a table recording determination areas for restoring bk. X
' (kT@) + Y' (kT *) is the second
X (kT,), Y (kr,
) is corrected by the output of the above transversal filter to obtain x'(kT,) and Y'(kT,).

Figure 2F shows g, which is the input for Figure 2E. h@+Jh□,
. . gM, -1hM-1 are output to the terminals represented by these symbols, and the predicted value of the signal error of the output signal of the series automatic equalizer is calculated. The lower part of Figure 2F does the former, and the upper part does the latter. In the former, the block ``]'' is a register that is updated every sampling, and the shift register constructed by this is a re-presentation of the one shown in FIG. 2E. Further, the block N used in each stage of the shift register is shown in Fig. 2G, and the T block connected to the output terminal of this block is
, the same symbology as in the curved portion of FIG. 2D is used, except for the integrator circuit with registers. Then the latter is (
2, 16). The reason why the above circuit is shaped like this is explained in the above-mentioned specification of the prior application.

Note that when allocating functions to a series automatic equalizer and a parallel automatic equalizer, the parallel automatic equalizer is highly dependent on the judgment result, so it mainly depends on the serial automatic equalizer,
Regarding the parallel type, there may be a method in which the frequency distribution of the transmission characteristic is made to have a role of correcting distortion components that are subject to large delays at both ends of the transmission band. In this case, the determination result in the i2F diagram is &). In the circuit that creates the coefficients of the transversal filter that feeds back r bk, the coefficients of taps with a small delay are not used.

3. To complete the comprehensive operation of the sample value operation type variable prick with synchronous control, the synchronous control must be improved. On the demodulation side, the detected signal %X' (k
T, ), Y' (kT,) Input To and TA in FIG. 2E, which is a cholera code determination table, to obtain &□, bk.

In order to perform these calculations, θ(kT,) must be determined as shown in Figures 2D and 2C.
This is still undecided. In addition, as mentioned in the previous section, when the operational equation on the demodulating side is in sample value form, the sampling time t = kT, etc. is substituted into the variable of the continuous equation. It is obtained from the system and has the form t='I', +△, where △ changes due to the synchronization difference. On the demodulation side, it is necessary to bring Δ to the appropriate position of the modulation element by automatic control.

First, θ(kT,) is controlled by α in equation (2, 1). (1)
Although it would be good to get close to , ff,(t) is an immeasurable quantity, so another method is needed. Regarding this, as shown in the specification of the prior application, the deviation from the state in which the detection signal can be detected in the optimum state is proportional to. This formula can be calculated using the determination results ak and bk. The state of xo' (kT,) -Q is θ groan, ) - α. QcT, ) cannot necessarily be said to be true. (
As can be seen from equation 3,1), xo(kT,) becomes 0 when both detected signals become equal. Therefore 7,
X.

It would be better to perform control so that (kT,) becomes 0. First,
This signal is input to the filter processing x(k-ν)T, )...(g, 2), and the high frequency components included in Xo(kT2) are removed to stabilize the control. Regarding this filter processing, it is necessary to select parameters such that the following fluctuations are not passed. However, this process introduces a delay of θ(kT) into the control loop.If this delay is not compensated, control will not be performed normally.For this reason, x
As a prediction of (kT,), x, (kT,) = 2 (2X (kT,) −x(
k-i) T, )-(2x, (k-t) T,)-
Consider x□(k-21) T, )...(3,5). Here, 1 is the number of skips in the predicted amount, and indicates that the predicted value is one element ahead. It is considered that the range in which such prediction is possible is that the operating time constant of the filter cylinder of equation (5, 2) is less than ten times the modulation element length T. Under these conditions, in order to make appropriate predictions, we consider a linear combination of the predicted amounts with different numbers of skips.
The coupling coefficient is optimized by setting this as θ(k'll',).

θ (kT,) = -Σ &1”t (kTm) ...C
3, 4) 1 effect 1 al (k + 1) −&1. (k)-ORxl(
k Ts ) If it is not necessary to take a large number of discrete values of the modulation vector 1llk, a low-pass filter may not be necessary. In this case, the high frequency components of the control loop are removed by a multiple lag filter. In this case, there is a control delay of one modulation element due to the sampling process to feed back the control signal, which is θ(kT,) −2(2z QcT,)−x(k−1)
T,)(2# (k-1) T,)-〇(k-2)
']'', )...(3,5) Compensation is performed by the prediction process. This human power x (kTs) is x OcT s)
! Ia s x t (i T s) + o *β
x(k-1)T, )Xl (IcTI) -〇sKB
(iT,) + amβX1(k-1)T,)x,
←T,) −〇mXo'(kTs) + 6sβx,
(kl) Tl)...(5, 6) This is obtained by the processing of a multiple lag filter. (g, 4), θ (kT,) determined by the formula (!1.5) can be calculated as oos # (kT,), sinθ by inputting it into a trigonometric function table prepared in advance.
(kT,) is obtained and inputted into the circuits shown in FIGS. 2C and 2D.

FIG. 3A is an overall circuit diagram when a low-pass filter is used, and the blocks X□, . The purpose is to calculate the second equation, and its input x' (kT s) is (
It can be found by processing equations 3, 1) and (s, 2). This is calculated by the block LP and block TII in FIG. 3A and their peripheral circuits. X'(h'r,), which is the input of the circuit of FIG. 3A,
Y'(k'r,), ak, bk, etc. are the second E
Obtained from the circuit shown in figure. The output of the circuit of Figure 3A is θ(
kT, ) can be obtained by inputting it into the trigonometric function table shown by clicking TC in the figure. The contents of the tables TB and TC may be calculated in advance. The click LP in Figure 3A indicates the processing of the digital filter of equation (5, 2), and its internal circuit is shown in Figure 3B (b
). In addition, the blocks X... The low-pass filter in Figure 3B (b) is a general representation, and by optimization it can be made into a more economical digital filter.The need to use a low-pass filter in the automatic phase control loop The processing circuit when a multi-lag filter is used without a multi-lag filter is shown in Figure 3C.
is a multi-lag filter circuit, and its output is inputted into a trigonometric function table TC by correcting the processing delay in the l-step prediction circuit (b), and its output is given cos θ
A signal of (kT,)1sinθ(kr,) is generated. Also, when compensating for the delay of the low-pass filter in the control loop, (3
, 3) The feedback term on the right side of the prediction equation is used as (
It can be considered that it is used when adaptive adjustment such as equation 5, 4) is not performed, and when adaptive adjustment is performed, the above feedback term is eliminated and xt (kT, ) - zxQcT, ) -x(c-1)T,
)...-(s, y), it is considered appropriate to use equation (L4).

In this case, the process shown in FIG. 3D can be used instead of the part N in FIG. 3A, making the process simpler than the process shown in FIG. 3C. @
In the 3D diagram, 1, 2. ...T with the number L added on
, are registers that are updated at sampling intervals T, and these blocks constitute a shift register. Vertical lines drawn from each stage of the shift register and! ,,X,
, ... r Xb, the cross point with the horizontal line means to output to.

In the description of sections 1 to 3, the sampling time for each modulation element was set as t −kT, but
If there is a timing shift in the ivy, it is necessary to set it to t-kT, 10. In automatic phase control, the detected carrier wave ω. The phase shift θQc7ρ of nT was determined from the detection signal (
3.1) It was mentioned that it can be controlled by equation. Therefore,
Detected carrier wave ω when not Δ−0. Correction of (nT+Δ/L) is also possible using the same operation formula. It is also possible to adjust for timing deviations using a method similar to this. For this purpose, in addition to a timing processing circuit based on the detected signal, it is necessary to configure a master clock oscillation circuit as shown in FIG. 3E. In FIG. 3E, D E M is a demodulation circuit that processes the timing processing circuits shown in FIGS. 2A to 2F, FIGS. 3A to 3C, and the above timing processing circuits.
is a click generation circuit that supplies sampling clicks to the above DEM. Two of the output lines of CL have a clock interval of T.

The double line l is a multiphase clock with a clock interval of T. The DEM also produces the output of the timing processing circuit described below, which is available on output line 3. This is proportional to the clock deviation Δ.

The VCO in the figure is a voltage controlled oscillator, and its output is 11114
A periodic wave having a frequency that is an integral multiple of the above clock is obtained, and CL is driven by this. The input 3 of the CO is a signal proportional to the clock deviation Δ, and as long as this signal is present, the CO shifts the oscillation frequency, and this signal maintains the oscillation frequency in a state close to O. When performing control to change the oscillation frequency, the four-way deviation is △(k-H) - Δ(k)-oz (kTffi) m
It will be controlled according to the formula H6 (3, s). Here, Z(kT,) is the DEM output 3 in FIG. 3E and is an analog signal. This analog signal is more than t'll! This is the result of digitally processing the l adjustment equation and converting the output to zero.

Z (kT,)-glX'(k-1) T,) 10g〆(
k'r,) + g', Y'(c-1) T,) + g
', Y' (kT B) ... (5,9)g 1=1
72' to -1t gs-1/2ak, g', -'1
/2bk, g', -b,.

/2ゎ2...(3,10) Figure 3F is a circuit that processes equations (L9) and (L10), and TD, TD calculates equations (5, 10) in advance and calculates the contents. This is a table with the following settings.

Timing information Z (kT,) is obtained as the output of the circuit shown in Figure 3F, which is DA converted and sent to the third
It is obtained as one of the outputs of the DEM in Figure E, and is applied to the frequency control terminal of CO, which is the main clock oscillator. This method is possible when the ■CO is the main oscillator for the click, and if the crotch requires input from the outside rather than from the ■CO in Figure 3E, the above method cannot be used. Can not. In this case, the main clock
% It is necessary to automatically adjust the delay of the transmission path instead of 4M.

Even in this case, since the output Z (kT,) in FIG. 3F is 0, there is no need to change FIG. 3F.

To automatically adjust the delay of the transmission path, a transversal filter used for automatic fixtures can be used. The automatic equalization operation is based on γ1 in equation (2, 12)
．． δ□ is adjusted using equation (2, 14), but in order to perform clock timing using this transversal filter, the adjustment operation equation (2° 14) needs to be modified. The transversal filter is adjusted in the direction of reducing the signal error of the detection signal (2, 17), but if the timing is also adjusted, E(kT,) = ε, s QcT,) 10 grams
(kT,) 10z'' (kT,) ・−(3,11).Here, ε-axis is given by the equation (2,1g).

In this case, Z (kT,) is (3,9)
Use the formula. When adjusting using equation (3, 12), the error of the detected signal, that is, the first . The tap coefficient adjustment term based on the second term is the second term on the right side of equation (2,14).
This is the same as the third term, with a term for timing adjustment added to it. In order to calculate this term, we need to calculate 1・(g, 1g). In this formula, for ax'/aγ1 etc., from formulas (2, 12) and (2, 17), aX'(hr,) / 811w o o eθQcT
,) x (k-1) T,) -sinθ(kT,)
y(k i)Tg) ax'(kTs) /aJ □--co s tl
(kT s) y (k-1) T s) -s 1n
II (kT s) x (ki) T s ) aY′(kT”) / aγi= o s# Qc
T,) y(k-1) T,) + s 1n19 (
kT,)x (k-1) T*) ay'(hT,)/aδ,7 o 611θ(kT,)
X(k-1) T,)-sinθQcT,)y(k-
1) T,) Gamaru. Calculation can be performed using this formula and the one obtained by substituting -1 in place of k in this formula. Now, A(n,k)=g
, -nooe#(IC-n)T,) 10g'2-nsi
nθ(k-n) T, )B (n, k) mg2. i
in#(k−n) T, )−g′! , oosθ(k−n
) Ts), then B (0*h) y(k-1) T, )am” (
kTi+)-2゜(kTs)(El (1*k)x(
k 11) TJ +A (b k)aδi y(k-
1-1)T,)+B(0,k)X(k-1)T,)+A
(Oe h) y(k-t) 'r, )...(5
, 14). The term for timing adjustment that is added to the side adjustment term in the operation equation (2, 14) for adjusting the tap coefficient of the transversal filter is proportional to equation (5, 14), and this term is The processing circuit is as shown in FIG. 3G, and its output is the output terminal roδ in FIG. 2D. ,...,
are added to γ8-4δN-1, respectively.

In Fig. 3G, the portions above the dashed-dotted line AB are commonly used for transversal filter taps, and the terminals 1, 2, and 3.4 have terminals (3, 14), respectively.
Formula A (or h) + B (or k) + A
(1tk) + B (1r k) is output. AB
The lower part calculates each term on the (114) force side.

C□ is the first . D□ outputs the calculation result of the second equation of equations (5, 14). This part is '-011
+..., calculated for each tap according to N-1. The overall flow of the above processing is shown in Figure 3H.

The shift F register consisting of the register T in this figure is a re-presentation of the transversal filter in FIG. 2C, and A is the part above AB in FIG. 3G, and is provided for each tap.

The internal circuit of the V-shaped vine is shown below the line AB in FIG. 3G. Also, aovlI (
The terminals kr, ) and sin # (kT,) are connected to the terminals with the same name in FIG. 3A or 3C.

gl * gl'+ gl + glZ! '(kT
The terminal named s) is connected from the terminal with the same name in FIG. 3F.

In modulation and demodulation systems that transmit modulation vectors that take a finite number of discrete values, it is necessary to make a function on the reception and demodulation side that can be determined from the detected signal to enable highly efficient transmission. It is necessary to perform optimization using the modulation vector, as described in Sections 2 and 3.

In order for this optimization operation to be performed normally, the above determination must be correct. However, in order for this determination to be made correctly, there is a kind of dilemma in that various optimization operations must be normal. In actual device implementation, when a carrier disconnection occurs on the demodulation side using a backward channel, an OFF signal is sent to the modulation side, and when the disconnection is recovered, an ON signal is sent and a start operation is started. Then, a start sequence is specified for transmission and reception. The optimization function depending on the judgment is shown in Figure 2C~
These include automatic equalization shown in FIG. 2F, automatic phase control shown in FIGS. 3A to 3D, and automatic timing control shown in □ and FIGS. 3E to 3H. Assuming that the judgment is incorrect, each of these functions will scan for abnormal conditions. This scanning will continue indefinitely unless a normal condition is found. If the champion performs random scanning at the same time,
It takes time to find normalcy. Therefore, first of all,
It is necessary to stop the automatic equalization function and restore the automatic phase control and automatic tying control to normal operation. Now, it is assumed that the permissible value for the distortion of the transmission path is about the two-phase or four-phase phase modulation system that does not perform automatic equalization. in this case,
Since a sufficient application area should be obtained without performing automatic equalization, first, under these conditions, only the automatic phase control and automatic timing control functions are brought to normal operation.

If the timing shift and phase shift are larger than a certain value, there is a range of shift where the sign cannot be determined correctly. If there is no distortion in the transmission line, if the deviation range is 2-phase or 4-phase, O
It becomes close to. Become more than 8-phase, you won't end up like this. Therefore, in the case of two-phase and four-phase, no matter what state the operation is started in, it can be brought to the center of control without scanning for abnormal states. If code amount interference occurs due to distortion in the transmission path, a range in which code determination is not performed correctly will occur, making it difficult to return to a normal state. On the contrary, the distortion of the transmission line that can be easily brought to a normal control state in two-phase and four-phase can be set as the allowable distortion. This defines the application area for 2-phase and 4-phase without automatic equalization.

Therefore, in the start sequence, two-phase or four-phase transmission is performed, the first phase is a state where automatic equalization is stopped, the automatic equalization is turned on in the second phase, and the modulation state is increased in the third phase. By doing so, it becomes possible to transmit information at eight times or four times the two-phase and four-times higher information rate, depending on the application area of each phase modulation method. The first phase in the start sequence,
It is necessary that the evening timing of the second phase is almost the same between the modulation units 11Re1. This is made possible by signal transmission using a backward channel, as described above.

Next, we will clarify the state relationships on the modulation and demodulation sides when establishing operation using a backward channel.

FIG. 4A is a state transition diagram of the start sequence on the demodulation side. The number of states is five, and they are distinguished by three bits as shown in the register S in FIG. 4B. 111,
110, 101, and 100°011 indicate carrier disconnection, the first phase, second phase, third phase of the start sequence, and communication status, respectively. On the other hand, the events that cause the transition between these states are carrier OFF, ON, first
This is a signal indicating that the output of the crotter counter that determines the time in phase 3 has finished counting a predetermined number of counts.

A carrier disconnection state may be artificially created on the modulation side in order to start communication, or it may also occur due to line failure. When the carrier is turned on, the state changes from 111 to 110, and in order to receive in 4-phase form, TA in Fig. 2E and TB in Fig. 3A
, and T D and T D in FIG. 3F. At the same time, time is monitored by a counter constituted by a register C shown in FIG. 4B, and by obtaining an ON signal indicating that a predetermined time has elapsed, the state changes from 110 to 101 and automatic equalization is started. At step 110, among the coefficients of the transversal filter for automatic equalization, 1 is input only to the appropriately selected coefficient γ1 among the output T of the second DED, and 0 is input to the others.

δ1 is all O. At 101, the addressing change of each of the above tables continues. When the counter output turns ON, the state changes to 100, the addressing change of each table is restored, and when the counter output turns ON again, the communication state Oll is entered. FIG. 4B shows a circuit implementing the above-mentioned control. The processing of this circuit is performed for each modulation element. C in Figure 4B is a register, one for each modulation element.
Time is measured by accumulating. K is a predetermined value and is subtracted by C. This result is determined by the table T& whether the result is positive or negative, and ON,
Whether or not the count has exceeded a certain value is displayed on each output line indicated by OFF.

The contents of C are reset by a table output of 1゛5. The reset signal, ie 0 is gated by the table Tb, is input to C. The gate signal applied to Tb is applied when the register S in FIG. 4B is at 111 and 011. As a result, C is reset in this state. Counting is performed in the first to third phases, and at the same time as entering phase 110, that is, the first phase, the reset of C is removed and counting is started. The same goes for states 101 and 100, but when the count value of C exceeds K, it is detected by the matrix M and a reset signal is sent to C. The diode matrix Mo detects the state of the register S, and the diode matrix Mo detects the state that the register S should take next. These are defined by the state diagram of FIG. 4A. This transition is carried out by the connection DR. The 1 input in FIG. 4B is produced by the automatic gain adjustment circuit described below and indicates whether a modulated signal is being received. Further, the output signal 2.3 is a signal for changing the table address and the automatic equalization transversal filter coefficient as described above. In addition, in FIG. 4B, T is set so that the output is turned ON when the set value of C is greater than or equal to K.

The contents are set, but when S is 110, 101, or 100, C is reset by turning T and output ON. On the other hand, due to this ON signal, 110 → 101
, 101→100. Alternatively, a transition from 100 to 011 must occur. To allow sufficient time for the effects of being turned ON to take effect, reset C at the final step of the processing of FIG. 4B in any modulation element. For this purpose, it is necessary to temporarily record the reset signal in the processing work memory. Fourth
Figure B shows double-line processing and single-line processing; double-line processing is signal processing in byte units, whereas single-line processing is logical processing in 1-bit units.

Further, in the first and second phases, the contents of each block T in the ff12F diagram are set to 0, and parallel equalization is stopped.

Next, a start sequence on the modulation side for the demodulation side described above is determined.

The start sequence on the modulation side is determined corresponding to the start sequence on the demodulation side, and the state diagram is as shown in FIG. 4C. That is, it enters the first phase state due to the backward signal signal returned from the demodulation side through the backward channel. When the backward signal is turned ON, it means that the demodulation side is already in a 2-phase or 4-phase reception state. On the modulation side, the first phase also performs two-phase or four-phase modulation transmission. As shown in C of FIG. 4D and its attached circuit, the same number of counts as on the demodulation side is performed. Count the same number of counts as on the demodulation side, from the 1st phase to the 2nd phase,
A change is made from the phase to the fifth phase and from the third phase to the communication state. There is no need to distinguish between the first phase and the second phase in terms of operation, but
It is divided into two parts for time adjustment with the demodulation side.

1. In the second phase, the data signal is prohibited, only the data code scrambler at the modulator input is operated, and the address of the table that creates the modulation code shown in C in Figure 1A is changed,
Two additional hit numbers are output to each of the two output terminals. In the third phase, the demodulation side operates the automatic equalizer, and since this is the time when demodulation is ready in multiple states, the address C in Figure 1A that was used up to the second phase is changed. Cancel the change and perform multi-state modulation while keeping the data signal inhibited.

The communication state is entered by C in FIG. 4D counting out. Of course, the demodulating side has already entered the normal state.The reason why the demodulating side causes the state transition first is that there is a delay in transmitting the 0N-OFF signal using the packed word channel, and there is also a delay in transmitting the 0N-OFF signal on the data channel. This takes into account the addition of transmission delay. This delay is desirable for establishing operation. Figure 4D is a processing circuit diagram created according to the state transition diagram of Figure 4C.
It performs almost the same function as the start sequence circuit on the demodulation side shown in the figure. The symbols in FIG. 4D that are the same as the symbols in FIG. 4B perform the same role or function. The backward signal, which is the input signal in FIG. 4D, is 0N-O
It is an FF type circuit, and the circuit near the backward signal terminal in Figure 4D detects the rising edge of the above signal.
, is used to calculate the difference from the previous basket by 1 change element, and the difference signal is sliced using a table called To to convert it to 0N-OFF. It is set to be ON only during the rise time of the backward signal, and to be OFF at other times. In addition, the table address change terminal in Fig. 4D is the first
It is added to the input side of table C in figure A, and moves to change the address.

Further, the data input inhibit terminal inhibits the terminal to which a data signal is input, and operates only the data code scrambler.

Carrier 0N-OFF (No. 1 will develop the start sequence as described in the 4th person diagram,
Detection of this signal is closely related to the automatic gain adjustment function. The automatic gain adjustment function, ie, AGC, amplifies the signal input to the demodulation circuit, and the amplification factor of the AGC signal is automatically adjusted so that the level of the detected signal becomes an appropriate value. The relationship between the processing circuit related to AGC and the analog amplifier circuit is as follows. First, if the AGCf) signal gain is αk), then the adjustment operation formula for αk) is as follows. Here B (kT,) −sX” (kT,) +g,’ (
kT, ) −...(4,2), and...(4,5). The block indicated by the dashed dotted line AGC in Fig. 4E is
The received modulated wave applied to the terminal IN is converted into a digital quantity by an analog-to-digital converter called A/D. The conversion characteristics of the Human/D are designed such that the logarithm of the corresponding output digital value is proportional to the input analog value. The A/DI) fi power addresses a read-only memory called ROM. In this ROM, the relationship between the address value and the output value read out to the output bus is such that the logarithm of the address value and the output value are directly proportional.
The contents of the record are stipulated. This is a known method for preventing the quantization noise of the A/D output from increasing in a small input analog value signal.

The processing bits B used in the AGC block are 3 to 4 bits more than the parts other than AGC'.

■ in this block is RO depending on how TI comes out.
The M output value is increased to a level suitable for this processing block and the demodulation operation type processing connected thereafter, and the OU
It is output to the T terminal. In the processing block after the OUT terminal, the lower 3 to 4 bits of the output logic value of block a are removed to perform operational processing.

Digital signal processing is performed by a processing unit F consisting of logic devices, and its input/output signals must be converted from analog to digital or digital to analog. In particular, even when the input signal is received at a low level, it is necessary to use the method described with respect to AGC in FIG. 4E above to avoid quantization noise.

Each of the processing circuits explained in sections 1 to 4 is executed by digital signal processing, and furthermore,
Filter processing to separate the backward channel and data channel at the transmitting/receiving interface, and balancing to eliminate crosstalk between transmitting and receiving due to unbalance that occurs when converting a 2-wire line to a 4-wire system. Functions are similarly realized through digital signal processing. The connections between these processing blocks and the peripheral circuits necessary for digital signal processing are shown in FIG. 4F.

First, on the modulation side, (a) transmission code circuit: denoted by S in FIG. 4F. This is the circuit that creates 1 in FIG. 1A, and receives the transmission code from the data terminal device from the SD terminal in FIG. 4F.

Inside the S, the □ signal is inhibited by the ``data input inhibit'' signal shown in FIG. 4D during scrambling of the sD code.

(b) Transmission wave sending circuit: Digital signal processing to create the transmission wave is performed by the MOD shown in Figure 4F, and its output signal is input to the SFD that performs transmission wave processing for combination with the backward signal. . BL is LIN, as described below.
This is a circuit that converts a 2-wire line E from 2 wires to 4 wires, and this circuit performs balancing processing to compensate for the lack of return loss between transmitting and receiving caused by unbalance in the 2 → feed block. 4 of the SFD output signal BL
Input from one terminal and output from two terminals. This signal is converted into an analysis signal and sent to LINB via 2←4.

(/J Backward circuit low reception data channel and RFD
, and RFB by a frequency division method through digital signal processing of filters.

RFB is also the FM received from the backward channel.
Signal detection is also performed using digital signal processing,
Add the output to the MOD's 2nd terminal.

Next, on the demodulation side, (a) Modulated wave receiving circuit: The process of detecting a detection signal from the received modulated wave and reproducing the modulation code is performed in the DBM shown in FIG. 4F. The input signal is input to the AGC from a two-wire line called LINE together with the local station transmission signal suppressed by 2→4. The inside of the AGC is as shown in the AGC in Fig. 4E, and the terminals input from the 3 terminals of the DEM to the AGC in Fig. 4F are as follows.

The output obtained by performing processing other than AGC in the DEM in FIG. 4E is added. Of the AGC processing bits, the low-order 3 to 4 bits are added to the BL 1 terminal, the local modulation signal leaked from the transmitting side is removed in the BL, and the signal is filtered by data channel filtering called RFD. , the data modulated wave is input to the DEM separately from the backward channel.

(→Backward circuit: Constructed by the processing of the FMS block shown in Fig. 4F. The FMS performs digital signal processing that performs FM modulation to create a backward signal using the carrier detection signal in the processing of Fig. 4B in the DEM. The signal is added to the SFD output through the digital signal processing of the filter in Fht s, and B
It is added to the transmission terminal 4 of L.

(c) Reception code circuit: The circuit indicated by R in Fig. 4F takes the difference between PLkHbk in Fig. 2F and reproduces the transmission code. This part needs to be connected to the automatic equalization change terminal in FIG. 4B, as shown by the line 1 in FIG. 4F. This is to inhibit data reception and output before operation is established in the start sequence.

The BL shown in FIG. 4F is used as a circuit for maintaining a sufficient return loss between transmission and reception, and the operational formula for the function of this part is as follows.

FIG. 4G (a) is a diagram showing the principle of this signal processing, in which a transmission signal xj applied to a converter 2-4 is applied to a transversal filter TR8. T, 3 is 2 → 40
The taps of the transversal filter are adjusted so that at the output of the circuit, the component that leaks from Xj is equal to the value that is included. This ∎ well-ordered algorithm is created as follows. Let the transmission signal be Xj and the tap coefficient of TR3 in Fig. 4q (a) be C! 1(j), the output of TR8 is X −Σ C(j) −xj, ---(4, 4
) j n = 1 ”. Here, the algorithm creates a correlation function such as ) = (y − x') x Considering that, 7.1-1j' in Figure 4G (&) does not include the component of Xj. Here, Xj (τ) is a function of xj delayed by τ seconds. In this case, When minimizing 63 while keeping τ identified, it is necessary to pay attention to the following points.

That is, when removing the component proportional to
becomes 0. At this time, Litanris does not get any better. To eliminate this concern, it is necessary to consider a function that integrates - within a range of τ that is larger than the delay that may occur in the transversal filter. That is, consider an algorithm that minimizes . First of all, it becomes. Here, since it becomes ax'/ac casting de Xj-yu, it becomes. Here, α−fXj(τtdτ 10 can be considered a constant, and after all, τ does not affect the algorithm. Therefore, the adjustment operation formula for the tap coefficient is 0□(j+t)−a, ( j)-1(ya-Xj')
Xj-yu...(4,7). Figure 4G (b
) is the internal structure of the pull-outer BL in Figure 4F and the AGC.
, D/It shows the connection between people. Figure 4G (b)
M is a memory shared by the terminals 1,2°3.4 and the processing units TR8 and TAP, and is used to exchange information bytes between them. This is done by allocating slots for accessing in a time-sharing manner.

TR5 processes the equation (4, 4), and TAP.

Calculate equation (4, 7). ■The eastern line is 籟θ)(+-1
~N) is transferred.

Note that the details of the peripheral configuration of the common memory M in FIG. 4G(b) are the same as in the case of DEM and MOD, which will be described later, and will not be described in detail here.

Next, the method of constructing the RFD and SFD shown in FIG. 4F uses a known digital filter method, and thereby
Configure a transmission channel for data signals from 00 to 3000 Hz. FM8 and RFB for backward channel are
Performs filtering and processing of low-speed FM modulation/demodulation method. Of these, 300 to 600 are used for filtering.
This constitutes a Hz backward transmission channel. Among these, the operation formula of the FM modulation and demodulation method is that on the modulation side, that is, FMS, the transmitted modulated wave is sampled value operation formula fo "
) -QQ"φ0"')) φ(nT')-φ(n-1) T') 10m'no
Create by τ′+μ′−′(]!LT′)...(4,8). Here, s'(nT') represents the signal on the input line from the DEM to the FMS in FIG. 4F.

The sampling interval of this formula is C4-7) P <c J
It becomes the same as that of T, and then it becomes an integer fraction of T. town.

is the carrier frequency of the packed word channel.

It is appropriate that the operating formula on the demodulation side be a VCO type, and the detection signal 5 (nl') is generated using the following sample value operating equation.

The received wave, that is, the output wave of RFB filtering is /(
nT'), it becomes. (4,11) l Processing formula (4,9)
When expressed in a graph, it looks like Figure 4H (→, (b)).

The device circuit configurations of the RFD, SFD, FMS, and RFB in Figure 4F are the same as those in Figure 4Q (b), but the configuration method for these is the same as in the case of DEM and MOD described later. Therefore, it is omitted.

CL shown in FIG. 4F is supplied with a clock from a voltage controlled oscillator indicated by CO in the same figure, thereby supplying clocks for digital signal processing and logic processing to other pulls. It is necessary to establish timetables for each of these four tasks. There are quite a number of these timetables. These timetables can be realized using a small number of LSI elements. In FIG. 41, a high frequency main click source such as an OSC and a VCO is provided. This is the 4th F
This corresponds to the VCO in the figure. A counter is provided to count the output, and the output logical value is read from the read-only memory as an address signal.In the output value taken, the timetable of the logical value of the bit of each digit is added to the DEM or MOD shown in Figure 4F. It is possible to set the contents of the read-only memory so that a timetable of clocks is obtained. BC in Figure 4
is the counter of the above-mentioned main oscillator, ROM is a read-only memory, RR is an output register, and terminals l, 2. ...N is a clock line taken out from each digit bit of RR. 1
In the case of a regulator, the main clock source is a voltage controlled oscillator vCO, and four terminals l, 2. . . . The clock generated for each modulation element in N is controlled to be phase-synchronized with the modulation element click of the opposite modulator. The clocks 1 and 2 of CL in FIG. 4F are polyphase clocks with the period of the modulation element, and the clocks 5 and 4 are polyphase clocks with a higher frequency.

The operation of the 6-digital signal processing circuit modulation/demodulation system can be expressed in the form of an operational equation by analysis as shown in the specification of the prior application. Modulation and demodulation functions are performed by processing such operating equations. It is necessary to rationalize these operating equations by mathematical means, ignoring the feasibility of using modulator/demodulator components and device circuits. Next, various means can be considered if the modulation/demodulation function is to be realized by processing these operational formulas. When considering an application to a voice telephone line, the above processing does not need to be particularly fast, and it is advantageous to use a computer-type processing unit that can flexibly execute the operational formula. In this case, the above-mentioned operating equation cannot be used as is; it is necessary to convert it into a sample value operating equation. This is as described in each section above.

If the modulation/demodulation function is to be performed by calculating the sample value operation formula, it is necessary to implement the apparatus shown in FIG. 5A. Fifth
Figure A shows the internal configuration of the MOD in Figure 4F. Terminals 1.2 and 3.4 in FIG. 5A correspond to the same numbered terminals in FIG. 4F. Terminal 3 in FIG. 5A outputs a transmission wave through the t-interface circuit 5 determined by equation (C15).

A signal for inhibiting and opening the transmission code circuit is outputted to the terminal 1 in accordance with the state diagram of the start sequence on the transmission side shown in FIG. 4C. The pull pull D relays this signal. Terminal 4 is a terminal for inputting the output signal of the transmission code circuit, that is, 111 r bi of equation (1, 15) to the DEM. Further, the terminal 2 is a terminal for inputting the ON-OFF signal of the backward channel necessary for controlling the transmitting side start sequence shown in FIG. 4C.

#! Blocks A, B, and C in Figure 5A execute the modulated wave creation flow graph shown in Figure 1A, and A is the block A, B, and C in Figure 1A.
In the figure, (a), B (b), and C (,) perform the processing of the start sequence on the transmitting side shown in FIG. 4C.

The east line 6 in FIG. 5A indicates the output 1IJ5 of the kubuk generation circuit CL shown in FIG. 4F, and the line A in FIG.
In addition to supplying the operating clock to each block up to NG, 9.6.4.8.2-4 KH is supplied to A, B, and C respectively.
Provides four real-time interrupts for z. 5th A
The block RES in the figure is a common memory and is a temporary memory for information for exchanging information between the blocks A to G. In order for each block A and G to access the RES in order to exchange information with other blocks, the MP
Access slots are allocated by a ssit allocator that operates according to an operating clock X. MPX
The output line consists of several bits, and each block is designated by its code configuration.

The common line BO2 is used for each block to address the RES in a given time slot and exchange its contents.

The line that addresses RES is the output line of MPX, and BUS
is used to transfer information.

The clocks A, B, and C in FIG. 5A are computer-type processing units, and first, A is 9.6KH,
RES every time a real-time clock interrupt occurs.
By reading the information content corresponding to block H in Figure 1A recorded at a specific address in Figure 1A (a)
Then, the result f(,T) is recorded in another specific address of the RES. This recorded content is read out when slot G in FIG. 5A is given, converted into an analog/4G signal, and sent out to the line. A smells good,
By executing the last instruction, the next 9.6KH
Enter the real-time clock waiting list.

Next, B executes a program that calculates part (b) of FIG. 1A by being interrupted by a 4-8 KHz real-time clock. The execution result is the first
This corresponds to the clock H in figure A, but its contents are RE
It is recorded at the address specified for H of S. The input data used by this program are A in Figure 1A and &□', bk' in Figure 1C, and the RES address specified for these data is C in Figure 1A, clock processing. updated by. The last command of the above processing program in B is to wait for the next 4.8 KH, or four interrupts.

Next, to the foil δ, C in the figure executes a program that executes the start sequence represented by the part (, ) in Figure 1A and the state diagram in Figure 4C by the 2.4KH clock interrupt. . FIG. 4D shows the functions of this program in the form of logical processing and arithmetic processing flows. The first of the programs executed by C in Figure yA
The 10 inputs in Figure A (t3) correspond to 4 terminals in Figure 4F, and are accepted by the block from the terminal to G in Figure 5A, and the RES designation is made in the slot given to G from MPX. It is recorded in the address.

Next, the digital processing circuit on the demodulation side will be described. FIG. 5B shows the internal structure of the DEM of FIG. 4F. Terminals 1.2, 3, 4.5.6 in FIG. 5B correspond to the same numbered terminals in FIG. 4F. The output of the data channel reception filter indicated by RFD in FIG. 4F is applied to terminal 4 in FIG. 5B.

Also, the signal output from terminal 2 is A in Figure 5B.
, C, ~3 The timing signal calculated by the computer-type processing unit, ie, Z(k T,) in FIG. 3F, is converted into an analog signal by F and output. In the switch S shown in FIG. 4F, the above 2(kT,) is
As shown in Figure 3H, it is disconnected when used to adjust the delay of the automatic equalization filter. The terminal 1 in FIG. 5B transmits a signal for inhibiting received data in the first and second phases generated by executing the start sequence on the receiving side shown in FIG. 4A, that is, by the output 2 in FIG. 4B. put out. Terminal 5 in FIG.
It is connected to the terminal with the symbol A, which indicates carrier disconnection in the figure. The carrier disconnection in FIG. 4E and the process for creating the AGC control signal are shown in A in FIG. 5B.

Calculated by processing units C4-3. 6 in Figure 5B
The modulation code determined by the demodulation processing in A and C4-3, ie, the signal % pbk in FIG. 2E, is output to the terminal . In addition, the terminal numbered 3 is A, 01~
It is performed in three processing units, of which the fourth
It outputs the processing results of parts other than the AGC in Figure E, and this signal is input to the automatic reception gain adjustment circuit including the AD conversion called AGC in Figure f64F. The 0, E, F, G, H, J, etc. directly connected to the above terminals contain temporary registers for the signals input to the above terminals.

These relay registers and processing units A, C□, ClC5
The two systems share a common register called IIES in a time-division manner and enable mutual transfer of byte signals. Each of the clocks accesses the RES to exchange information with other blocks using the MPX shown in FIG. 5B. The method is the same as in FIG. 5A.

At A in FIG. 5B, a real-time clock interrupt of 9.6KH is performed. This time, read the signal at point 6 in Figure 2A that is recorded at a specific address in the RES, process the part (a) in Figure 2A, and then
Signals 9 and 10 in Figure A are recorded in another specific address of the RES. This recorded content is read when C0 in diagram @5B is given a slot. At A in Figure 5B, the last instruction is executed, resulting in the next 9.5K
H.

Enters real-time clock waiting state. Next, 15
C0 in FIG. B executes a program that calculates the portions in FIGS. 2C to 2F when a 2.4 KH real-time clock interrupt is performed.

The execution result is input to the designated address of the RES that records the signal value &kr bk in the i2E diagram.

When C0 is given a slot to access the RES, cooθ and si necessary for the processing in FIGS. 2C to 2F are
Read nθ from the designated address of the RBS where each is recorded. This record is created by the processing of C9. The last instruction in the above process at C0 is 2.
It is used for interrupts of 4KH.

Next, processing is performed by the real-time clock interrupt of C1 in FIG. 5B, which is also 2.4 KH. The processing contents are automatic phase control shown in Figures 3A to 3B, and 3F.
3F to 3H. The input/output signals of automatic phase control are X'(kT,), Y as shown in Figure 3A.
'(kT,) and &2. It is transferred from C0 via a specific address of bkt-RES, and colIθ and sinθ are also transferred to C0 via another specific address of RESO. In addition, the program that automatically controls timing is
X', Y', ak, input as above,
2 (k'I',) created by bk is transferred to the block H connected to terminal 17 in FIG. 5B via a specific address of RES. C3 in Figure 5B is also 2.4K
Processing is performed by an interrupt of the H2 clock, and the start sequence shown in the state diagram shown in FIG.
FIG. 4B shows the functions of the program shown in FIG. 4A, which executes the parts other than the one-dot chain line of the AGC functions shown in FIG. E
, F, G, J and the processing unit in the above description of the communication between the processing units is C. In addition, C, to X', Y'.

ak, bk are transferred.

Figure 5C shows A, B, and C in Figure 5A, and A, C in Figure 5B.
, , C, , C1 shows the internal configuration of each processing unit. The configuration of the processing unit shown in FIG. 5C is basically the same as that of a general-purpose computer of the storage type. When the processing unit is used as shown in FIGS. 6A and 5B, the so-called I10 device is not used like a general-purpose computer.
Connect from the external data bus and control line on the left side of Figure 5C. In the case of Figures 5A and 5B, these I10 devices will be temporarily connected to perform some processing before operating as a modem.

In the conventional system configuration method, the microcode block, controller block, data bus block, memory management block, system bus interface, etc. in FIG. This is what is being done.

Therefore, in the conventional system, the connecting lines between each block create many intersections, as shown in FIG. 5C. However, since these wirings were performed by wiring outside each monolithic structure, there was no problem.

The present invention implements all blocks shown in FIG. 5C in a monolithic structure. This situation becomes extremely difficult to realize with conventional integrated circuit technology due to the above-mentioned intersections. In the present invention, the method of the present invention is applied not only to the internal configuration of each block in FIG. 5C by the method shown in FIGS. 6A to 6I, but also to the wiring between the blocks. It is. That is, the 6th A
The method shown in Figures ~ @ 6■ is to fill in the portion removed by etching of the first wafer with another material. For example, each block shown in Figure 6C is In this method, the connections are not made in the same layer, but the connection lines of each block are grown to different processed layers, and the above-mentioned etching process is performed in that layer to connect the blocks. If overlapping occurs again during this connection, only that wiring is canceled, another layer is layered, and the terminals that could not be wired are grown up to this layer and then connected. According to this method, it is not necessary to form each block in FIG. 5C on the same layer, and as described in 1! It is possible to connect the dashes even if they are formed in different processing layers. The method of FIGS. 6A to 6-6 is believed to improve the yield rate over the conventional method, and therefore allows for a further increase in the number of integrated circuit devices. moreover,
By forming each quadruple in a different layer, the number of devices per layer can be reduced, allowing more devices to be accommodated in a monolithic integrated circuit.

The functional outline of each block in FIG. 5C is as follows.

The data bus block provides the data manipulation functions required by the processing unit and is operated by a series of microinstructions retrieved from the memory of the mic 4 hood. In this case, the address of the memory to be retrieved is
Lovelock specifies. The major subsystems of the data bus block include registers, array shifters, and arithmetic logic circuits.

The controller block includes a microprogram counter that stores the address of the microcode memory and a counter that provides control over the loop of the microphone program. Also, micro program counter,
It also includes a stack for storing the value of the loop control counter.

The memory management block specifies data memory addresses and manages communication between blocks on the data bus. Also, some simple data structures can be formed in the data memory. In this case, this block can divide the memory into several areas and implement different data structures in each area. Four basic data structures can be implemented: stacks, queues, linked lists, and arrays. When performing transversal processing, an array is used as a memory as a data structure, and the microcode uses the management block to shift data on the array or read the value of an element on the array. performs various operations on the shift register.

The system bus interface communicates with other processing systems through the illustrated system bus.

The system bus in Figure 5C represents the connection between each bus in Figure 5-A and the BUS in Figure 5-A.
Also, the system bus enable in FIG. 5C can correspond to the outputs of the MPX in FIG. 6A that are wired to each processing unit. Figure 15A glue, E, F, G, and Figure 5B glue, E, F, G, H,
The BUS side of blocks such as I and J has the same structure as the system-path side of the system bus interface block in FIG. 5C. The above also applies to FIG. 5B.

The clock block generates the operating clock signal necessary for the system, but when it can be driven from each part as shown in the operating clock lines in Figs. 5A to 5B, the external flag terminal in Fig. 5C is connected to the external flag terminal in Fig. i5A. 2, 4, 4.8 in
, 9.6KH, terminal, and 2, 4 in Figure 5B.
, 9.6KH, is connected to the terminal.

Next, a microfabrication method and an etching method applied to connections between blocks in each processing unit of the present invention will be explained.

6. The steps involved in making a structural integrated circuit by microfabrication include etching a film-like forest material. To perform etching,
An original plate called a mask is required to obtain a resist image. A mask works like a photographic plate, and is produced by reducing the size of the object to be processed by obtaining a photograph from an original drawing that has been enlarged to a size that is 10 to 100 times larger than the object to be processed.

To perform this processing, first apply a resist agent to a uniform thickness on the surface of the wafer, harden it, and then
Irradiation of light, electron beams, or generally radiation through a mask. A resist agent is a material whose solubility with respect to a specific chemical solvent changes when irradiated with radiation. A kiln corresponding to a pattern of a specific processing device is drawn on the mask using a well-known electron beam writing method or the like. Next, the portions of the resist agent that have been irradiated with radiation or electron beams that have passed through the window of the mask are altered by radiation or electron beam transfer. When positive development is performed, only the altered parts are dissolved away, creating a film pattern of resist agent on the sea urchin. Next, by a wet or dry etching process that dissolves or removes the wafer, the portion of the wafer to which the resist agent is not attached is removed to form part of the planar fine structure of the intended device.

The present invention enables layered microstructures, and the necessary conditions for this are the above-described process of forming a second wafer to fill in the portions removed by etching of the first wafer. It needs to be possible. Now, suppose that another material is grown on the etched first wafer to form the material for the second wafer, and the surface of this second material is different from the material of the first wafer. A tingling sensation appears in the removed area. The material on the second wafer other than this edge is removed. For this reason, the following processing is performed. A resist agent is again applied onto the second material, and a developing step is performed in which the resist agent on the second wafer is irradiated through the mask used when processing the first wafer. This results in negative development. That is, the resist agent in the portions that have not been irradiated and has not changed in quality is removed, and the material in the removed portions is etched. Thereafter, the resist agent is removed. At this time, if a reverse pattern of the mask used for the first wafer is used, a positive developing process is performed.

That is, the resist agent in the portion that has been altered by irradiation is removed, and the material in that portion is etched.

FIG. 6A shows an example of forming a structure consisting of a three-dimensional distribution of two different materials by the above method, in which devices 20 are formed on the surface of a semiconductor wafer 100 using microfabrication technology or the like.・Usually, on its surface,
A protective film 30 is formed. FIG. 6A shows this situation.

Although an oxide film such as 810H is used for the protective film 30, an insulating film such as resin can also be used. Next, as shown in FIG. 6A (13), an opening 40 is formed in a desired portion of the protective film 30 by the method described above. Thereafter, another material 50 is formed on the top surface of the protective film 30 including the opening 40, as shown in FIG. 6A-C). Next, as shown in FIG. 6A υ), this material 50 is
The etching process is performed leaving only the opening 40 formed in .

At this time, it is necessary to consider the combination of the protective film 30 and the material 50 so that the protective film 30 and the material 50 are not etched at the same time. Next, as shown in FIG. 6A (E), a protective film 31 is again formed on the surface. Below, this protective film 31
By repeating the same steps used in FIGS. 6A-6D, a structure as shown in FIG. 6A-F can be obtained.

Each processed layer in the multilayer process shown in FIG. 6A has its own thickness. This causes side etching. In FIG. 6A, this side etching and raised development on the sides are ignored.

When side etching is performed, the side surface of the processed layer pattern is etched from the edge of the resist, and the finished dimension L is smaller than the resist dimension L8. Figure 6B (
A).

(B) shows this situation, where O is the resist, ■ is the processed layer, and ■ is the substrate. (A) before etching, (B)
shows the appearance after etching. The magnitude of side etching is expressed by the conversion difference, -Lp, which increases in proportion to the thickness of the processed layer. Therefore, with the process of the present invention, bulges may occur at the seams of the material, the magnitude of which depends on the magnitude of this side etching. The dimensions of the mask are determined based on the size required to eliminate protrusions using these side etchings. Figure 6B (C), (D).

(E) shows the results of the steps shown in FIGS. 6A, (B), (C), and (D) by performing side etching as described above, and thereby adjusting the protrusions that occur at the joints of the materials. Therefore, the interface between the two structures shown in FIG. OA (F) is actually not as smooth as shown. From this, the dimensional accuracy of these three-dimensional structures is determined by the size of the side etching.

According to the above method, it is possible to create a three-dimensional distribution of multiple types of materials. In the present invention, these methods can be used to construct a multilayer system in which a plurality of planes are stacked, and FIG. The two structures shown in Figure (F) allow connection with an electronic circuit device system that is further laminated on the top surface.

If the material of the structure 2 in FIG. 6A (F) is conductive, it is possible to couple the upper and lower layer systems by light,
Electrical coupling is possible with conductive materials.

Next, regarding the internal structure of the device, p-type and n-type
distribution of shaped semiconductors is required. For this reason, the method shown in FIG. 6A cannot be used as is, but by modifying these methods depending on the material used, a three-dimensional distribution of pn junctions can be created. First, when using a single-crystal semiconductor such as single-crystal silicon, the single-crystal semiconductor is grown in vapor phase on a conductor substrate, and then an oxide film is grown in vapor phase thereon. Apply a resist film on top of it,
Particle beam irradiation is performed on the portion to be made into an n-type semiconductor, the oxide film that is not irradiated is etched, and n-type impurities are thermally diffused.

The lost oxide film is dissolved and an oxide film is again grown in a vapor phase over the entire surface, and a similar process is performed on the portion to be the p shadow region to perform pV diffusion. This method lacks flexibility in terms of three-dimensional construction because the conductive base must be removed by etching, as will be described later. To provide flexibility in construction methods, the substrate may be an insulator. In this case, if an attempt is made to create a pn junction using the method described above, the semiconductor portion will become polycrystalline and impurities cannot be diffused. In order to create the required three-dimensional distribution of pH junctions by mixing impurities without using a single crystal, an amorphous semiconductor is used instead of a single crystal semiconductor. This is formed by DC discharge decomposition, and PHa is used as an n-type impurity, and B, H, etc. are used as type impurities. , PHs, or B.

This is done by mixing H1.

6C and 6D show that the method of FIG. 6A is applied to the case where a MOS device is constructed using a semiconductor such as amorphous silicon. In Figure 6C, (A)
is 2 on the insulating substrate 10 by the above glow discharge.
The results of the process of forming a semiconductor containing p-type impurity 0 are shown. Next, (B) is obtained by etching 20 of (A). This is done using a dry etching method using a resist image, using CF4. CF, +0. , CF, +N, etc. In (C), an oxide is vapor-phase grown on the entire surface of (B) to form an insulating film 11. In (D), the part above 20 of 11 is etched. in this case,
When the insulating film is S, O, etc., H is used as the etching gas.
In (E), a method different from that used for etching semiconductors is used, such as using a "F" gas.
D) Vapor phase growth of an oxide film etc. is performed on the entire surface of the #lj structure,
In (F), a window is opened above the p-type semiconductor of 20, and (
The same p-type semiconductor 21 as shown in G) is grown and etched by the above method to form a structure shown in (H). Here, (1
- In [), the portion of the insulator 12 above the p-type semiconductor 20 is etched to form the n-type semiconductor of the MOS device. The resist film used at this time was left as it was, an n-type semiconductor of 30 was grown as shown in (J) by a method similar to that of the PFF conductor, and the structure of (K) was obtained by removing the etching resist film. do. The process shown in FIG. 6C (b) (L) to (0) shows the process of making a MOS device and its electrodes using an insulating film 40 and a conductive material 50. [Fig. 6C] In the MOS device constructed by the above steps, @, θ,
2 is the electrode as shown in (0) of the same figure. 9) ■ and @ are conductors shown by 2 in FIG. 6A (F), for example, and are connected to lower-layer electronic circuit devices. (
For the process of making ■ and P), see Figure 00 (A) ~
Not included in (0). If the above electrode process is included (
There are four additional steps in addition to A) to (0).

In the present invention, as described above, processing is performed so that the portion removed by etching of the first wafer is filled with a second wafer, and the spatial distribution of p-type and n-type semiconductors is is controlled by layers. 6th A
As shown in 10.20 of Figure (F), when applied to devices made by conventional microfabrication techniques, it is possible to interconnect integrated circuits made up of multiple layers. In this case, layers other than the bottom layer become an integrated circuit including a system of devices as shown in FIG. 6C (CP).

An example of the method for making an integrated circuit using the device shown in FIG. 6C (P) is as follows.

That is, the configuration of the figure (P) viewed from the top is as shown in the upper row of the figure (Q) (■).

@, θ, ■, @ correspond to the configuration indicated by the same symbol in (P), and θ, ■, ■, ■ in (Q) are electrodes of a device made at the same time as CP). If this device is a diode, for example, the structure of the pn junction part of this diode is manufactured simultaneously with each step from (F) to (0) in Figure 6C, and the layers below this structure are This portion is performed in parallel with the steps (A) to (E) in FIG. 6C, and is formed by growing an insulator similarly to the portions other than the semiconductor portion 20 in this step.

In addition, in the electronic circuit diagram using the MO3A element, the element corresponding to the resistor is composed of the same elements as in Fig. 6C (CP), and is constructed in each step of Fig. 6C, and its terminal is as shown in (Q). It has the same configuration as toeθIO9■. Connections between these devices are made by connecting the terminals shown in Figure 6C (Q) with conductors.
), a single layer of the 1111 film and the terminal conductor is grown on the connection surface, and a metal conductor is deposited on the top surface.
Etching is performed using a mask whose chamber is the wiring pattern connecting the terminals shown in (Q). If cross-wiring occurs, the terminals and the protective film are grown in another layer, and the wiring is performed in the same manner.

According to the present invention, connections between devices are made by providing a layer that serves as a connection surface. If a situation occurs where the connecting lines cross,
Furthermore, since it is only necessary to create a layer that forms a connection surface, the so-called topomagic problem that occurs in conventional integrated circuits does not occur. However, in order to reduce the number of steps as much as possible, connections between devices need to be made internally.

Another step reduction consideration is the need to increase the number of devices included in each layer, which in turn requires less material to be used. In particular, when it is necessary to reduce the thickness of a layer such as layer 40 in FIG. 6C, ie, the insulating layer in the MO8 structure, it is necessary to match the layers for other devices as well. The MaD diagram shows an example of such a process, and 1, 2. ...0 is the layer number, and , [phase], and θ are a bipolar transistor and a device that plays the role of a resistor in a circuit using it, respectively.

M that performs calculations in diodes and analog circuits
It is an OS device. The three layers are, in the MOS device θ,
It is an insulating layer that becomes the base, and in ① it becomes a P-type semiconductor part that becomes the base of the Bibo 5F4# structure. The diode O does not require a particularly thin layer like θ, ■, but in order to match the process with other devices, the p
The process of forming a semiconductor layer is included. The layer 1 consists of a phase analog and a p-type semiconductor, the layer 2 consists of a conductor, a p-type semiconductor, an n-type semiconductor, and an insulator, and the other layers have fewer materials than the two layers. Therefore, the process shown in FIG. 6E is the same as that shown in FIG. 6D (P). With the above thinking, NA
The basic device construction method required to create a logic circuit based on an ND circuit is shown in FIGS. 6F and 6G.

(A), (B).

(C) are inverter, NAND, and NO
It is an R circuit, and is marked ■ in each figure.

O, O respectively show a circuit diagram, a top view of a multilayer arrangement, and a side view of the same multilayer arrangement. The numbers on the right side of the side view are layer numbers, and these devices are constructed in the same process, with a connection surface formed on the top surface and wired by an etching process for wiring. If crossover occurs, the connecting surface will have two or more layers. Furthermore, memory circuits such as flip-flip are configured in the same manner, and are shown in FIG. 6C (D
)become that way. Here, Q, to Q6 are MOS devices as shown in FIG. 6D (CP), and ■, [phase], and O are a circuit diagram, a plan view, and a side view, respectively. In the case of this circuit, in order to match the layers with those shown in FIGS. 01 (A) to (C), a configuration was adopted in which the crossover wiring was routed around.

A similar basic circuit for logic circuits can be considered for bipolar transistors as well. This uses the device shown in Figure 6E (a) as an element, and performs wiring using five layers among the layer numbers shown on the left side of the figure. If not, M.O.
A basic circuit can be created with four layers, which is fewer than the S device. Figure 6H961 shows the NA of the MOS type in Figures 6F and 6G.
This is a basic NAND circuit using bipolar transistors compatible with the basic ND circuit.

In the following explanation regarding the 6th layer diagrams 6H and 6th layer diagram, the MOS device in the explanation regarding the 6F and 6G diagrams is replaced with a bipolar device.

Effects As explained above, according to the present invention, flexible wiring arrangement within the modulation/demodulation unit is possible, and the modulation/demodulation method (
By efficiently connecting partial functions in the system, a unit can be realized with a relatively small space, and each function can be easily optimized, allowing high-efficiency transmission.

[Brief explanation of the drawing]

FIG. 1A is a block diagram of an arithmetic circuit used in a modulation/demodulation unit showing an embodiment of the present invention, and FIGS.
Detailed view of the shift registers A, B, part 2A of the figure.
Figure 2B is a block diagram of the circuit that processes equation (2, 11), Figure 2C is a block diagram of the automatic equalization processing circuit, and Figure 2C is a block diagram of the automatic equalization processing circuit.
Figure D is a block diagram of the transversal filter adjustment processing circuit, and Figure 2E is (2, 1e), (2, 19).
Figure 2F is a block diagram of the equation processing circuit, Figure 2F is a diagram of the circuit that calculates the predicted value of the output error of the serial automatic equalizer, Figure 2G is the circuit diagram of brick N of the shift register, and Figure 3A is the low frequency A circuit diagram using a pass filter, Figure 3B, is a digital
Figure 3C is a diagram of the filter processing circuit, Figure 3C is a configuration diagram of a multi-lag filter circuit, Figure 3D is a diagram of a circuit that replaces the circuit N in Figure 2G, and Figure 3E is a diagram of the master clock oscillation circuit. The block diagram and Figure 3F are (5, 9), (3, 1
o) A diagram of the circuit that processes the equation, Figure 3G is a diagram of the timing adjustment processing circuit, Figure 3H is a diagram of the calculation processing circuit of the equation (3°14), and Figure 4A is the state of the start sequence on the demodulation side. The transition diagram and M4B diagram are block diagrams of the control circuit of the demodulator,
FIG. 4C is a state transition diagram of the start sequence on the modulation side, FIG. 4D is a block diagram of a processing circuit that performs the control in FIG. 4C, and FIG. 4E is a block diagram of a received modulated wave AGC circuit.
Figure 4F is an overall system diagram of the processing circuit and peripheral circuits, and Figure 4G
The figure is a signal processing diagram of a circuit that maintains return loss between transmission and reception, Figure +H is a processing flow diagram of equations (4, 8) and (4, 9), Figure 2641 is a block diagram of a clock supply circuit, and Figure 5A is the internal configuration diagram of the modulation unit ('MOD) in Figure 4F,
Figure 5B is an internal configuration diagram of the demodulator (DEM) in Figure 4F;
Figure 5C is A, B, C, C□~C of Figure 5A and Figure 5B.
8, the mQA diagram is a cross-sectional view of a structure consisting of three-dimensional distribution of different materials, Figure 6B is a diagram of the multilayer process before and after etching, and Figures 6C and 6D are diagrams of 6A.
In the figure, a MOS device is constructed using a semiconductor such as amorphous silicon, FIG. 6E is a cross-sectional diagram of an O resistance transistor, an @ diode, and a θ multiplication device. is (A)
Inverter, (B) NAND. (C) NOR, (D) Multilayer structure plan and side view for storage device, Figures 60 and 6I are for (A) inverter, (B) NAND, (C) NOR, (D) storage device. FIG. 2 is a circuit configuration diagram using bipolar transistors. 10: semiconductor wafer, 20: device, 30 = protective film,
40 = opening. 1 l I 1 ward. 1+l'1 m,, + + 1,' + ++ 2nd G Figure OhO 3rd A Figure X'(kT,,) Y'(kT2) 3rd B Figure (a) 3rd D Figure 1 2 - --- -, I. Figure 3E Figure 4E Figure QE-1ρTo匡匡 ■ ■ Figure 4G (a) Figure 4H (a) 1710 of the drawing (content 1 unchanged) Figure 41 Figure 6 A Figure 30 Figure 6 Figure B Figure 6 Figure C Figure 6D Figure 6 Name Modulation/Demodulation Unino 1-3 Relationship with the person making the amendment Patent No. R applicant 4, agent

Claims (2)

[Claims] (1) Equipped with a plurality of processing units assigned to each function and a common memory for communication between the processing units, and a plurality of layers formed between each block in each processing unit by microfabrication and etching. A modulation/demodulation unit characterized in that it is connected by configuring. (2) The modulation/demodulation unit according to claim 1, wherein the processing unit performs the modulation/demodulation operation by processing a mathematically determined sample value operation equation.