JPH05102143A - Method for forming wiring of semiconductor device - Google Patents

Method for forming wiring of semiconductor device

Info

Publication number
JPH05102143A
JPH05102143A JP25684991A JP25684991A JPH05102143A JP H05102143 A JPH05102143 A JP H05102143A JP 25684991 A JP25684991 A JP 25684991A JP 25684991 A JP25684991 A JP 25684991A JP H05102143 A JPH05102143 A JP H05102143A
Authority
JP
Japan
Prior art keywords
wiring
mask
layer
sio2
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25684991A
Other languages
Japanese (ja)
Inventor
Tomotoshi Inoue
智利 井上
Kenichi Tomita
健一 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25684991A priority Critical patent/JPH05102143A/en
Publication of JPH05102143A publication Critical patent/JPH05102143A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To resolve the problem of mask matching at the time of additionally piling up a metal for wiring by forming SiO2 which thicker than a first wiring layer by liquid phase growth after the first wiring is formed and growing a metal by plating on the first wiring by using the SiO2 as a mask. CONSTITUTION:At the time of forming the wiring of a semiconductor device, a metallic layer 5 is formed on a first wiring layer 3 after the wiring layer 3 is formed. In such wiring, SiO2 4 is formed on the layer 3 so that the SiO2 4 can become thicker than the layer 3 by liquid phase growth after the layer 3 is formed and the metallic layer 5 is grown by plating on the layer 3 by using the SiO2 4 as a mask. For example, after an SiO2 film 2 is for on a GaAs substrate 1, Ti/Pt/Au wiring 3 is formed on the film 2 by using a spacer lifting- off method. Then, after forming a thick SiO2 film 4 by liquid-phase growth, electroless plating 5 of Au is performed by using the film 4 as a mask.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】半導体装置の配線の形成に係わ
り、特に配線の低抵抗が必要となる場合の厚い配線の形
成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the formation of wiring for semiconductor devices, and more particularly to the formation of thick wiring when low resistance of the wiring is required.

【0002】[0002]

【従来の技術】従来の配線を厚くする方法を図2に示
す。
2. Description of the Related Art A conventional method for thickening a wiring is shown in FIG.

【0003】まず公知の技術たとえばスペーサリフトオ
フ法などを用いて半導体上に第1の配線層を形成する図
2(a)、この配線を厚くするために、まず第1の配線
のパターンにあわせてフォトリソグラフ技術によりフォ
トレジストを第1の配線と同じか又はそのパターンの内
側が開口するように形成する。これは、近接した絶縁さ
れるべき第1の配線が同一の開口部に存在しないように
するためである。
First, a first wiring layer is formed on a semiconductor by using a known technique, such as a spacer lift-off method, as shown in FIG. 2A. In order to thicken this wiring, first, a pattern of the first wiring is formed. A photoresist is formed by the photolithography technique so as to be the same as the first wiring or have an opening inside the pattern. This is to prevent adjacent first wirings to be insulated from existing in the same opening.

【0004】しかしながら近年の配線は非常に微細に加
工されているため、マスク形成時の合せ精度が追いつか
ず、この合せずれを見込んだ上でフォトレジストを形成
しなければならない。実際には、このため第1の配線の
内側に形成する必要がある。又極めて微細な配線上は、
レジストの開口が困難であった。そして上記のフォトレ
ジストをマスクとしてメッキ法によりレジスト開口部に
金属層を形成して厚くしている。
However, since the wiring in recent years is extremely finely processed, the alignment accuracy at the time of mask formation cannot keep up, and the photoresist must be formed in consideration of this misalignment. In practice, therefore, it is necessary to form it inside the first wiring. Also, on extremely fine wiring,
It was difficult to open the resist. Then, a metal layer is formed in the resist opening by the plating method using the above photoresist as a mask to thicken it.

【0005】この方法の場合、先に述べたレジストパタ
ーンの形成が非常に重要であり、第1の配線と同じか又
は小さいパターンを開口する必要があるが、第1の配線
をフォトリソグラフの限界寸法とした場合は、この様な
レジストパターンを形成することは不可能となる。又、
仮に形成できたとしても最終形状は非常に段差の大きい
ものができるため、上層の配線形成において種々の障害
が発生することは、明らかである。
In this method, the formation of the resist pattern described above is very important and it is necessary to open a pattern which is the same as or smaller than the first wiring, but the first wiring is limited by photolithography. When the dimensions are set, it becomes impossible to form such a resist pattern. or,
Even if it can be formed, the final shape can have a very large step, so that it is obvious that various obstacles occur in the formation of the wiring in the upper layer.

【0006】[0006]

【発明が解決しようとする課題】上記の様に従来の配線
形成方法では、積み増しする時のマスクとなるレジスト
の形成及び合せが難しく微細な配線上に積み増しできな
いという問題及びでき上り形状の段差が非常に大きいと
いう問題があった。
As described above, according to the conventional wiring forming method, it is difficult to form and align a resist that serves as a mask for the additional wiring, and it is impossible to build up on a fine wiring. There was the problem of being very large.

【0007】本発明は、この問題に対して有効な解決を
与えるものであり第1の問題に対しては、積み増しを自
己整合的に行う方法を提供する。この時同時に第2の問
題の解決できる方法を提供する。
The present invention provides an effective solution to this problem and, for the first problem, provides a method of self-aligning the build-up. At the same time, a method capable of solving the second problem is provided.

【0008】[0008]

【課題を解決するための手段】前述した問題を解決する
手段は、第1の配線を形成した後に液相成長SiO
2(LPD−SiO2 )を第1の配線をマスクとして自
己整合的に成長させる。この時重要な点は、後のメッキ
工程のマスクとなる様に第1の配線の厚さにメッキ成長
厚さを加えた厚さにまでLPD−SiO2 を成長させる
ことである。これにより第1の配線にマスク合せを全く
行うことなくマスクを形成できる。即ち、まず第1の配
線を親水性の絶縁膜上に形成する。次にこの親水性の絶
縁膜上に第1の配線層をマスクとしてSiO2 を液相成
長法で自己整合的に成長させる。この時、液相成長の厚
さは、第1の配線の厚さに、積み増す予定の分だけ加え
た厚さに成長させる。この時、液相成長したSiO
2 は、自己整合的に配線上を開口しているから、このS
iO2 をマスクとしてメッキを行う。又メッキは、Si
2 の表面と同じ厚みまで行う。これにより自己整合的
に厚く、かつ平坦な配線が可能となる。
[Means for Solving the Problems] A means for solving the above-mentioned problems is to form a liquid phase growth SiO after forming a first wiring.
2 (LPD-SiO 2 ) is grown in a self-aligned manner using the first wiring as a mask. At this time, an important point is to grow LPD-SiO 2 to a thickness obtained by adding the plating growth thickness to the thickness of the first wiring so as to serve as a mask for the subsequent plating process. As a result, the mask can be formed on the first wiring without performing any mask alignment. That is, first, the first wiring is formed on the hydrophilic insulating film. Then, SiO 2 is grown on the hydrophilic insulating film in a self-aligned manner by a liquid phase growth method using the first wiring layer as a mask. At this time, the thickness of the liquid phase growth is made to be the thickness of the first wiring plus the thickness to be accumulated. At this time, liquid phase grown SiO
2 has an opening on the wiring in a self-aligned manner, so this S
Plating is performed using iO 2 as a mask. Also, the plating is Si
Perform to the same thickness as the surface of O 2 . This enables thick and flat wiring in a self-aligning manner.

【0009】[0009]

【作用】上記LPD−SiO2 は、第1の配線のみを開
口した理想的なマスクとなるため微細な配線、特に隣接
した配線のスペース部が極めて小さい場合でも配線の増
積による低抵抗化が可能となる。又LPD−SiO2
マスクとしてメッキを行う場合は、一般のレジストの場
に問題となる炭素によるメッキ液の汚染が少ないなどの
効果もある。
Since the LPD-SiO 2 serves as an ideal mask in which only the first wiring is opened, the resistance can be reduced by increasing the wiring even if the wiring is fine, especially when the space between adjacent wirings is extremely small. It will be possible. In addition, when plating is performed using LPD-SiO 2 as a mask, there is an effect that the plating solution is less contaminated by carbon, which is a problem in general resists.

【0010】[0010]

【実施例】本発明の一実施例としてGaAs半導体の配
線に応用した場合を示す。図1(a)〜(c)を用いて
説明する。
EXAMPLE As an example of the present invention, the case of application to wiring of a GaAs semiconductor will be shown. This will be described with reference to FIGS.

【0011】まず、GaAs基板上に絶縁膜(2)を形
成する。この時この絶縁膜は、後の工程で行うSiO2
液相成長(LPD)が可能となる親水性の絶縁膜、例え
ば、SiO2 などを用いる。しかる後に、従来より公知
のスーペーサリフトオフ法を用いてこの絶縁膜上にTi
/Pt/Auの配線(Ti500nm/Pt500nm
/Au10000nm)の形線を形成する。次に、この
基板を公知の技術であるLPD法によりSiO2 膜を形
成するためフッ化硅水素の過飽和液中に浸漬する。通常
は平坦化などに用いられるため成長膜厚は、先の配線と
同じ厚さ、本実施例にあてはめると11000nm成長
させている。しかし本発明では、これを自己整合的なマ
スクとして用いるため行なっているので、11000n
mに当初の目的である積み増しによる厚膜のため、その
厚み分を見込みさらに厚く成長させる。本実施例の場合
は、さらに2μmを加えて計3.1μm成長させた。
First, an insulating film (2) is formed on a GaAs substrate. At this time, this insulating film is formed of SiO 2 which will be used in a later step.
A hydrophilic insulating film that enables liquid phase growth (LPD), such as SiO 2 , is used. After that, Ti is formed on the insulating film by using a conventionally known spacer lift-off method.
/ Pt / Au wiring (Ti500nm / Pt500nm
/ Au 10000 nm). Next, this substrate is dipped in a supersaturated solution of hydrogen fluoride to form a SiO 2 film by the well-known LPD method. Since it is usually used for flattening or the like, the growth film thickness is the same as that of the previous wiring, which is 11000 nm when applied to this embodiment. However, in the present invention, since this is used as a self-aligning mask, 11000n
Since m is a thick film formed by the addition, which is the original purpose, the thickness is expected to grow thicker. In the case of this example, 2 μm was further added to grow a total of 3.1 μm.

【0012】これにより配線の上部のみ自己整合的に開
口したマスクが形成された。このSiO2 をマスクとし
てAuの無電解メッキを行うことにより、マスク合せを
行なわずに厚く積み増すことに成功した。又この時Au
のメッキをマスクの上面と同じ高さまで成長させれば同
時に副次的に平坦化がなされる。
As a result, a mask was formed in which only the upper portion of the wiring was opened in a self-aligned manner. By performing electroless plating of Au using this SiO2 as a mask, it succeeded in stacking thickly without performing mask alignment. Also at this time Au
If the plating is grown to the same height as the upper surface of the mask, planarization is secondarily performed at the same time.

【0013】本実施例は本発明の1例に過ぎず、例え
ば、第1の配線形成をリフトオフでなくミリング用いた
場合を考えると、GaAs基板に全面堆積されたSiO
2 上に、Ti/Auを全面にデポジションし、レジスト
をマスクとして所望のパターンにTi/Auを加工す
る。この後レジストを除去することなくLPD成長させ
てその後にレジストを除去し後は、同様にメッキすれば
よい。この時ミリングのマスクはLPDのマスクとして
も有効に働くためLPD後に取る方が良いことが分って
いる。
This embodiment is only one example of the present invention. Considering, for example, the case where the first wiring is formed by milling instead of lift-off, the SiO deposited over the entire surface of the GaAs substrate is considered.
Then , Ti / Au is deposited on the entire surface, and Ti / Au is processed into a desired pattern using the resist as a mask. After that, LPD growth is performed without removing the resist, the resist is removed thereafter, and plating is similarly performed. At this time, the milling mask works effectively also as a LPD mask, and it has been found that it is better to take it after LPD.

【0014】[0014]

【発明の効果】本発明によればGaAsICなどで問題
に必要となる配線の低抵抗化のために行う配線用金属の
増し積みにおいて問題となるマスク合せの誤差を自己整
合的にマスクを形成することにより解決することができ
る。
According to the present invention, a mask is formed in a self-aligning manner with respect to a mask alignment error, which is a problem in increasing wiring metal for reducing the resistance of a wiring required for a GaAs IC or the like. It can be solved by

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例の図。FIG. 1 is a diagram of an embodiment of the present invention.

【図2】 従来例の図。FIG. 2 is a diagram of a conventional example.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置の配線形成において、第1の
配線を形成した後に該第1の配線上にさらに金属層を形
成する配線において、第1の配線を形成した後にSiO
2 を液相成長法により第1の配線層より厚く形成する工
程と該SiO2 をマスクとして第1の配線上に渡金によ
り金属を成長させる工程を少なくとも含む半導体装置の
配線形成方法。
1. In the wiring formation of a semiconductor device, in a wiring in which a metal layer is further formed on the first wiring after forming the first wiring, SiO is formed after the first wiring is formed.
A method for forming a wiring of a semiconductor device, comprising at least a step of forming 2 thicker than a first wiring layer by a liquid phase epitaxy method and a step of growing a metal on the first wiring by a metal transfer using the SiO 2 as a mask.
JP25684991A 1991-10-04 1991-10-04 Method for forming wiring of semiconductor device Pending JPH05102143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25684991A JPH05102143A (en) 1991-10-04 1991-10-04 Method for forming wiring of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25684991A JPH05102143A (en) 1991-10-04 1991-10-04 Method for forming wiring of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05102143A true JPH05102143A (en) 1993-04-23

Family

ID=17298270

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25684991A Pending JPH05102143A (en) 1991-10-04 1991-10-04 Method for forming wiring of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05102143A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08255911A (en) * 1994-12-30 1996-10-01 Siliconix Inc Longitudinal power mosfet with thick metallic layer for reducing distributed resistance, and its manufacture
JPH08264785A (en) * 1994-12-30 1996-10-11 Siliconix Inc Integrated circuit die and its manufacture
EP0916498A1 (en) * 1997-11-14 1999-05-19 Canon Kabushiki Kaisha Ink jet recording head, method for producing the same and recording apparatus equipped with the same
JP2017208524A (en) * 2016-05-18 2017-11-24 モテク インダストリーズ インコーポレイテッド. Execution of electric plating to penetration conductive film of solar battery and manufacturing of electrode of solar battery

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08255911A (en) * 1994-12-30 1996-10-01 Siliconix Inc Longitudinal power mosfet with thick metallic layer for reducing distributed resistance, and its manufacture
JPH08264785A (en) * 1994-12-30 1996-10-11 Siliconix Inc Integrated circuit die and its manufacture
EP0916498A1 (en) * 1997-11-14 1999-05-19 Canon Kabushiki Kaisha Ink jet recording head, method for producing the same and recording apparatus equipped with the same
US6609783B1 (en) 1997-11-14 2003-08-26 Canon Kabushiki Kaisha Ink jet recording head, method for producing the same and recording apparatus equipped with the same
JP2017208524A (en) * 2016-05-18 2017-11-24 モテク インダストリーズ インコーポレイテッド. Execution of electric plating to penetration conductive film of solar battery and manufacturing of electrode of solar battery

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