JPS6057089B2 - Parity control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity control method that allows parity to be easily generated in a microprogram control processing device.

FIG. 1 shows the general configuration of a microprogram control type processing device, where 1 is a control memory, 2 is a control memory at 1, a female register, 3 is a +1 circuit, 4 is an instruction register, and 5 is a control memory. 6 indicates an X register, 6 indicates a Y register, 7 indicates an arithmetic logic unit, and 8-0 to 8-n indicate external registers.

In the microprogram control type processing device shown in FIG. 1, a plurality of external registers 8-0 that can be read or written by microinstructions for various controls
8-n are provided.

Among these types of external registers, there are those that do not have a parity bit, and those that change irrespective of microinstructions and cannot guarantee parity. In conventional technology, a parity generator is provided for each external register that does not have a parity bit and for external registers that cannot guarantee parity, but such conventional technology requires a complicated circuit configuration on the external register side. It has the disadvantage of being SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks and to provide a parity control method that allows parity generation to be easily performed in a microprogram control processing device.

Therefore, the parity control method of the present invention includes a control memory in which a plurality of microinstructions are stored, an instruction register in which microinstructions read from the control memory are set, a plurality of arithmetic registers, and an arithmetic logic unit. , and a plurality of external registers, a parity generator that generates parity based on the data of the arithmetic register X, which is provided on the output side of one arithmetic register X; a parity selection circuit that selects either the parity generated by the parity generator or the parity of the calculation register X according to the value of the data at a predetermined bit position of the instruction register; The device is characterized in that it is configured such that the parity generated by the processing can be sent to the arithmetic logic unit or external register together with the data. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention, in which 9 is a NOT circuit, 1
0 is parity generator, 11 and 12 are AND circuit, 13 is 0R circuit, DA is write external register address, SA
indicates a read external register address, and PC indicates a parity control flag, respectively.

Parity generator 10 generates parity bits according to the data in X register 5.

When the parity control plug PC is logic 11j, the parity bits generated by the parity generator 10 are included with the data. The signal is sent to an external register or arithmetic logic unit via an AND circuit 11 and an OR circuit 13. If the parity control flag PC is logical RO, the parity bit of the X register 5 is sent to an external register or arithmetic control unit along with the data. The contents of the instruction register 4 in FIG. 2 indicate a MOVE instruction.

When a MOVE instruction is executed, data is read from the external register specified by the read external register address SA of the microinstruction, and this read data is stored in x register 5.
is set to MOVE command parity control plug P
When C is at logic Rlj, the parity bit generated by parity generator 10 is selected, and this parity bit and the data in X register 5 are sent to the external register specified by write external register address DA. M.O.
If the parity control flag PC of the VE instruction is logical ROJ, the . Data and parity bits are sent to the external register specified in the DA portion of the MOVE instruction. FIG. 3 shows the format of an operation instruction. In the case of an arithmetic instruction, bits 0 to 4 of the microinstruction are R.
Bits 5 to 7 indicate the function of the arithmetic logic unit 7. For example, when bits 5 to 7 are ROOOJ, X+Y; when rOOlJ, X+Y+1; when 0010J, Y-X; when rOOLL, Y-X-1; when r100J, Y+1; when r10, Y4Y. When it is rllO, it shows XORY. When it is rll, it shows XANDY.

Bits 8 to 15 of the operation instruction are the same as the MOVE instruction. Note that when an arithmetic instruction is executed, data read from the external register or data from the instruction register 4 is stored in the Y register 6 in advance. Furthermore, not only data but also parity bits are input to the arithmetic logic unit 7. When an arithmetic instruction is executed, the S of the arithmetic instruction is
Data is output from the external register designated by the A section, and this read data is set in the X register 5.

When the parity control flag PC of the arithmetic instruction is logic RlJ, the parity bit generated by the parity generator 10 and the data in the X register 5 are input to one input of the arithmetic logic unit 7, and the Y The data and parity of the registers are input to the other input of the arithmetic logic unit 7. The parity control flag PC of the operation instruction is logic R.
O. In the case of J, the data and parity of the X register 5 are input to one input of the arithmetic and logic unit, and the data and parity of the Y register 6 are input to the other input of the arithmetic and logic unit 7. The output from the arithmetic logic unit 7 is set in the X register 5 again. As is clear from the above description, according to the present invention, there is no need to provide a large number of parity generators on the external register side as in the conventional system, but only a parity generator is provided on the output side of one arithmetic register. Therefore, the circuit configuration on the external register side can be greatly simplified.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the general configuration of a microprogram control type processing device, FIG. 2 is a block diagram of one embodiment of the present invention, and FIG. 3 is a diagram showing the data format of arithmetic instructions. .

Claims (1)

[Claims] 1. A microprogram control comprising a control memory in which a plurality of microinstructions are stored, an instruction register in which microinstructions read from the control memory are set, a plurality of arithmetic registers, an arithmetic logic unit, and a plurality of external registers. In the processing device according to the method, a parity generator is provided on the output side of one arithmetic register X and generates parity based on the data of the arithmetic register X, and a parity generator is provided on the output side of one arithmetic register Accordingly, a parity selection circuit is provided for selecting either the parity generated by the parity generator or the parity of the arithmetic register A parity control method characterized by being configured so that it can be sent to a register.