JPS6056297B2 - Airtight mounting structure for integrated circuit elements - Google Patents
Airtight mounting structure for integrated circuit elementsInfo
- Publication number
- JPS6056297B2 JPS6056297B2 JP51032521A JP3252176A JPS6056297B2 JP S6056297 B2 JPS6056297 B2 JP S6056297B2 JP 51032521 A JP51032521 A JP 51032521A JP 3252176 A JP3252176 A JP 3252176A JP S6056297 B2 JPS6056297 B2 JP S6056297B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- ceramic sheet
- integrated circuit
- hole
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Description
【発明の詳細な説明】
本発明は集積回路装置の気密実装構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an airtight mounting structure for an integrated circuit device.
集積回路装置では、半導体チップの電極接続部の信頼度
が集積回路装置全体の信頼度を大きく左右している。In an integrated circuit device, the reliability of the electrode connection portion of a semiconductor chip greatly influences the reliability of the entire integrated circuit device.
このため高い信頼度を必要とする集積回路装置では、例
えばセラミックパッケージを用い、半導体チップを完全
に気密封止を行つているがガラスシールや金属カバーの
溶接によつて気密封止を行つているため実装コストが非
常に高くつくとう欠点があつた。For this reason, in integrated circuit devices that require high reliability, for example, a ceramic package is used to completely hermetically seal the semiconductor chip, but airtight sealing is also achieved by welding a glass seal or metal cover. Therefore, the drawback was that the implementation cost was extremely high.
本発明の目的は、上記した従来技術の欠点を改善し、気
密封止が簡単に行える経済的な集積回路装置の気密実装
構造を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks of the prior art and to provide an economical hermetic packaging structure for an integrated circuit device that can be easily hermetically sealed.
本発明の特徴は、第１のセラミックシートおよび第２の
セラミックシートよりなるセラミック基板を用い、第１
のセラミックシートにはその表面に配線導体を設け、第
２のセラミックシートは半”導体チップとほぼ等しい厚
さとし、その周囲表面に金属層を形成した半導体チップ
収納穴を形成する貫通穴を設け、第１のセラミックシー
トの表面に第２のセラミックシートを重ね合せて半導体
チップ収納穴を形成し、裏面に金属層を形成した半導体
チップを前記チップ収納穴内にフェースダウンボンディ
ングし、半導体チップ裏面周囲とチップ収納穴の周囲と
をはんだのごとき低融点金属を用いて、ブリッジさせて
気密実装するようになしたものである。A feature of the present invention is that a ceramic substrate consisting of a first ceramic sheet and a second ceramic sheet is used;
The second ceramic sheet is provided with a wiring conductor on its surface, the second ceramic sheet has a thickness approximately equal to that of the semiconductor chip, and a through hole is provided to form a semiconductor chip storage hole with a metal layer formed on the peripheral surface of the second ceramic sheet. A second ceramic sheet is superimposed on the surface of the first ceramic sheet to form a semiconductor chip storage hole, and a semiconductor chip with a metal layer formed on the back surface is face-down bonded into the chip storage hole, and the semiconductor chip is bonded face-down to the periphery of the back surface of the semiconductor chip. The periphery of the chip storage hole is bridged with a low melting point metal such as solder for airtight mounting.
以下、図を用いて、本発明の一実施例を詳細に説明する
。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図は本発明による集積回路装置の実装構造の一実施
例の横断面図で、第２図はその上面図である。FIG. 1 is a cross-sectional view of an embodiment of a mounting structure for an integrated circuit device according to the present invention, and FIG. 2 is a top view thereof.
第１図および第２図において、１は第１のセラミックシ
ート１４と第２のセラミックシートＩＢよりなるセラミ
ック基板である。２は第２のセラミックシートＩＢに設
けられた、半導体チップ３の収納用貫通穴、４は第１の
セラミツクシー卜１Ａの表面上に設けた配線導体である
。In FIGS. 1 and 2, reference numeral 1 denotes a ceramic substrate consisting of a first ceramic sheet 14 and a second ceramic sheet IB. Reference numeral 2 designates a through hole for accommodating the semiconductor chip 3 provided in the second ceramic sheet IB, and 4 designates a wiring conductor provided on the surface of the first ceramic sheet 1A.
５はチップ収納用貫通穴２の周囲表面に形成した金属層
である。Reference numeral 5 denotes a metal layer formed on the peripheral surface of the chip storage through hole 2.
第２のセラミックシート１Ｂの厚さは、第２のセラミッ
クシートの表面と半導体チップ裏面とがほぼ同一平面に
なる厚さであり、大略半導体チップの厚さに等しい。６
は半導体チップ３の裏面に形成した金属導体層である。The thickness of the second ceramic sheet 1B is such that the front surface of the second ceramic sheet and the back surface of the semiconductor chip are approximately on the same plane, and is approximately equal to the thickness of the semiconductor chip. 6
is a metal conductor layer formed on the back surface of the semiconductor chip 3.
７は半導体チップの電極であり、半導体チップ３は第１
のセラミックシート１Ａの表面に第２のセラミックシー
ト１Ｂに重ね合せることにより出来た収納穴２に第１の
セラミックシート１Ａの表面の配線導体４と半導体チッ
プ３の電極７とによりフェースダウンボンディングする
如く収納されている。7 is an electrode of the semiconductor chip, and the semiconductor chip 3 is the first electrode.
The wiring conductor 4 on the surface of the first ceramic sheet 1A and the electrode 7 of the semiconductor chip 3 are bonded face down to the storage hole 2 formed by overlapping the second ceramic sheet 1B on the surface of the ceramic sheet 1A. It is stored.
そしてこの半導体チップ３裏面周囲に形成した金属導体
層６とチップ収納穴周囲に形成された金属導体層５との
間には、はんだ８が盛られ半導体チップとチップ収納穴
とのすきまは、はんだがブリッジされ半導体チップの接
続部は気密封止される。尚このすきまはできるだけ少な
い方がこのましい。第３図は本発明の別の実施例を示す
断面図で２枚のセラミックシート１０Ａ，１０Ｂよりな
るセラミック基板±ｕに複数個の半導体チップ３を第１
図図示の第１の実施例と同様の方法によつて実装気密封
止したものである。以上の実装気密封止は、チップ収納
穴と同じ形状のリング状はんだをのせて加熱するか、あ
るいは、はんだ槽に表面を浸けるなどによつて簡単に行
うことができる。Solder 8 is applied between the metal conductor layer 6 formed around the back surface of the semiconductor chip 3 and the metal conductor layer 5 formed around the chip storage hole, and the gap between the semiconductor chip and the chip storage hole is filled with solder. are bridged and the connection portion of the semiconductor chip is hermetically sealed. It is preferable that this gap be as small as possible. FIG. 3 is a sectional view showing another embodiment of the present invention, in which a plurality of semiconductor chips 3 are mounted on a ceramic substrate ±u made of two ceramic sheets 10A and 10B.
It is mounted and hermetically sealed by the same method as the first embodiment shown in the figure. The above mounting airtight sealing can be easily performed by placing a ring-shaped solder having the same shape as the chip storage hole and heating it, or by dipping the surface in a solder bath.
なお気密封止材料としては、はんだ以外の低融点金属で
もよい。Note that the hermetic sealing material may be a low melting point metal other than solder.
以上説明したように本発明を用いればきわめて簡単な実
装構造で集積回路素子の気密封止を行うことが可能とな
り、大きな経済的効果が得られる。As explained above, by using the present invention, it is possible to hermetically seal an integrated circuit element with an extremely simple mounting structure, and a large economic effect can be obtained.
なお気密封止のために形成した第２のセラミックシート
のチップ収納穴周囲表面の金属層を接地あるいは定電位
点に接続しておけば、半導体チップ内素子への外部から
のノイズの影響防止や、同一チップ内で分離されている
べき回路素子間の静電結合の防止効果も得られる。Note that if the metal layer on the surface around the chip storage hole of the second ceramic sheet formed for airtight sealing is connected to ground or a constant potential point, the influence of external noise on the elements inside the semiconductor chip can be prevented. This also provides the effect of preventing electrostatic coupling between circuit elements that should be separated within the same chip.
またさらには、半導体チップの放熱効果も大きい。Furthermore, the heat dissipation effect of the semiconductor chip is also great.
第１図は本発明による集積回路素子の気密実装構造の一
実施例の横断面図、第２図は第１図図示の気密実装構造
の上面図、第３図は本発明の他の実施例の横断面図を示
す。
１，■・・・・・・セラミック基板、１Ａ，１０Ａ・・
・・・第１のセラミックシート、１Ｂ，１０Ｂ・・・・
・・第２のセラミックシート、２・・・・・・チップ収
納用貫通穴、３・・・・・・半導体チップ、４・・・・
・・配線導体、５・・・・・・金属層、６・・・・・・
チップ裏面金属層、７・・・・・・電極、８・・・・・
・気密封止用はんだ。FIG. 1 is a cross-sectional view of an embodiment of an airtight mounting structure for integrated circuit elements according to the present invention, FIG. 2 is a top view of the airtight mounting structure shown in FIG. 1, and FIG. 3 is another embodiment of the invention. A cross-sectional view is shown. 1, ■... Ceramic substrate, 1A, 10A...
...First ceramic sheet, 1B, 10B...
...Second ceramic sheet, 2...Through hole for chip storage, 3...Semiconductor chip, 4...
...Wiring conductor, 5...Metal layer, 6...
Chip back metal layer, 7...electrode, 8...
・Solder for airtight sealing.
Claims (1)
で成る多層セラミック基板において、第１のセラミック
シートの表面に配線導体を設け第２のセラミックシート
は半導体チップの厚さとほぼ等しい厚さとし、その周囲
表面に金属層を形成した半導体チップ収納用貫通穴を設
け、第１のセラミックシートの表面に第２のセラミック
シートを重ね合せて半導体チップ収納穴を形成し、裏面
に金属層を形成し表面にボンディング用電極を有する半
導体チップを前記半導体チップ収納穴内に収納して第１
のセラミックシート表面の配線導体と半導体チップの電
極とをフェイスダウンボンディングし、半導体チップ裏
面周囲と、前記第２のセラミックシートに設けられたチ
ップ収納用貫通穴周囲表面の金属層との間を低融点金属
により接続して気密封止を行うようにしたことを特徴と
する集積回路素子の気密実装構造。1. In a multilayer ceramic substrate consisting of a first ceramic sheet and a second ceramic sheet, a wiring conductor is provided on the surface of the first ceramic sheet, the second ceramic sheet has a thickness approximately equal to that of the semiconductor chip, and the surrounding surface A through hole for storing a semiconductor chip is formed with a metal layer formed on the surface, a second ceramic sheet is superimposed on the surface of the first ceramic sheet to form a hole for storing the semiconductor chip, a metal layer is formed on the back surface, and bonding is performed on the surface. A semiconductor chip having an electrode for use is stored in the semiconductor chip storage hole and the first
The wiring conductor on the surface of the second ceramic sheet and the electrode of the semiconductor chip are face-down bonded, and the bond between the back surface of the semiconductor chip and the metal layer on the surface around the chip storage through hole provided in the second ceramic sheet is bonded face-down. An airtight mounting structure for an integrated circuit element, characterized in that the integrated circuit element is connected by a melting point metal for airtight sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51032521A JPS6056297B2 (en) | 1976-03-26 | 1976-03-26 | Airtight mounting structure for integrated circuit elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51032521A JPS6056297B2 (en) | 1976-03-26 | 1976-03-26 | Airtight mounting structure for integrated circuit elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52116073A JPS52116073A (en) | 1977-09-29 |
| JPS6056297B2 true JPS6056297B2 (en) | 1985-12-09 |
Family
ID=12361254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51032521A Expired JPS6056297B2 (en) | 1976-03-26 | 1976-03-26 | Airtight mounting structure for integrated circuit elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6056297B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0566591U (en) * | 1992-02-21 | 1993-09-03 | 株式会社精工舎 | Alarm clock with remote control function |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59222948A (en) * | 1983-06-02 | 1984-12-14 | Matsushita Electronics Corp | Semiconductor package |
| JPS61292332A (en) * | 1985-06-19 | 1986-12-23 | Sumitomo Electric Ind Ltd | Semiconductor chip carrier |
-
1976
- 1976-03-26 JP JP51032521A patent/JPS6056297B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0566591U (en) * | 1992-02-21 | 1993-09-03 | 株式会社精工舎 | Alarm clock with remote control function |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52116073A (en) | 1977-09-29 |
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