JPS59222948A - Semiconductor package - Google Patents

Abstract

PURPOSE:To enable to obtain an element, which is tough against mechanical demages, to prevent the characteristics of the element from deterioration due to circumstances and to realize a higher density-mounting by reducing the number of parts to be mounted on a substrate by a method wherein plural pieces of chip parts of different kinds are mounted in the same cavity of the same package. CONSTITUTION:A package has been made into a multilayer structure made of ceramics. In the greent sheet laminating process at the manufacturing time of the package, the substratum is made into such a way that a step difference can be formed in the main surface thereof, namely, the die-attaching surface. In the mounting order of chips, a chip capacitor is mounted first, in view of influences to exert upon the characteristics of a LSI chip. As the package itself is usually heated up to about 400-500 deg.C in the die-bonding process for the LSI chip, a material, which cannot be fused at the above-mentioned temperatures, is desirable as a material for jointing the chip capacitor having been already mounted on the package with the package. On the other hand, in case a recessed part of such a size that the chip capacitor can be exactly accomodated in is formed by providing the step difference at the die-attaching surface, this recessed part does an action to support the chip capacitor itself.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to electronic components called chip components when mounting them in a package.
Pano-cage, a semiconductor package that can be mounted within the same cavity.

Conventional Structures and Problems Conventionally, chip components such as chip resistors and chip capacitors have generally been directly attached to motherboards and printed circuit boards. However, in such a mounting method, the chip components are exposed to the outside world, so they are easily susceptible to mechanical damage, and the characteristics of the elements are also degraded by the environment. Moreover, the increase in the number of 27'-components on the board prevents high-density mounting, and there are problems such as failure of each component caused a decrease in yield at the module level or knee 7) level. .

OBJECTS OF THE INVENTION The present invention provides a semiconductor package that solves the problems seen in the conventional mounting methods as described above.

Structure of the Invention The present invention has a structure in which the main surface of a package base is provided with a stepped surface on which a plurality of chip components can be mounted.
These above-mentioned problems have been resolved. In addition, by providing multiple steps in the die attachment part within the cavity, uneven parts are formed on which each chip is mounted, making it easy to mount the chips.
- It is possible to easily align the chip during the process and make it possible to align the chip to 7 points correctly.

DESCRIPTION OF THE EMBODIMENTS FIG. 1 is a sectional view of an embodiment of the present invention. jd in example
Although it is a D I L type, it can be applied to all packages with cavities such as Chisopki Konria and Binguli Sod array (distance).The package is made of ceramic multi-layer 11η.
It is constructed. A step is formed on the main surface of the base, that is, the die attach surface, in the green sheet top layer process during package manufacturing. FIG. 2 shows a case where an LSI chip and a chip capacitor are mounted on the main surface of the package bonded in the embodiment shown in FIG. The chip mounting order is LS
The chip capacitor is mounted first, considering the effect on the characteristics of the I-chip. Normally, in the die bonding process for LSI chips, the package itself is
Since it is heated to 0'C, it is preferable to bond the chip capacitor and package already mounted on the tower to a phase bond that will not melt at this temperature. However, here, due to the step difference on the die attach surface, a recess is formed in which the chip capacitor can be accommodated, and these four parts serve to support the chip capacitor itself. For example, if you use a low-melting-point solder such as Pb-3n solder to bond a chip capacitor, there is a risk that the chip capacitor will be misaligned because the solder will melt once when die-bonding the LSI chip, but the four parts will act as supports. There isn't.

Effects of the Invention As described above, according to the present invention, by mounting a plurality of different types of chip components in the same cavity of the same package, it is resistant to mechanical damage and prevents deterioration of the characteristics of the element due to the environment. Enables high-density mounting by reducing the number of components on the board. Furthermore, by providing a step in the die attachment of the cavity, alignment of chip components during the mounting process is made easier and more accurate.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of the embodiment of FIG. 1 with an LSI chip and a chip capacitor mounted thereon. 1...First diamond attachment, 2...Second
Dia attachment, 3...Outer lead pin, 4...Ceramic sheet, 6...LSI
Chip, 6...Chip capacitor.

Claims (1)

[Claims] A semiconductor pantage having a stepped surface on the main surface of a package base on which a plurality of chip parts can be individually mounted.