JPS6055734A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To make the correction of errors up to triple errors possible by allowing a double correcting circuit to perform the triple error correction processing in accordance with the decision output of a triple error in an error correcting circuit of crossinterleave double correction code. CONSTITUTION:Symbols outputted from a deinterleaving circuit 15 are led to a syndrome generating circuit 17 to generate a syndrome. An error flag outputted from the deinterleaving circuit 15 is led to a latch circuit 18, and the error location of the symbol to which the error flag is added is latched. This location and the syndrome are led to a triple error deciding circuit 19 to decide that each error location of the triple error is correct, and double correcting circuit 16 is allowed to perform the triple error correction processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in an error correction circuit suitable for use in a DAD (digital audio disc) playback device of, for example, a CD (optical continuous disc) system.

(Technical Background of the Invention) Recently, in the field of audio equipment, in order to achieve as high fidelity reproduction as possible, PCM (curse code modulation)
Digital recording and playback methods using technology are being adopted. In other words, this is what is called digital audio, and the audio characteristics do not depend on the characteristics of the recording medium, but are much better than those using conventional analog recording and playback methods. This is because it is established in principle.

In this case, a system that uses a disk as a recording medium is called a DAD system, and optical, capacitive, and mechanical recording and reproducing methods have been proposed. However, no matter which method is adopted, the playback device that embodies it must be able to satisfy various advanced control functions and performance that are not found in conventional devices. has been done.

In other words, if we take the CD system as an example,
The CLV (Constant Linear Velocity) method is a disk made of a transparent resin disk with a diameter of 12 [(B) and a thickness of 1.2 Cmm] coated with a metal thin film that forms pits (unevenness) compatible with digital (PCM). approximately 500-200 (r, p, m
, ) is rotated at a variable rotational speed, and reproduced by an optical pickup containing a semiconductor laser and a photoelectric conversion element in a linear tracking manner from the inner circumferential side to the outer circumferential side. The pitch is 1.6 [μm], and the program area (radius 2
5 to 58 Cmm), and their index data etc. are recorded in the lead-in area (radius 23 cm).
This can be easily seen from the fact that it is included in ~25 [lnm1].

By the way, in the above-mentioned AD system, when recording digitized data on a disk, it is possible to easily generate a bit synchronization signal during playback, and the RF multiplier read by an optical pickup is In order to perform stable data slicing with narrow band signal frequency characteristics, digitized data is modulated into data whose polarity reversal interval is always within the specified maximum and minimum polarity reversal intervals. I am trying to record it on a disc. As this modulation method, optical CD
In the case of a system CAD playback device, E, FM (eight-to-fourteen modulation) modulation is generally used. This EFM modulation divides digitized data into 8-bit units and records it on a disc in 14-bit data in f-key.
The pit data is demodulated into the original 8-pit digitized data and reproduced.

Then, the 8-bit digitized data formed by the 14-pit data *tsm reproduced from the disk as described above is led to a correction circuit and subjected to error correction processing.

Here, especially for optical CD type DAr) playback devices, cross ear is used as the error correction code.1-17-
A Breed-Solomon code (c-Rc) is adopted. In other words, this uses a Reed-Solomon code, which is a type of BCH code that is widely defined as having the highest error correction ability among typical random error correction codes known in the past. However, in order to have a high correction ability even for burst errors, signal processing called cross interleaving is added.

Incidentally, decoding, that is, error correction, of the Reed-Solomon code can be performed in the same manner as that of the BCH code. now,
For example, let us examine the decoding method for a Reed-Solomon code consisting of a code length (n), information symbols (k), and check symbols (n - IC). However, each of the above symbols is an element of the Galois field G F (2m), which is a finite field having (→ binary pits, that is, 2m elements).

In this case, the generating polynomial H(X) of the double error correcting Reed-Solomon code is the Hwogalois field G
) is expressed as the following 0 expression or 0 expression.

H(,3= (,+α)(x+α”) ・−−−−−(
X ten α! j;) ,・■H(X)=(X+α0)(x
+α＞ −−−−−−<, 1α*t−1),... ■Still, the recording signal polynomial is expressed as ty ('') s the reproduced signal polynomial t−V (X), and the error polynomial is expressed as E ( x
), the following relationship holds between them.

V (x) = U (x) + E (x) ...
・・・・・・・・・・・・・・・・・・・・・ ■In this case, the coefficients of the polynomial are included in the Galois field GF(2m), and the error polynomial E(x) is It contains only terms corresponding to location and value (size). Therefore, the error/
Error pattern e (y
j), then E(x)== f Y jX j ・・・・・・・・・
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .

Here, the syndrome (Sl) is f3i=V(α) ・・・・・・・・・・・・・・・
・・・・・・・・・・・・ ■(However, i=0.1...
..., zt-1), the above 0
From the formula, 5i=U(α')+g(α1). In this case, U(x) is evenly divisible by H(x), so U(α1)=0 S i = E (α1). Therefore, from the above equation 0, 8i=E(α1)=ΣYj(α1)j=fYjX1...
... It can be expressed as ■. However, αi ==
X j , where Xj represents the error location at α1.

Here, the error location polynomial σ(X) is as follows, where the number of errors is (e): σ(X)=Σ(x-Xi) =X8+σ, Xe-1+...10σ.・・・・・・
・・・・・・・・・・・・ ■Defined as.

Further, σ1 to σθ in the equation (2) are related to the syndrome (Si) as follows.

Bice+σ, Si+e−1+−−−−・σe−
ISi+x+σeBt −■ In other words, the decoding procedure of the Reed-Solomon code as described above is as follows: (1) The syndrome (81) is divided by the formula (1).

(Il) Calculate the coefficients σ1 to σe of the error location polynomial using equation 0.

(1) ■From formula d, the root of the error location −7 Yon polynomial (X
j).

(1'V) Obtain the error pattern (Yj) using the 0 formula, and find the error polynomial using ②2.

(V) Perform error correction using formula 0.

This results in moves 11 of (1) to ('/).

Next, as a specific example 11 of error correction using the above decoding procedure, a case will be described in which one block data vC4 (a fixed check symbol is used. That is, the generating polynomial H(x) in this case is H(x )=(x+1)
(x+α><x+α2) (x+α3), and it is possible to correct up to double errors, which will be explained below.

(1) Calculate 7-ndromes (So) to (S3).

(n) 0 equation as e=1. Rewriting e=2, e
In the case of =1, it becomes. Moreover, in the case of e=2, it becomes.

Here, if we assume that the actual decoder starts operating from the power line when e=t, first, we will first solve the solution (σ1
) must be met. Then, if this solution does not exist, the decoder next uses the system of equations [
We must find solutions (σ1) and (σ2) that satisfy [phase]. Note that if no solution is obtained here, it is assumed that e≧3.

(2) The solution σ1 of the equation is determined, and the solution M(σ1) and (σ2) of the QΦ equation are determined.

l) Once the coefficients (σi) of the error location polynomial have been obtained as described above, next find the roots of the error location polynomial using equation (2). First, if e=1, σ(χ ) = x + σI = Ot,'
, we can find the solution by sequentially substituting the elements of the Galois field Gg(2nn) into the equation Q), and now let this root be (xt)
, (xt).

(Light) Once the roots of the error location polynomial have been determined, next find the error pattern (Yj) using the 0 formula.

First, in the case of e; 1, So=　Yl　,’-Yl　”　8゜ becomes. Also, in the case of e=2, s0=y, +y.

St: y, x, 10y, X.

Therefore, Y 2 ”: 86 + Y t ■) Error pattern (ys) created as above
, (yt).

FIG. 1 is a block diagram showing a conventional error correction circuit which is an actual decoding system for a cross-interleaved Reed-Solomon code based on the above principle. That is, reference numeral 11 denotes a pickup, which reproduces a disk (not shown) and outputs an RF multiplied signal. This RF multiplied signal,
After being converted into digitized data by a data slice circuit (not shown), the data is subjected to self-clock synchronization signal extraction and supplied to the demodulation circuit 12. Here, as described above, this demodulation circuit 12 performs a BFM demodulation operation to convert 14-bit data recorded on the disk into 8-bit data, and sends the demodulated symbols to the error correction means I.
3.

This error correction means 13 includes a double correction circuit 14
, a cross-interleave double correction system consisting of a dinterleave circuit 15 and a double correction circuit 16. As is well known, the double correction circuit 14 judges the error of the demodulated symbol, and if the error can be corrected, the error is corrected as described above, and the error is corrected via the dinterleave circuit 15 and the double correction circuit 16. If the error correction capacity is exceeded, the error flag (Ef") indicating the error location is added to the demodulated symbol and output to the dinterleave circuit 15. , an error flag (gr) is applied, and the double correction circuit 16 performs error correction by performing dinterleave processing.

[Problems with background technology]

However, the conventional error correction circuit as described above still cannot be said to have sufficient error correction ability, and there remains room for various improvements. In other words, although the double correction circuits 14 and 16 are theoretically capable of correcting up to quadruple errors, they are designed to only perform double error correction in consideration of the reliability of the error location. be.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and by reliably determining whether each error location of a triple error is correct, it is possible to substantially correct up to triple errors, and especially burst errors. It is an object of the present invention to provide an extremely good error correction circuit that is effective for.

[Summary of the invention]

That is, the present invention uses an error location polynomial based on a double correction BCH code in the Galois field GF(zm) to generate error locations and error patterns necessary for error correction, and generates an error flag when the error correction capacity is exceeded. 1 double correction circuit and this first 2
a dinterleave circuit for the symbols and error flags output from the double correction circuit; and a second circuit that performs double error correction processing for the symbols output from the dinterleave circuit based on the second flag. Double correction circuit and fully equipped cross-interleaved double correction BCH
The error correction circuit of code ' includes a syndrome generation circuit that generates a syndrome based on the symbol output from the dinterleave circuit, and an error location indicated by an error flag output from the dinterleave circuit and the syndrome. and a triple error determination circuit that performs triple error determination based on the triple error determination circuit.
The present invention is characterized in that the double error correction circuit is caused to perform triple error correction processing in response to the determination output of the multiple error determination circuit.

[Implementation sequence of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 2, the same parts as in FIG. 1 are indicated by the same symbols, and only the different parts will be explained here. That is, the symbols output from the dinterleaving circuit dg15 are guided to the syndrome generation circuit 17, and syndromes (so) to (ss
) is generated. Additionally, the error flag (rv r') output from the dinterleave circuit 15 is transferred to the latch circuit 1.
8 and latches the error location of the symbol to which the error flag (Er) is attached.

Soshite, this error location and syndrome (SO
) to (S8) are led to the triple error determination circuit 19, and 3
It is determined that each error location of the double error is correct, and the double correction circuit 16 is caused to perform triple error correction processing.

Here, the triple error determination circuit 19 will be explained. Now, let the first root of the modulus polynomial over the Galois field GF(2') be (b), and the generator polynomial H(x) be H(x) = (x
+1 ) (x+α) (X+α ri (X+α3).

Then, the number of symbols in the correction block (the number of symbols is 32, the recording side polynomial U (x) is, U(x) = Ull X" + U3゜X"10."
UI X+U(.

If it is expressed as When an error occurs, the above formula is not satisfied, and in the case of a triple error, let the error location be (αa), (αb), (α0) and the error pattern be (ea)e(lilb)e(eo). , syndromes (so) to (S,) are as follows.The known data in the above equation is % (8G)? (81).

(St)-(Sa)e(αs, (αb), (α0), so if (ea), (θb), (eo) are removed, we get
s3+(a"tenα"+a')s, ten(α"a"4-a"
α'+α0aa)S, +αααB, :O・Song...song...same song... [phase]. When this [phase] equation is satisfied, it can be reliably determined that there is a triple error. That is, the triple error determination circuit 19 detects the syndrome (So) output from the syndrome generation circuit 17.
~(S,) and the error locations (αa) to (αo) latched by the latch circuit 18, the above-mentioned [phase] equation is calculated to determine a triple error.

Then, when it is determined that there is a triple error, the double correction circuit 1
6 trusts the above error locations (αa) to (α0) and the error location to which the multiple error flag (gr) is added as correct, finds the error pattern (ea) to (eo) using the above @ formula, and performs triple It performs error correction.

Therefore, according to the configuration of the above embodiment, the triple error determination circuit 19 performs the calculation shown in equation 0, determines that there is no error in the error location and that a triple error has occurred, and then performs the double error determination circuit 19. Since the correction circuit 16 is configured to perform triple error correction processing, error correction can be performed correctly, and is particularly effective against burst errors.

Here, FIG. 3 shows a concrete array of the triple error correction circuit 19. In FIG. 3, a memory 20 stores the syndromes (8°) to (S,) output from the syndrome generating circuit 17. In the figure, 21 is a decoder, 22 is an arithmetic circuit, 23 is an accumulator, 24 is a selector circuit, 25 #26 is a register, and 27 is an O detection circuit, which are stored in a read-only memory (hereinafter referred to as ROM) 28. The program is operated as follows.

(1) First, the error location (
α0) is output to the pass line (A), and outputted from the memory 20 to the syndrome (So) all pass lines (B).
The calculation circuit 22 performs the calculation αOx so and stores the result in the accumulator 23.

(2) Next, the contents of the accumulator 23 are outputted to the pass line (A) via the selector circuit 24 and stored in the memory 20.
Syndrome (S+) is output to the pass line (B), and (Ace)+61+ However, (Ace) is the calculation of the contents of the accumulator 23, that is, α0B6 + S 1f is generated and stored in the -C accumulator 23.

(3) Next, (Acc) is outputted to the path line (A) via the selector circuit 24, and the error location (αb) is outputted from the latch circuit 18 to all path lines (s)K, and (Ace))< An operation α, that is, αb(α0so+s, ) is generated and stored in the register 25.

(4) Next, the error location (
α0) output to all pass lines (A), output from memory 20 to syndrome (S+) V pass line (B), α
'XS, fr,' are performed and the results are stored in the accumulator 23.

(5) Next (Ace), that is, α0×S! the path line (
A) and output the syndrome (sz) from memory 20.
f: Output to the pass line (B) to generate the calculation (Acc)+82, that is, αo S H+82, and store it in the accumulator 23 and register 26, respectively.

(6) Next, output (Acc)'i to the pass line (A), output the contents of the register 25 (hereinafter referred to as (R1)) to the pass line (B), and (Ace) + (R1 ), that is, generate αb(α0So×SI)+α's1+s2,
It is stored in the accumulator 23.

(Next, output to (Ace) (H pass line (A),
From the latch circuit 18 to the error location ((1')'e
It outputs to the pass line (B) to generate the calculation (Ace) xα0, that is, α0(αb(α0so+s, )+α0s, +s2), and stores it in the register 25.

(8) Next, the contents of the register 26 (hereinafter referred to as (R2)) are output to the pass line (70), and outputted from the latch circuit 18 to the error location (αb) and all pass lines (B), (R2) x α5 The calculation α(αS1+8.) is generated and stored in the accumulator 23.

(9) Next, output (AcC) to the pass line (A),
(R1) is output to the pass line (B), and the calculation becomes (Acc) + (R1), that is, α0(αb(α0s, +s,)+α's, +s2)+α
b(α0s, +s2) is generated and stored in the register 25.

[Stocks] Next, from memory 20 syndrome (82) *
The error location (α0) is outputted to the pass line (A) from the latch circuit 18 to the pass line (B) K, and the calculation S2Xα0 is performed and stored in the accumulator 23.

+il1st K, (Acc) is output to the pass line (A) K, and the syndrome (S3) from Memo 1) 20 is output to the pass line (B) to generate (Acc) + 8°, that is, S2α0+83. , stored in the accumulator 23.

(I insult) Next, output (Acc) to the pass line (A) and %
, (R1) is output to the pass line (B) and the calculation becomes (Acc) + (R1), that is, α0 (αb (α080 + SI) + α'S, +S,) + α
b(α'S, +8.)+s2α0+83 is generated and stored in the accumulator 23, thereby obtaining top-distribution plastic forming.

t13 Next, it is output to the pass line (C) via the (Ace)l selector circuit 24, and the 0 detection circuit 27 makes a complete determination as to whether or not it is O, thereby making a triple error determination here. It is.

Here, erroneously determining a quadruple error as a triple error will be explained. The error location of the quadruple error is (α
1), (αj), (αji.

(αL), error pattern/(e 1') + (ej
') , (ek') + (ez'), and now suppose that the position of (α) is misjudged and the error flag (Kf) is not set. Then, this becomes '+e)/+e i == e
t+e j +ekS,=ei'αi +e j/α
j+ e IC'α +et'(t' = e1α1l-
ejα'+a l "S,,=e1'α"1+ej'
α2j+el'α2+et'C1" =+ eiα"
+ejα2j+ekα2kS, = e i'α31 ten eJ/α3j+e1/α3 tene t'α3L; e1α
31+ejα3j+ekα3, and from the above equation, Since it has been proven that the 0 equation is never satisfied in the double correction BCH code, the 0 equation is naturally never satisfied.

Therefore, there is no possibility that a quadruple error is mistakenly determined as a triple error #41.

It should be noted that the present invention is not limited to the above embodiments, and can be implemented with various modifications within the range of ml without departing from the gist thereof.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, since it is reliably determined that each error location of a triple error is correct, it is possible to substantially correct up to a triple error. , it is possible to provide a good error correction circuit for the first time, which is particularly effective against burst errors.

[Brief explanation of the drawing]

Figure 1 shows a conventional cross inter 1〕-゛IJ-)'
Block II showing a Solomon code error correction circuit!
2 is a block diagram showing an embodiment of the error correction circuit according to the present invention, and FIG. 3 is a block diagram showing details of the main parts of the same embodiment. 11...Pickup, 12...Demodulation circuit, 13.
... Error correction means, 14 ... 2 companies, 3 models (circuit, 1
5... Dinterleave circuit, 16... Double correction circuit, 17... Syndrome generation circuit, 1B... Latch circuit, 19... Triple error determination circuit, 20... Memo IJ, 21... Decoder, 22... Arithmetic circuit, 2
3... Accumulator, 24... Selector circuit,
zfx26...Register, 27...0 detection circuit, 2
8...ROMo

Claims (1)

[Claims] The first method generates error locations and error patterns necessary for error correction using an error location polynomial based on a double correction BC'H code in Ay (2m), and generates an error flag when the error correction capacity is exceeded.
a dinterleave circuit that performs dinterleave processing on the symbol and error flag output from the first double correction circuit; and a dinterleave circuit that performs dinterleave processing on the symbol and error flag output from the first double correction circuit; and a second double correction circuit that performs double error correction processing based on the error flag. a syndrome generation circuit that generates a syndrome based on the dinterleave circuit; and a triple error determination circuit that performs triple error 4QJ determination based on the syndrome and the error location indicated by the error flag output from the dinterleave circuit. ;
The error blind system is characterized in that the 811% double correction circuit performs triple error correction processing in accordance with the determination output of the 111% triple error determination circuit.
Positive circuit.