JPS6055733A - Error correcting circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution and to ensure the error decision by deciding as an error location when the output of a signal processing means attains to ''0'' in an error correcting circuit which generates the error location and an error pattern. CONSTITUTION:A syndrome Si is generated on a basis of coded words of double correction BCH code in a Galois field FG(2<m>), and operations are performed on a basis of this syndrome Si. As the result, an element alpha<i> of the galois field GF(2<m>) is decided as the error location when the output of the signal processing means goes to ''0''. Consequently, whether a double error or a triple or more multiple error occurs and whether a single error or a triple or more multiple error occurs is judged.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention, for example, a CD (optical compact disc)
The present invention relates to an improvement in an error correction circuit suitable for use in a digital audio disc (DAD) playback device.

[Technical background of the invention]

Recently, in the field of audio equipment, a digital recording and reproducing method using PCM (pulse code modulation) technology is being adopted in order to achieve high fidelity reproduction as much as possible.

In other words, this is what is called digital audio, and the audio characteristics do not depend on the characteristics of the recording medium and are much superior to those using conventional analog recording and playback methods. This is because it is established in principle.

In this case, the system that targets a disk (disk) as the recording medium is called the UDAD system, and the recording and reproducing methods have been proposed such as optical, capacitive, and mechanical. Regardless of which method is adopted, the playback device that embodies it must be able to satisfy various advanced control functions and performance that are not found in conventional devices. There is.

In other words, if we take the CD system as an example,
CL is a disc made by covering a transparent resin disc with a diameter of 12cI1m) and a thickness of 1.2CIun with a metal thin film that forms pits (irregularities) compatible with digital (PCM).
Approximately 500 to 200 Cr by V (constant linear velocity) method,
p, m, ) is rotated at a variable rotational speed, and is reproduced in a linear tracking manner from the inner circumference side to the outer circumference side using an optical pickup containing a semiconductor laser and a photoelectric conversion element. The disc has a track pitch of 1.6 [μm], and a huge amount of information that can be played in stereo for about an hour on one side is recorded in the program area (radius 25 to 58 [-]). Index data etc. are in the lead-in area (
This can be easily seen from the fact that it is recorded in a radius of 23 to 25 [home].

By the way, there is an AD system as mentioned above.

When recording digitized data on a disc,
In order to easily generate a bit synchronization signal during playback, and to perform stable demess2s as a narrow band of RF multiplied signal frequency characteristics read by an optical pickup, The digitized data is modulated into data whose polarity inversion interval is within the specified maximum and minimum polarity inversion intervals, and is recorded on the disk. And, as this modulation method,
In the case of optical CD type DAD playback devices, EFM (eight-to-fourteen modulation) modulation is generally used. This EFM modulation divides digitized data into 8-bit units and modulates the data into 14-bit data for recording on a disc. During playback, the 14-bit data is converted into 8-bit original digitized data. It is designed to demodulate and play it back.

Then, the 8-pit digitized data obtained by demodulating the 14-pit data reproduced from the disk as described above is led to a correction circuit and subjected to step 2 - correction processing.

Here, especially in an optical CD type DAD reproducing apparatus, a cross-interleaved Reed-Solomon code (CIRC) is adopted as an error correction code. In other words, this uses a Reed-Solomon code, which is a type of 6BCH code and is widely defined as having the highest level of correction capability among typical random error correction codes known in the past. , and is accompanied by cross-interleaving signal processing in order to have a high correction ability even for burst errors.

By the way, decoding of Reed-Solomon code - 1) Error correction can be performed in the same way as that of BCH code. For example, let's examine the decoding method for a Reed-Solomon code consisting of code length (n), information symbols (k), and check symbols (n-k).However, the valley symbol above is (to) This is a redundancy of the Galois field GF(2), which is a finite field having 2 binary bits, that is, 2 7C.

In this case, let be the generator polynomial H(2) of the double error correcting Reed-Solomon code, and (α) be the Galois field CF(2).
The primitive light of is expressed as the following equation 0 or equation 0.

H(x) = CX ten α) (x+d”)・(x-1-
α2t) −・−−■H(x)=(x+α0)(X+α
) − ( The following relationship holds true.

v (x) = U (9) 10E (illusion...
■In this case, the coefficients of the polynomial are Galois field G F (2”)
The error polynomial E(x)U contains only the terms corresponding to the error location and value (magnitude). Therefore, if the error pattern temperature (Yj) at the error location (Xj) is E(g)=ヰ゛Yj
...■ and Nashi, in the formula 0, Σ means the summation over all positions of 2-.

If we define the syndrome (St) as (however, i = 0, 1..., 2t-1), then from the above equation 0, 5s = u (α') + E (αi
) becomes. In this case, U) is divisible into wealth by H((trans)), so U(α)=0, so 5i=E(αi).Therefore, according to the above equation 0, it can be expressed as p. However, when α1=Xj, Sx' represents the error location at αi.

Here, the error location polynomial σ (increases to J, where the number of errors is (e)) -! (X-Xt) =Xe+σ1xe-1+...+σe...River...
■Defined as.

The relationship between mata, ■expression no σ, ~σe扛, and syndrome (Si) is as follows.

Si+6 + σ, Si+e−s 1”’10σe−
tsi−1−+10σ. Si......■ Tsumashi, the above-mentioned Reed-Don-Romon code decoding procedure is as follows: (1) Calculate the 0-formula syndrome (S:).

(It) Coefficients σ, ~σ of the error location polynomial in Equation 0. Calculate.

(#) Roots of the 0 expression Nyokuen-Location polynomial (x
Add l).

■ Insert the Nyota error pattern (Yj) into Equation 0, and insert the Scherrer polynomial into Equation 0.

(7) Perform the 0-type error correction.

This results in steps (1) to (b).

Next, as a specific example of error correction using the above decoding procedure, a case will be described in which four check symbols are used for one block of data.

That is, in this case, the generator polynomial H) is H(x)
= (x+1) (x+a) (x0a”) (x+
c''), and it is possible to correct up to double en-, which will be explained below.

(1) Calculate syndromes (So) to (S3).

(It) Rewriting equation 0 for e=l and e=2 gives -
In the case of e = l, it becomes. Moreover, in the case of e=2, it becomes.

Here, assuming that the actual decoder starts operation from the case where e = 1, first, a solution (σ
). Then, if this solution does not exist, the decoder must next find a solution (σ, ), (σ2) that satisfies the simultaneous equations for the case e = 2. Note that if no solution is obtained here, e≧
It will be considered as 3.

■The solution of the equation (σ,) is given as , and the solution of the [phase] equation is given as (σ,), (σ,)d.

After obtaining the coefficients (σi) of the error location polynomial as described above, next find the root of the Scherrer location polynomial using equation 0.

First, when e=1, σ(2)=X+σl=0++°, X1=σ1. In addition, in the case of e = 2, let σ = Now, let this root be (X+), (Xt
).

(2) If the roots of the 2-location polynomial are fixed, then
Next, enter the error pattern (Yj) into equation 0.

First, if e = l, So = Yr, '-Y I = S.

becomes. If i, e = 2, then So-Ys 10Yt S, = Y, X, 10Y, X2 Yosi, Y, =X・S・+S・ X, +X.

Yv = So Y+ (7) Error pattern (y+) created as above
, (y*) correction is performed.

FIG. 1 is a block diagram showing a conventional error correction circuit which is an actual decoding system for cross-interleaved Reed-Solomon codes based on the above principle. That is, reference numeral 11 denotes a pickup, which reproduces a disk (not shown) and outputs an RF multiplied signal. This RF multiplied signal,
After being converted into digitized data by a data slicing circuit (not shown), the data is subjected to synchronous signal extraction for self-clocking, and then supplied to the demodulation circuit 12. Here, in this demodulation circuit 12, as described above, gF converts the 14-bit data recorded on the disk into 8-bit data.
It performs M demodulation operation and outputs the demodulated symbols to the correction means 13.

The error correction means 131fi, the double correction circuit 14. Dinterleave circuit 15 and double correction circuit 16
This is a cross-interleaved double correction method. In addition, as is well known, the double correction circuit 14 performs error determination on the demodulated symbol, and if the error can be corrected, performs step 2-correction as described above to the dinterleave circuit 15 and the double correction circuit 16. D/ not shown through
If the error correction capacity is exceeded, the error is not corrected and an error 7 lag (Ef) indicating the error location is added to the demodulated symbol and output to the dinterleave circuit 16, and the error 7 is output to the dinterleave circuit 16. Dinterleave processing is performed together with the lag J, and the double correction circuit 16 performs error correction.

[Problems with background technology]

By the way, in the conventional error correction circuit for the double-compensated BCH code as described above, the above-mentioned simultaneous equations (2).

Coefficient ('i) of error location polynomial by [shares]
Determine the number of errors (single error, double error, triple error or more), then determine the error location polynomial according to the number of errors, find its root (error location), and perform the following steps. 2- Error correction is performed based on a pattern. However, the above (σi) is
+As mentioned above, in the case of the 0 formula, it is necessary to perform division, and in the case of the [stock] formula, it is necessary to perform division. Here, as is well known, when configuring a digital data arithmetic circuit, a multiplication circuit can be realized with a simple configuration, but a division circuit has a complicated configuration1. It is strongly desired to be able to easily determine whether the error is a single error, a double error, a triple error or more, with a simple configuration.

[Purpose of the invention]

The present invention was made based on the above-mentioned circumstances, and an object of the present invention is to provide an extremely good error correction circuit that can perform reliable error determination with a simple configuration.

[Summary of the invention]

That is, this invention provides 2 in the Galois field GF(2)
2. In the correction circuit, a syndrome (St) (iU correct a syndrome generating means for generating a syndrome (an integer of Based on the syndrome (Sl) generated by rs = StSo + Str! = Sl B6 + S, Slr I=SsS
t + Sg and the output of this operation + stage (r
=) = Crt), the third holding means that holds (r3) out of (rl), and the output (r
s ) = (rt) , (rs) (D out of ra
A determination means for determining whether 'e07>rs=0 or not, and r3 lol O is determined by this determination means! 1. The above (r, ) is applied to the first and second holding means in place of the above (st) and (So).

(r,), and a control means for holding sH, respectively.
The content (st)i*U(r,) held in the holding means and the content (so) or (r,) held in the second holding means of the Gaq field GF(2). The value obtained by multiplying by (α') and the nine content (r3) held in the third holding means
and a signal processing means for adding a value obtained by multiplying by (αIf), and the element (ei) when the output of the signal processing means becomes 0 is set as an error location. That is.

Hereinafter, before explaining one embodiment of the present invention, the principle of the determination means in the present invention will be explained. Now, as an example, we will discuss the Galois field GF'(2'). In this case, let the first root of the modulo polynomial be ←),
II(x)=(x+1)(x+α
)(X0α″)CX+α3], the number of symbols in the correction block (to) is 32, and the recording side polynomial U) is U(x) = UHX” + Usox30+ ・・・
+UI X 10U.

Assuming that U(b) is divisible by H(9), as mentioned above, U(1)=U(α)=U(α')=U(α3)−〇. However, if an error occurs on the playback side,
The above equation is no longer satisfied.

In other words, in the case of a single error, if the process is (α) and the error pattern is (ei), then
The syndromes (So) to (S,) are satisfied as follows: 3o=ei S1=elα 32=6i(X' B,=eLα31) The above equation corresponds to the above equation 0. Therefore, Sl + X So ・・・・・・・・・ Substituting (α0) to (α3m) in sequence for the rest of the expression 0,
The point where the value is 0 is the error location.

In addition, in the case of a double error, the error location (
αa), (α) Toshi, Error-Ap-y (ea),
(”b), syndromes (So) to (S3)
Since 5o=ea+eb b S,=eaα+ebα 52=eBα2a+ebα2b s'="a"a+eba3b, is satisfied. The above equation corresponds to the above [phase] equation. Here, if we set B l) ab α + α = A, αα = B, then (α ) and (α ) are the roots of the quadratic equation: x”+Ax+B ・・・・・・・・・・・・◎ It can be expressed as .In addition, the 0 expression can be expressed as pl, where, if we set, the [phase] expression becomes 5. (α) and (α) are the roots of this quadratic expression. because there is,
Naturally, r, x2+r, x + r,...
・It is also the root of 0. Therefore, (α0
) to (α3') are sequentially substituted, and the point where the value becomes 0 becomes the error location.

In other words, in the case of a single error, the formula 0 is (α0)~
A single error is determined by sequentially substituting (α31) and if the 0 expression has one root that becomes 0, and in the case of a double error, sequentially substituting (α0) to (α31) to 0 formula is 0
By having two roots, a double error is determined.

Here, in the case of a single error, from the above formula 0, 1812 + 5
aSo =S: +S+Ss =S+S2+5oss=
0 can be derived, and when correlated with the Hime formula, rs=
It can be seen that r2=r,=Q. On the other hand, in the case of double error, r3 loss is 0, so in the end, r3(0 means double error or triple error or more r, = Ofz
Therefore, it can be determined that there is a single error, a triple error or more.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention based on the above principle will be described in detail with reference to the drawings. Figure 2 shows the above 0
The operation will be described with reference to the flowchart shown in FIG. 3, which is a block diagram showing means for solving equations and [phase] equations.

In other words, 17 in FIG. 2 is an arithmetic processing circuit, and when the operation is started in step ST in FIG. 3, the syndrome is (So)～(S
3) Calculate.

Then, the arithmetic processing circuit 17 calculates the requested syndrome (S
Among O) to (S, ), first 7/drome (So is output to the pass line 19. At this time, the ROM z
The gate circuit 20 controlled by s is the latch circuit 2
A latch signal is output for 1, and the above syndrome (S
l) is latched by the latch circuit 21. Next, the arithmetic processing circuit 17 calculates the requested syndromes (S O) to (S
3) Output the syndrome So to the pass line 19. Then, the gate circuit 20 outputs a latch signal to the latch circuit 22, and the syndrome (So) is latched by the latch circuit 22.

Next, the arithmetic processing circuit 17 determines whether each syndrome (So) to (S,) are all O in step ST3. If all of the syndromes (So) to (S3) are O (YES), the symbol is determined to have no error, that is, to be a correct symbol, and error determination and correction processing is performed via step STa. It will be output as is. t, each syndrome (So) ~ (
ss) If d=not all 0 (NO), arithmetic processing circuit 1
7 is step ST, each syndrome (S o) ~
If it is determined whether any one of (S3) is 0 or not all crabs (No), it is determined that there is an error of 3N or more in step STa.

If YES in step ST, the arithmetic processing circuit 17 determines the syndrome (S) in step 8T.
o) Based on ~(Ss), the above (rs), (r2)
.

(r,) respectively. After that, step ST8
It is determined whether (r,) is 0 or not. This determination is made as follows. First, the arithmetic processing circuit Noah can request (r s), (r 2), (r ,) of (
r3) is output to the pass line 19. And Ko (7)
(r s ) ID output to Hass line 19, RO
The 0 determination circuit 23 controlled by M18 determines whether the value is O or not. At this time, at the same time,
r3 output to the pass line 19 is latched by a latch circuit 24 controlled by the ROM 18. after that,
The arithmetic processing circuit 17 converts (r 2) , (r , ) into I
l[The 14th pass line 19 is moved as shown below.

Here, first, rsNO, that is, step s'r.

The case of (NO) will be explained in 1. As described above, it is determined that there is a double error or triple error or more, so step sT is performed.

Then, an operation is performed to find the roots of the above equation 0.

This calculation is performed as follows. That is, when the 0 determination circuit 23 determines that r340, the gate circuit 20
is driven, and the arithmetic processing circuit 17 outputs (r,), (
r,) is output, the latch circuit 22.
A latch signal is generated for each of 21. Therefore, the latch circuit 22°21 has the syndrome (s
o), (s +), (rJ, (r+)) will be latched, respectively.

Then, each latch circuit 21, 2.2.24 (rυ, (
When r t) and (r s) are latched, Seratoi et al.
-8P) was generated and launched into the latch circuits 21, 22, and 24 (r+) and (r2).

(r,) are collectively the register circuits 25, 26, 27
will be transferred to.

Here, the register circuit 26 has a multiplication clock signal (
W(r2) of the register circuit 26 in accordance with the error location (α) (in this case, α is α0 to
A multiplication circuit 28 is connected to multiply the signal by α31) and set it in the register circuit 26 again. The register circuit 22 also receives the multiplication clock signal (r-CK
) to multiply the contents (r3) of the register 1 white path 27 by α2 and set it in the register circuit 27 again.
A multiplication circuit 29 is connected. And the above Ca')
~(Register times Di(125, 26
The output of the adder 31 is incremented by the adder 30, and the result of the increment is added to the output of the register circuit 27 by the adder 3]. r, (
α') 10r'.

rs=(a’)2+rt(”) 10r.

r3(α”)2+r2(a”)+r.

This is the result of sequentially performing the following calculations, and the result of the calculation is 0. :, ←) are the roots of the 0 formula, that is, the error locations (α') and (αj), so a pick-up is performed to insert the root of the 0 formula here.

Next, when the calculation for finding the root of the equation (2) is performed as described above, it is determined in step 5T1o whether or not two roots have been found. This determination is made based on whether the output of the adder 3 is passed to the 0 determination circuit 32 and it is determined that it has become 0 twice. And if 2 roots are found (YES),
If it is determined in step 5T11 that there is a double error and the double root was not found (NO), it is determined in step s'ra that there is a triple error or more.

Also, with r3 = 0 j9 steps S 'l' a (YE
The case of S) will be explained. In this case, as described above, since it is determined that the error is one ri error or triple error or more, the 0 determination circuit 23 first performs step s'rtt
Determine whether r2 is 0 or not, r2'eO (NO)
In this case, it is determined in step ST6 that there is a 3-salt error or more, and r
, = 0 (YES), in step ST, an operation is performed to find the roots of the 0 equation. This calculation is performed as follows. That is, when the 0 determination circuit 23 determines that r3=0, it does not drive the gate circuit 20. Therefore, the arithmetic processing circuit 17 outputs (r,
), (r,) are not latched by the latch circuits 21, 22, and the contents of the latch circuits 2J, 22 remain as the syndromes (S+), (So).

and the contents of the latch circuits 21 and 22 (St).

(S o ) −tz is transferred to the register circuit is, ze as described above, and the contents of the register circuit 26 (S,
) is multiplied by the error location (α). Note that the content (r3) of the latch circuit 24 is transferred to the register circuit 27 and multiplied by α2, but in this case r3
= 0, the output of the register circuit 27 is 0. Therefore, the output of adder 3 is the result of sequentially performing the following operations: St+8゜(α0) S, +S, (α') Ss +So(α3'), so the result of the operation is 0, fc(α) is the root of the 0 expression, that is, an operation is performed to locate the error.

When the calculation for finding the root of the 0 equation is performed in this way, it is determined in steps s'r, . . . whether or not one root has been found. This determination is made based on whether or not the 0 determination circuit 32 determines that the value has become 0 once. If one root has been found (YES), a single error is determined in step 5T1s, and if one root has not been found (NO), step ST is performed.

It is determined that there is a triple error or more.

Here, FIGS. 4 and 5 show r8=O and r
4(a) from the arithmetic processing circuit 17 in the case of r,=Q.
When (So) to (Ss) are output at the timing shown in FIG. 4(b), the latch circuit 22 outputs (
The two-touch circuit 2 latches (Sl) at the timing shown in FIG. 4(0).

Next, when (r3) to (r, ) are outputted from the arithmetic processing circuit 17 at the timing shown in FIG. (P, ) is output to put the gate circuit 2Q into a non-drive state, and the later generated < rt) + (rl) is the latch circuit 22.2.
Prevent it from being latched to 1.

Also, at this time, ROM J 8 outputs a latch signal to the latch circuit 24 at the timing shown in FIG. 4(e), and the latch circuit 24 outputs a latch signal to r8=0 at the timing shown in FIG. 4(f).
Latch. Thereafter, if r=0, the 0 determination circuit 23 outputs the r2=00 determination pulse (P2) at the timing shown in FIG. 4(d).

When all the latch operations of the latch circuits El and 22 and 24 are completed and r is determined to be 0, a set signal (r-8P) is output at the timing shown in ) in FIG. This allows an operation to find the root of an expression.

Moreover, in the case of r8NO, from the arithmetic processing circuit 17! Figure 5 (
When (So) to (Ss) are output at the timing shown in a), the latch circuit 22 doubles (So) at the timing shown in FIG. )
Double check (S,) at the timing shown by K1, then,
When (r, ) to (rl) are output from the arithmetic processing circuit 17 at the timing shown in FIG. 5(a), first, since rs'=0, the 0 determination circuit 23 outputs the output as shown in FIG. 5(d). As shown, the determination pulse (pt)t; with r8=0 is not output, the gate circuit 20 is put into the driving state, and the determination pulse (pt)t; is generated later.
r2), (r,) are latched by the latch circuits 22 and 21. Also, at this time, ROM 1
g is the latch circuit 24 at the timing shown in FIG. 5 (6).
The latch circuit 24 outputs a latch signal as shown in FIG. 5(f).
(r3) is latched at the timing shown in FIG.
At the timing shown in Q), (So) = (S
t) Latch (r[), (rt) instead of VC.

Then, when all the latch operations of the latch circuits 21, 22, and 24 are completed, a set signal (r-8P) is output at the timing shown in FIG. will be carried out.

Therefore, according to the configuration of the above embodiment, the following calculation is performed, and when rs''EO, r3x2+r, x0r are calculated. , =0, and if two roots are found, it is determined to be a double error and the two roots are set as the error location (αSr(αj)), and if two roots are not found, it is determined to be 3 heavy engineering 2- or more. , when r3=0, find the root of s10XSo=Q with r2=0, and if one root is found, it is determined that there is a one-lin error, and that one root is set as the error location (αi), and rt'i'0
If the root of 1 or 1 cannot be found, it is judged as 3 heavy industrial 2- or more, so it is possible to judge between 1 error and 2xL error by only multiplication and addition, instead of dividing as before. There is no need to carry out this process, the circuit configuration can be simplified, and as a result, reliable error determination can be performed.

In addition, in the case of double heavy engineering 2-, the error location (αi) is obtained by adding the error location polynomial to equation 0.

Since (αj) is chosen, there is no need to perform division here either, and it is possible to simplify one circuit configuration. Regarding this point, conventionally, as mentioned earlier, 0
The formula is: X+σ, X10.

is the error location polynomial, so the coefficient (σ
I), which raises the problem that a division circuit is required to calculate σ.

Furthermore, if the syndrome (St)p(So)Yrl =Q, which is double-checked in the latch circuits 21 and 22, is latched as is and the calculation of the 0 formula is performed, and if rsNO is (Sr)
, (SO) by latching (rθ, (r,) and [
The latch circuits 21 and 22 and the register circuits 25 and 26 are calculated by calculating the error location of the first heavy worker 2- and the double error worker 2-location.
, the multiplier circuit 28, the adder 30, etc. can be used in common, so that the circuit configuration can be simplified and the processing time can be shortened in this respect as well.

Then, as mentioned above, the syndromes (s+) and (so) that are doubled in the latch circuits 21 and 22 are set to r3=0
Then, latch that t and perform the operation of the 0 expression, and rs
'eO, instead of (s,), (sz), (rI), (r
By latching s) and performing the calculation of the 0 expression, the latch circuit 21,
22, the register circuits 25 and 26, the multiplication circuit 28, the adder 30, etc. can be used in common, which is a feature of the present invention.

In addition, after finding the roots of formula 0 with Stella 7'BT and In, it is determined in step 5T14 whether or not 1 root has been found, and if the 1 type is waterlogged, it is determined as a 1 error, and 1 root has not been found. If there is no error, it is determined that the number is 3 or higher, so that it is possible to prevent a false determination of a 1M error with a high probability. In other words, if it is erroneously determined to be a single error even though there is a quadruple error or more, rs:rt=0
This is because sometimes it is impossible to find the root. For this reason, for example, if the number of symbols (N) in the correction block is 32 and the Galois field GF(2), the probability that a quadruple error or more will be incorrectly determined as a single error and 1 root 2 will be found is /s = 1/ 8, and step ST
, 4, it is possible to prevent a quadruple error or more from being mistakenly determined as a single error with a probability of 1/8.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[The young fruits of invention]

Therefore, as described in detail above, according to the present invention, it is possible to perform reliable error determination with a simple configuration.
An extremely good error correction circuit can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional error correction circuit.
FIG. 2 is a block diagram showing an embodiment of the error correction circuit according to the present invention, and FIGS. 3 to 5 are a flowchart and timing diagram for explaining the operation of the embodiment, respectively. Pickup, 12... Demodulation circuit, 13.
...Error correction means, 14...2M correction circuit, 15.
...Dinterleave circuit, 16...2 blood correction circuit,
12... Arithmetic processing circuit, 18... ROM, J! 9・
...Pass line, 20...Gate circuit, 21.22.
...Latch circuit, 23...O determination circuit, 24...Latch circuit, 25 to 27...Register circuit, 2B, 2
9゛°°multiplication circuit, 30.31... adder, 32...
・0 judgment circuit.

Claims (1)

[Scope of Claims] An error correction circuit which generates an error location and an error pattern suitable for error correction using an error location polynomial based on a code word of a double-corrected BCH code in a Galois field GF(+). Syndrome generating means for generating syndrome (Si) (i is a positive integer) from a code word, and among the syndromes (St) output from this syndrome generating means, (Sl ), (
first and second holding means respectively holding so);
The syndrome generated by the syndrome generating means (
SS) VC, based on r3 = 81So + 8”1 r= =s, sO+Stew r1=SsSI + S:
3), a third holding means for holding (r, ) among (r= ), (r,), and an output (r=), (r
l) -(rt), a determining means for determining whether r, ('Q or r8=0); Said (st)
, (so), a control means for holding the above (rl) and (r, ), respectively, and a control means for holding the contents (sl) or (rl) held in the first holding means and the second holding means. The value obtained by multiplying the retained content (so) or (, rt) by the element (α) of the Galois field GF (2m) and the content (r,) retained in the third retaining means are (α!1 ), the element (αi) when the output of the signal processing means becomes 0;
An error correction circuit characterized in that the error location is set as the error location.