JPS6055727A - Ecl integrated circuit - Google Patents

Abstract

PURPOSE:To maximize power consumption by adding a transistor TR to each gate circuit in an ECL integrated circuit to set all outputs of the ECL integrated circuit to a uniform state of a high logical level. CONSTITUTION:In the ECL integrated circuit consisting of plural current switching gates due to emitter coupling, a TR15 is added which has the emitter connected to the emitter common part of gate TRs 12 and 13 and has the collector connected to the ground. A reference potential which is a middle potential between the high level and the low level is applied to a terminal 5, and a negative power VEE is applied to a terminal 7. When a control input terminal 10 is set to the GND potential, TRs 12, 13, and 14 are all cut off, and a high-potential logical level H appears in terminals 3 and 4 in any combination of logical levels H and L applied to input terminals 1 and 2. In this case, the power consumed by emitter followers 8 and 16 is larger than that in the case where the logical level L appears in terminals 3 and 4. When the terminal 10 is set to the VEE potential, the TR15 is cut off, and the ECL circuit is operated normally.

Description

[Detailed Description of the Invention] The present invention relates to a BCL multiplication circuit used for information processing temporary storage. It provides all the functions of making the logic states of the gates the same and allowing the integrated circuit to consume maximum power.

In the non-invention, each emitter inside the FJCL monomer circuit.

At least one new transistor is connected to the joint gate circuit part, with the common emitter part connected to the emitter, and the collector connected to the ground part.

By making the output logic level of the valley gate circuit sufficiently higher than the high potential logic level of the binary input/output logic level of the data coupling gate circuit and making the output logic level of the valley gate circuit the human logic level, the ECL integrated circuit The integrated circuit can perform normal logical operations.

In the Ee1 circuit, connect a new transistor with the emitter connected to the emitter-coupled part and the collector connected to the ground, and make its base potential sufficiently higher than the high potential level of the binary input/output logic level of the 2HCL circuit! D,E
All the transistors in the CLu path and the transistors based on the reference potential are turned off, and all output logic levels in the ECLu path are at a high potential.

Fig. 1 shows an embodiment of the present invention'f, a two-man powered ECL gate circuit. Terminals 1 and 2 are the input terminals of this gate circuit, and terminals 3 and 4.
is an output terminal, terminal 5 is a reference potential input terminal, 6 is a constant current source, and terminal 7 is a power supply input terminal.If the higher potential of the input/output curl logic level of this ECLu path is the H1 lower potential = iL. , a potential intermediate between H and L is applied as a reference potential to terminal 5, and a negative power source is applied to terminal 7. FIG. 2 shows the relationship between these levels and FIG. 3 shows the truth value relationship of human output.

The part 11 in Figure 1 is a newly added part that is not clear. By setting the control input terminal 1 (1% (JND) potential, all transistors 12, 13, and 14 are turned off. , for any combination of human logic levels H, L applied to input terminals 1.2, output terminals 3, 4.
A high potential logic level U appears at. Moreover, when the control input terminal 10t-IE potential is set, the transistor 15 is cut off and this ECLu path operates normally. In FIG. 1, when a high potential logic level H appears at the output terminal 3.4, The power consumed by the emitter follower 8.16 is greater than if a low potential logic level L were present at the output terminal 3.4.

FIG. 4 shows an ECI and gate circuit in which terminals 18 and 19 are input terminals, terminal 20 is an output terminal, terminal 21 is a reference potential input terminal, terminal 22 is a control input terminal, and terminal 23 is a power input terminal. Here, the ECL gate circuit 't-
The terminals 1.2.3.4. of FIG. 1 are represented as shown in FIG.
10' to terminals 23, 24゜25.26.27 in Figure 5
, and the ECL gate circuit jI! of FIG. All 6th
Terminals 18, 19, 20.2 in FIG.
1 Correspond to terminals 28°29.30.31 in Figure 6. In FIGS. 5 and 6, the reference potential input terminal and power input are omitted.

FIG. 7 shows a conceptual diagram in which the present invention is applied to the ECL@product circuit using the symbols shown in FIG. 5 and FIG. 6.

Terminals 32, 33, 34, 35, 36.37 are connected to this EC
The input terminals of the L integrated circuit, terminals 38.39° and 40.41 are output terminals, and the terminal 42 is a control input terminal.
All outputs of the gate circuits are at logic level H, consuming the maximum power of this integrated circuit. - Also, control input terminal 1
When set to the VEB potential, this integrated circuit performs normal logic operations. In Fig. 7, the GNL) terminal power input terminal,
The reference potential input terminal is omitted.

As explained above, the invention is achieved by adding the transistor 'k i=J to the valley gate circuit in the ECL integrated circuit. All the outputs inside the ECL integrated circuit are kept in a uniform high logic level state, which has the effect of maximizing and maximizing the overall cost of fi'r.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
A conceptual diagram of the logical level of the circuit diagram shown in Figure 3, No. 1
Figure 4 is a circuit diagram showing another embodiment of the present invention, Figure 5 is a diagram showing Figure 1 with simple symbols. Figure 6 is a simple symbol representation of Figure 4, and Figure 7 is a conceptual diagram of an integrated circuit that implements the invention. 1.2, 18.19.23, 24, 28.29 are ECL
Gate circuit input terminal, 3, 4, 20° 25.26.3
0 is the output terminal of the BCL gate circuit, and 5.21 is the reference potential input terminal of the HCL gate circuit. 7.23 is Eel, the power input terminal of the gate circuit, 10°22.27.31 is Eel, the control input terminal of the gate circuit, 11 is the uninvented part, 8.16 is the emitter follower, 9
．． 17 is the emitter low flow. 32.33, 34, 35, 36.37 are input terminals of the EeL integrated circuit, 38, 39, 40.41 are output terminals of the ECL integrated circuit, and 42 is a control input terminal of the integrated circuit. L Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] In an integrated circuit consisting of a plurality of current-switching gates with emitter coupling, a transistor is added to each gate such that the emitter T1 ground is connected to the collector tray at the common part of the gate, and the base of the added transistor is 1. An integrated circuit characterized in that all voltages are connected in common and this is controlled by a valley gate circuit to a high potential level ↓9 of binary logical levels having antiphase and below a low potential level.