JPS6055641A - Mos type silicon integrated circuit element - Google Patents

Abstract

PURPOSE:To block leakage due to the decrease in threshold voltage by the exposure to radiation by a method wherein element isolation gate electrodes are connected to a ground line in the case of an NMOS type transistor, and to a power source line in the case of a PMOS type transistor. CONSTITUTION:NMOS transistors 221 and 223 are provided with gate electrodes 31 and 31 connected to the ground line (VSS) 30, and PMOS type transistors 231 and 233 with gate electrodes 34 and 34 connected to the power source line (VCC) 33, and the elements are isolated by these gate electrodes. Besides, common gates 26... and the gate ends of the gate electrodes 31, 31, 34, 34 are provided with insulation films 35 of the same film thickness as that of the gate insulation film of each transistor, so as not come to contact with the field insulation film. Thereby, the leakage between the source and drain regions due to the inversion of the gate ends can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an MO8 type silicon integrated circuit device that can operate normally under an environment exposed to radiation.

[Technical background of the invention and its problems]

2. Description of the Related Art Conventionally, as an MO8 type silicon integrated circuit element, such as a gate array, the one shown in FIG. 1 is known.

11 m1m... in the figure, NMO8 type O8 transistor 21e22..., 1MO8 type transistor 31.3
2... are a plurality of bare basic cells, which are arranged and separated from each other by a thick field oxide film (not shown). Said NMO13 type transistor 2 I+
22”/kl-1 layer type CO source region (S)
4 t' -42..., n 4 [', drain region of I) 51 a5g..., dart'N 4
t, 6 s a 62... and 114. - Power, PMO8 type O8 register 3. ．． 3. ...are respectively p 7111 source m area (S) 71 a
7□... and the drain of p-dobe in the 0 area (9) 81.
82..., dirt 11, pole 9. ,9. . . . (1-j is formed. The drain Sll'I region (r) of the layer type of the NMO8 type transistor 2., 2.) 5
m, source region (6ilft+ corresponding to between S>4m
: On the first field oxide film and on the other field oxide films, wiring 10... is formed. This J + ill, group 10...ke, each source, drain'
%['l 1j4Q, and are connected via contacts 11...

In a gate array having such a structure, the wiring 10...
The thick field oxide crotch at the bottom is a semiconductor substrate, so a parasitic MO8) runnostar is formed.
The structure is such that it does not normally operate as a transistor. Moreover, each transistor 2. ,2. ..., 31m3m r-
) city, pole 6. .

The ends of 6, l...', 9159m'... exist on the thick field oxide film, but the ends of the dirt electrodes are connected to each transistor 2! , 2. ..., 31m3M... has a structure that does not contribute to the operation.

However, each transistor 21.2. ..., 31
*32... When radiation such as gamma rays is irradiated, fixed positive charges are accumulated in the dart insulating film and surface states are generated, so that each transistor 2112,..., 31a32
The threshold voltage (vth) of ... shifts in the negative direction, and the channel mobility deteriorates (R, Freeman
et al a, IE Trans on Nucl
ear 5oience # NS-25a A 6
#P1216 (1978)). Specifically, radiation causes NMO8 type O8 resistor 2Is2! ...'s v
th is shallow < (vth listen). For this reason, lowering the process temperature (G, W, ITugles et al.
l+ 5o11d StatsTecbnology
, 70 (1979)) etc., efforts are being made to suppress element parameter fluctuations.

By the way, the amount of shift in vth due to radiation is due to the oxide film I
Proportional to the second to third power of V (G, F.

1) *rb*nwiek et ml, IE'T
rans, on NuclearScience@*
NS-22+ A6*P, 2151 (197
5)) Therefore, in the parasitic MO8l transistor formed via the JGt field saturation film, vth changes significantly. As a result, in the N channel region of the NMO8 type O8 transistor 21m2m..., for example, the parasitic MO8 transistor under the wiring 10 is always ON, and a leakage current occurs between the drain region 51 and the source region 4. , the four effects occur: element isolation is performed normally and tl disappears.

In addition, the ends of the gate electrodes 6K and 6 of each transistor 21s'l... are structured to exist on a thick field oxide film, so they are NMO8 type O8.
In the registers 21, 22..., the booth area 42
A problem arises in that leakage occurs between the drain region 52 and the drain region 52, and normal transistor operation is hindered.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and includes problems such as radiation exposure, leakage caused by a drop in the threshold voltage of parasitic MO transistors existing in element isolation regions having thick field oxide films, and f -) Parasitic MO at the end of the electrode
8) MOS Bq that can prevent leakage caused by a drop in transistor threshold voltage and ensure normal operation.
The object is to provide a silicon integrated circuit device.

61 [Summary of the Invention] The present invention is synonymous with the source f (i) of an MO8 type transistor with a 1t1' type channel. Connect the r-) M/pole to the ground line or power supply line, and prevent leakage by connecting it to the ground line or power supply line.

To be more specific about the above-mentioned element size of 1tllL gate electrode, in the case of a core case 1-electrode dNMOS transistor, the contact is 111j, and the 1'tl gate electrode of a 2MO8 transistor is 1'tl. Ha, (connected to the line) and
As a result, the element amount l#11 is used instead of the conventional thick field oxide layer.

[Examples of the invention]

Hereinafter, a dirt array constituting a three-man powered NOR dirt system according to an embodiment of the 2t invention will be described with reference to FIG.

In the figure (D211.21..21. are NMO8 type O8 registers 221, 222, 22., PMO8 type O8
register 231. These are a plurality of basic cells each having a pair of 232 and 233 cells. Said NMO8 type O8 register 22
1 to 223 are n+ type source regions (S) 24, drain regions (B) 25, and common darts 26 connected to signal lines, not shown, respectively, provided on a semiconductor substrate (not shown). ...Toga PMO8 type O8 register 231
-233 are ps provided on a semiconductor substrate (not shown), respectively.
A ten-shaped source region (S) + y... and a drain region (
) 28... and the common dirt 26...

In a 2MO8 type transistor, the source region 27...
The drain regions 28, . . . are provided close to each other.

Between the NMO8 type O8 transistors 223 and 22B and the NMO8 type transistor on the column side (not shown), gate electrodes 31 and 31 connected to a ground line (Vllll) 30 via contacts 29 and 29 are provided, respectively. The element thickness 1F is performed by the R,6 dart electrodes 31 and 31. Similarly, PMO8 type O8 register 23
A power line (
The dart electrodes 34, . 9
4 are provided respectively, and the gate electrodes 34 and 34 perform the separation. Mi+ transistor 22
, ~223.23, ~233 common darts 26... and dart electrodes 31, 31, 34, 34 in nine layers in the dart width direction.

However, according to the present invention, when a thick field oxide film is used as in the conventional case, the isolation between elements can be improved by using NMO8 type O
In the 8-type transistor, the dirt electrodes 31.31 are connected to the ground line 30, and in the 2MO8 transistor, the r-) electrodes 34, 34 are connected to the power supply line 33, and the r-) ends are connected to the dirt electrodes 34, 34 of each transistor. The insulating film 35 having the same thickness as the insulating film does not come into contact with the Nyoshifield oxide film, so leakage between the source and drain regions due to inversion of the dart end can be prevented.

This effect is more effective for the inversion prevention layer because the substrate under the dirt oxide film at the dirt end has a high degree of impurity.

In the above embodiments, the shape of the dart end is described for the case where an insulating film having the same thickness as the dart insulating film of each transistor is provided in a direction perpendicular to the dart width direction. Not done. For example, as shown in FIG. 3, the structure may be such that the insulating films 41 and 41 are provided perpendicularly to the dart width direction and along the dart width direction. Note that 47 in Figures 3 and 4 also sounds when you want to minimize the drop in stacking density and prevent the seat from reversing. It is.

In addition, in the above embodiment, an NMO8 type O8 transistor and a p
Mns 2-II) Although the case of a dirt array with transistors has been described, the case is not limited to this, but NMO8 type O
The present invention can be similarly applied to an MO8 type silicon integrated circuit device consisting of only either one of a PMO8 type O8 transistor and a PMO8 type O8 type transistor.

[The germ of invention]

As detailed above, according to the present invention, the dart end has a high M
By providing an O8 type silicon integrated circuit device, the cost can be reduced by >%.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a conventional dirt array, FIG. 2 is a plan view of a dirt array according to an embodiment of the present invention, and FIGS. 3 and 4 are views of the gate array shown in FIG. FIG. 7 is a plan view showing a modified example of the shape of the dart end. 211-213... Basic cell, 221-223・NM
O8 type transistor, z, p, 2s, ~2J3-PMO
8 type transistor, 24, 27.42.45...source region, 25.2B, 43.46...drain region,
26...common) f-t, 29.32...contact, 30...ground wire (Vss), 31,34°47.
... Keto electrode, 33 ... Power supply line (VCC), 35
．． 41...Insulating film. Applicant: Director of the Agency of Industrial Science and Technology Kawa 1) Yube 13- Figure 1 Figure 3 Figure 4

Claims (1)

[Claims] 1. Two or more MO8s comprising source and drain regions formed on a semiconductor substrate, and a dirt electrode formed on a channel region of these regions via a dirt insulating film.
In a semiconductor device consisting of a type transistor, the source region and the drain region, or the drain region and the drain region, or the source region and the source region of each isothermal channel MO8 type transistor are provided in contact with each other, and a dirt electrode is connected to a ground line. Alternatively, it is connected to a power supply line, the dart electrode is provided between the MO8 type transistors of each of the isothermal channels, and an insulating film having the same thickness as the dart insulating film is provided at the end of the dirt in the gate width direction. MO8 to be
type silicon integrated circuit element. 2. The MO8 type according to claim 1, wherein the conductivity type of the channel of each MO8 type transistor is N type, and the dirt electrode provided between the MO8 type transistors is connected to a ground line. Silicon integrated circuit element. 3. The MO8 type silicon according to claim 1, wherein the channel conductivity type of each MO8 type transistor is P type, and the gate electrode provided between the MO8 type transistors is connected to a power supply line. Integrated circuit elements. 4. The MO8 type silicon integrated device according to claim 1, characterized in that the concentration of the semiconductor substrate under the insulating film at the end of the dirt in the dart width direction having the same film thickness as that of the dirt insulating film is increased. circuit element.