JPS6053065A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6053065A JPS6053065A JP58160331A JP16033183A JPS6053065A JP S6053065 A JPS6053065 A JP S6053065A JP 58160331 A JP58160331 A JP 58160331A JP 16033183 A JP16033183 A JP 16033183A JP S6053065 A JPS6053065 A JP S6053065A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- silver solder
- external
- molten
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野］
本発明は、半導体装置の信頼性向」−１特に外部リード
をパッケージにろう利を用いて固着する型のパンケージ
の半導体装置の信頼性向」二に適用して有効な技術に関
するものである。[Detailed Description of the Invention] [Technical Field] The present invention is applicable to the reliability of semiconductor devices (1), especially the reliability of semiconductor devices of the type that uses soldering to secure external leads to the package (2). It is about effective techniques.
［背景技術］
半導体装置の利用が多様化するに伴い、半導体装置に対
する要求も増加する傾向にあり、その１つに顧客段階で
ソケットに挿入して使用に供される製品がある。たとえ
ば、ＥＰＲＯＭ （紫外線照射消去可能読み出し専用メ
モリー）等の外部リードをろう材を用いてパンケージの
側面（サイド） −にろう付け（ブレーズ）するザイド
ブレーズドバソケージを用いてなる半導体装置であって
、これらソケット使用される半導体装置については、装
“置の性能保持の観点から、外部リードの最上層には金
等の貴金属を撞着することにより、外部リードの腐食を
防止し、半導体装置の信頼性向上を図り、顧客の要求に
応えている（たとえば雑誌「電子材料」、１９８２年４
月号Ｐ２９６など）。[Background Art] As the uses of semiconductor devices become more diverse, the demands on semiconductor devices tend to increase, and one of them is a product that is used by being inserted into a socket at the customer stage. For example, a semiconductor device using a Zidebrazed bath cage in which external leads of an EPROM (ultraviolet irradiation erasable read-only memory) or the like are brazed to the sides of the pan cage using a brazing material. For semiconductor devices used in these sockets, from the perspective of maintaining device performance, the top layer of the external leads is coated with a noble metal such as gold to prevent corrosion of the external leads and improve the reliability of the semiconductor devices. (For example, the magazine "Electronic Materials", April 1982)
Monthly issue P296 etc.).
ところが、外部リードに金等をめっきした半導体装置で
あっても、外部リードの腐食が原因で、導通不良やリー
ド折れ等の問題が生していることが、本発明者等により
見い出された。However, the inventors have discovered that even in semiconductor devices whose external leads are plated with gold or the like, problems such as poor conductivity and lead breakage occur due to corrosion of the external leads.
これら導通不良等の問題点の原因究明のため本発明者等
が鋭意検討した結果、次の事実が明らかにされた。As a result of intensive studies by the present inventors to investigate the cause of these problems such as poor conduction, the following facts were clarified.
（１）外部リードのソケット差し込み部の金等のめっき
仕上げ面にできた亀裂や剥離部から腐食が生じているこ
とがリード折れ等の原因であること。(1) Corrosion occurring from cracks or peelings on the gold or other plated surface of the socket insertion part of the external lead is the cause of lead breakage.
（２）金等のめっき仕上げ面にできる亀裂等は該仕−ヒ
げ面に生じている凹凸部に、ソケット−・差し込む場合
等にストレスが加わることが主たる原因であること。(2) The main cause of cracks and the like that form on the plated surface of gold or the like is that stress is applied when inserting a socket into the uneven parts formed on the finished surface.
（３）仕上げ面の凹凸は、めっき前に外部リードを外部
電極にろう付けする際、溶融ろう材がソケット差し込み
部に流出移動し、該ソケット差し込み部に凝固してでき
た凹凸部が原因で生じている。(3) The unevenness on the finished surface is caused by the unevenness created when the external lead is brazed to the external electrode before plating, when the molten brazing metal flows out into the socket insertion area and solidifies in the socket insertion area. It is occurring.
したがって、上記問題は外部リードのろうイ」げ時に、
溶融ろう材がソゲソ］・差し込み部に流出移動すること
を防止することで解決できるということが本発明者等に
より明らかにされた。Therefore, the above problem occurs when the external lead is disabled.
The present inventors have revealed that the problem can be solved by preventing the molten brazing filler metal from flowing out and moving into the insertion section.
なお、上記問題点については、これまで注目していなか
ったものであり、本発明者等が始めて注目し、かつ明ら
かにしたものである。Note that the above-mentioned problem has not been noticed until now, and the inventors of the present invention have noticed and clarified it for the first time.
［発明の目的］
本発明の目的は、外部リードをめっき仕上げしてなる半
導体装置において、外部リードにできた亀裂が原因で発
生する外部リードの腐食を防止することにより、該半導
体装置の信頼性を向上することにある。[Object of the Invention] An object of the present invention is to improve the reliability of a semiconductor device in which external leads are plated by preventing corrosion of the external leads caused by cracks formed in the external leads. The goal is to improve.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［発明の概要］
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体装置の外部リードをパッケージの外部
電極にろう付けする際に、溶融ろう月が外部リート′の
ソケット差し込み部へ流出移動することを効果的に防止
し、その後に形成されるめっき仕上げ面を平坦形状にす
ることにより、該半導体装置をソケットに差し込んだ場
合でも局部的ストレスの発生を防ぐことができ、それ故
に、その局部的ストレスが原因でめっき仕上げ面に亀裂
または剥がれ等が発生することも防止できる。In other words, when the external leads of the semiconductor device are brazed to the external electrodes of the package, it effectively prevents the molten solder from flowing out into the socket insertion part of the external lead and prevents the plating finish surface formed afterwards. By making the semiconductor device flat, it is possible to prevent local stress from occurring even when the semiconductor device is inserted into a socket, and therefore, cracks or peeling may occur on the plated surface due to the local stress. It can also be prevented.
さらには、該亀裂等から水分等が侵入して行くことが原
因で発生する外部リードσ腐食を有効に防止することを
達成するものである。Furthermore, it is possible to effectively prevent external lead σ corrosion caused by moisture entering through the cracks and the like.
［実施例１コ
第１図は、本発明の一実施例であるＥＰＲＯＭ半導体装
置の概略断面図である。[Embodiment 1] FIG. 1 is a schematic cross-sectional view of an EPROM semiconductor device which is an embodiment of the present invention.
本実施例１であるＥＰＲＯＭ半導体装置ば、４２−アロ
イ等の外部リード１をセラミックパッケージ２の外部電
極３にろう付けした後に該外部リード１に下地めっきお
よび仕上げめっきをしてそれぞれニッケル層４および金
層５を形成したザイドブレーズド型セラミックパッケー
ジからなるものである。In the EPROM semiconductor device according to the first embodiment, an external lead 1 made of 42-alloy or the like is brazed to an external electrode 3 of a ceramic package 2, and then the external lead 1 is subjected to base plating and final plating to form a nickel layer 4 and a nickel layer 4, respectively. It consists of a Zide blazed type ceramic package on which a gold layer 5 is formed.
上記パッケージ２のキャビティ６内には、パンケージ基
板の上にペレット７がＡ ｕ −Ｓ ｉ共晶８等で取り
付けられ、該ペレット７のボンディングパソドと導電層
９とはワイヤ１０をボンディングすることにより電気的
に接続され、さらに該キャビティ６はガラスキャンプ１
１により低融点ガラス１２を介して気密封止されたもの
である。これによって、ガラスをパッケージに埋込むこ
とを省略して、パッケージを低コスト化してい′る。ま
た、パンケージ２の下側端部の角部を除いて、割れ、欠
は等を防止している。Inside the cavity 6 of the package 2, a pellet 7 is attached on the pan cage substrate using Au-Si eutectic 8 or the like, and a wire 10 is bonded to the bonding pad of the pellet 7 and the conductive layer 9. The cavity 6 is electrically connected to the glass camp 1.
1 and hermetically sealed with a low melting point glass 12 interposed therebetween. This eliminates the need to embed glass in the package, reducing the cost of the package. In addition, cracks, chips, etc. are prevented except for the corners of the lower end of the pan cage 2.
上記半導体装置における本発明の特徴は、ニッケルおよ
び金の２層を鑞着してなる上記外部り−ド１において、
該外部リード１のソケット差し込み部１ａの撞着面を平
坦形状に形成したところにある。The feature of the present invention in the semiconductor device is that in the external lead 1 formed by soldering two layers of nickel and gold,
The fitting surface of the socket insertion portion 1a of the external lead 1 is formed into a flat shape.
すなわち、外部リード１をパッケージの外部電極３に銀
ろう１３で加熱融着にて取り付ける際に、溶融した銀ろ
うがソケット差し込み部１ａに流出移動することを効果
的に防止し、該流出銀ろうが凝固してできる凹凸が原因
で該ソケット差し込み部１ａの撞着面に現れる凹凸の発
生を防止することにより、該撞着面の凹凸部が原因で生
じる撞着面の亀裂または剥離等の発生を防止し、ひいて
は、該撞着面に生じた亀裂等が原因となる外部ＩＪ −
ト１の腐食を防止し、該半導体装置の信頼性の向」二を
達成するものである。That is, when attaching the external lead 1 to the external electrode 3 of the package with the silver solder 13 by heating and fusing, the molten silver solder is effectively prevented from flowing into the socket insertion part 1a, and the flowing silver solder is prevented. By preventing the occurrence of unevenness that appears on the fitting surface of the socket insertion part 1a due to the unevenness formed by solidification, it is possible to prevent the occurrence of cracks or peeling of the fitting surface caused by the unevenness of the fitting surface. In addition, external IJ-
This prevents corrosion of the semiconductor device 1 and improves the reliability of the semiconductor device.
上記の凹凸形状の外部リード１のソケット差し込み部１
ａの形成は、次に示すこともその一因と考えられる。す
なわち、ろうイ旧ノは予め外部り−ド１を外部電極３に
銀ろうリボンを挟持した状だ１で固定した後、所定温度
に加熱融着しζ行うが、この場合に使用する外部リード
の固定治具の固定部が平面形状（図示せず）であると、
外部リード面と該固定部平面との間に間隙が形成され、
その間隙に溶融銀ろう１３が毛管現象で侵入して行き、
その結果ソケット差し込み部１ａにまで銀イ）う１３が
及び、凹凸面を形成することになる。Socket insertion part 1 of the above uneven external lead 1
The formation of a is thought to be due to the following factors. That is, the soldering wire is prepared by fixing the external lead 1 to the external electrode 3 with a silver soldering ribbon sandwiched between them, and then heating and fusing it to a predetermined temperature. If the fixing part of the fixing jig is a planar shape (not shown),
a gap is formed between the external lead surface and the fixed part plane;
Molten silver solder 13 enters the gap by capillary action,
As a result, the silver lining 13 extends to the socket insertion portion 1a, forming an uneven surface.
そこで、外部リート１のソゲソ１−差し込め部Ｉａより
上側の位置を、第２図に示すよう名−′その先端の断面
形状が鋸歯状であるようなダム１４て接離自在に挟み付
けることにより、／８副；銀ろう１３がソケット差し込
み部１ａに流出移動することを効果的に防止できるので
ある。Therefore, the position above the insertion part Ia of the external reel 1 is sandwiched between a dam 14 whose tip has a serrated cross-sectional shape as shown in FIG. , /8 vice: It is possible to effectively prevent the silver solder 13 from flowing out into the socket insertion part 1a.
この場合に使用するダム１４ば上記固定治具の一部であ
ればより効果的ではあるが、固定治具以外の流出防止を
目的とする装置であってもよい。Although it is more effective if the dam 14 used in this case is part of the fixing jig, it may be a device other than the fixing jig for the purpose of preventing outflow.
また、銀ろう流出防止の他の方法としては、特に銀ろう
の量が多い場合には、その溶融銀ろうが重力方向に流出
することも、ソケット差し込め部１ａにできる凹凸の一
因であると考えられる。そこで、外部電極３に銀ろうを
挟持した状態で外部リード１をパッケージ２に固定した
後の加熱融着の工程を、図示のようなサイドプレースＦ
型の場合は単に上下方向を逆にすることによっても、上
記理由によりソケット差し込み部１ａにできる凹凸の発
生を防止できる。In addition, as another method for preventing the silver solder from flowing out, especially when the amount of silver solder is large, the flow of the molten silver solder in the direction of gravity is also a cause of the unevenness formed on the socket insertion part 1a. Conceivable. Therefore, after fixing the external lead 1 to the package 2 with the silver solder sandwiched between the external electrode 3, the heat fusing process is performed using a side place F as shown in the figure.
In the case of a mold, simply reversing the vertical direction can also prevent the occurrence of unevenness on the socket insertion part 1a for the above-mentioned reason.
さらに、ソケット差し込め部に、予め銀ろうにぬれない
材質、たとえば、ポリイミド樹脂等の軟化点の高い有機
膜からなる被膜を形成した状態でろう付けし、その後に
該被膜を除去することによっても、目的を達成できる。Furthermore, by brazing the socket insertion part with a coating made of a material that cannot be wetted by silver solder, for example, an organic film with a high softening point such as polyimide resin, and then removing the coating, You can achieve your goals.
［実施例２］
第３図は、本実施例２である半導体装置における外部電
極への外部リード取り付は部の拡大断面図であり、該取
り付は部以外の構成は、上記実施例１である第１図の半
導体装置と同一である。[Example 2] FIG. 3 is an enlarged sectional view of the attachment of external leads to external electrodes in the semiconductor device of Example 2, and the structure other than the attachment is the same as that of Example 1. This is the same as the semiconductor device shown in FIG.
本実施例２である半導体装置の特徴は、第３図に示すよ
うに、パッケージ２の導電層９と電気的に接続されてい
る外部電極３に、銀ろう１３で取り付けられ、その後に
めっきしてなる外部リード１において、該取り付は部に
おける片面であって外部電極３の方向を向いた面にプレ
ス等の方法でギザギザの鋸歯形状１５の如き凹凸形状を
形成したことにある。すなわち、銀ろう融着部である外
部リード面に鋸歯形状１５を形成することにより、溶融
状態では流出移動する余分な銀ろうを該鋸歯形状１５に
より形成される隙間に吸収させることにより、溶融銀ろ
うの流出を防止し、ソゲソｔ・差し込み部に流出銀ろう
が原因で凹凸が生じることを有効に防止するものである
。さらに、取り付は部に鋸歯形状１５を形成することは
、接着材である銀ろうとの接触面積を拡大することにも
なるので、該取り付は部における外部リードの接着強度
を増大することができる。As shown in FIG. 3, the semiconductor device of Example 2 is characterized by being attached to the external electrode 3 electrically connected to the conductive layer 9 of the package 2 with silver solder 13, and then plated. In the external lead 1, the attachment is achieved by forming an uneven shape such as a jagged sawtooth shape 15 on one side of the part facing the external electrode 3 by a method such as pressing. That is, by forming the sawtooth shape 15 on the external lead surface which is the silver solder fusion part, excess silver solder that flows out and moves in the molten state is absorbed into the gap formed by the sawtooth shape 15, and the molten silver This prevents the solder from flowing out and effectively prevents unevenness from occurring at the soldering socket and insertion portion due to the flowing silver solder. Furthermore, forming the sawtooth shape 15 on the mounting part also expands the contact area with the silver solder, which is the adhesive, so this mounting can increase the adhesive strength of the external lead on the part. can.
本実施例２の半導体装置は、外部リードの取り付は部に
余分な溶融銀ろうを吸収して咳銀ろうの流出移動を防止
するものであるが、上記実施例１に示した取り付は方法
を採用すれば、さらに９ＪＪ果的に銀ろうの流出を防止
することができる。In the semiconductor device of Example 2, the attachment of the external leads absorbs excess molten silver solder to prevent the outflow and movement of the molten silver solder, but the attachment shown in Example 1 above If method 9JJ is adopted, the outflow of silver solder can be further effectively prevented.
［効果］
（１）、外部リードのソケット差し込み部の防食用撞着
面に亀裂または剥離が生じることを防止することにより
、該亀裂または剥離部から発生する外部リードの腐食を
有効に防止することができる。[Effects] (1) By preventing cracks or peeling from occurring on the anticorrosive contact surface of the socket insertion part of the external lead, corrosion of the external lead that occurs from the crack or peeling part can be effectively prevented. can.
（２）、外部リードのソケット差し込め部の防食用撞着
面に凹凸部が生じることを防止することにより、ソケッ
トへの抜き差し時に該凹凸部にストレスが加わることで
生じる該撞着面の亀裂またはヱｌ躇１１の発生を有効に
防止することができるため、上記（１）と同様の効果が
得られる。(2) By preventing the formation of uneven parts on the anti-corrosion fitting surface of the socket insertion part of the external lead, cracks or dents on the fitting surface that occur due to stress being applied to the uneven parts when inserting or removing the external lead into the socket can be prevented. Since the occurrence of hesitation 11 can be effectively prevented, the same effect as (1) above can be obtained.
（３）、外部リードをパッケージの外部電極部にろう付
けにて取り付ける場合、加熱溶融したろう利が該外部リ
ードのソケット差し込め部に流出移動し、該差し込み部
で冷却凝固して凹凸部を形成することを防止することに
より、ろう付は後に該外部リード表面に形成される防食
用撞着面に凹凸部がない状態にすることができるため、
上記（２）と同様の効果が得られる。(3) When attaching the external lead to the external electrode part of the package by brazing, the heated and melted wax flows into the socket insertion part of the external lead, cools and solidifies in the socket insertion part, and forms an uneven part. By preventing this, the brazing can be performed without any unevenness on the anti-corrosion fitting surface that will later be formed on the surface of the external lead.
The same effect as in (2) above can be obtained.
（４）、外部リードの外部電極への取り伺は部の接７「
面をギザギザ形状等の凹凸形状にすることにより、ろう
付けの際に余分なろう材を該凹凸部に吸収せしめること
ができるので、溶融ろう材の流出移動をより有効に防止
でき、上記（３）と同様の効果がｊｉｌられる。(4) For inquiries about the external electrode of the external lead, contact section 7 "
By making the surface have an uneven shape such as a jagged shape, excess brazing material can be absorbed by the unevenness during brazing, so it is possible to more effectively prevent the outflow and movement of the molten brazing material. ) has a similar effect.
（５）、外部リードのろう付けの際、使用する固定治具
の一部として、または他の装置としてｊｌ・：山１ノ（
等のダムで外部リードの所定の位置を挟み（＝Ｊりるご
とにより、溶融ろう材の流出移動を防１にし、−１−記
（３）と同様の効果がｉＭられる。(5) When brazing the external lead, as part of the fixing jig used or as other equipment.
By sandwiching a predetermined position of the external lead with a dam such as (=J), the outflow movement of the molten brazing material is prevented, and the same effect as in (3) in -1- is achieved.
（６）、上記（４）のように外部リードの接着面を凹凸
形状にすることにより、接着材であるろう材との接触面
積を拡大することができるので、外部リードのパッケー
ジ外部電極への接着強度を向上さ−Ｌ！イ。(6) By making the bonding surface of the external lead uneven as described in (4) above, the contact area with the brazing material, which is the bonding material, can be expanded, so that the external lead can be attached to the package external electrode. Improve adhesive strength-L! stomach.
ことができる。be able to.
（７）、上記（１）ないしく６）より、半導体装置の信
頼性を向上することができる。(7) From (1) to 6) above, the reliability of the semiconductor device can be improved.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、ろう材としては銀ろうのみについて説明した
がこれに限るものでなく、また、外部電極のめっきも実
施例に示したものに限るものでなく、単層または３層以
上であってもよく、さらにめっき材料についても、目的
に応じてニッケルまたは全以外の種々の金属をも使用で
きるものである。For example, although only silver solder was described as the brazing material, it is not limited to this, and the plating of the external electrode is not limited to that shown in the examples, but may be a single layer or three or more layers. Furthermore, as for the plating material, various metals other than nickel or nickel can be used depending on the purpose.
［利用分野］
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるサイドブレーズド型
セラミックパッケージからなるＥＰＲＯＭ半導体装置に
適用した場合について説明したが、それに限定されるも
のではなく、たとえば、外部リードをパッケージにろう
祠を用いてろう付けし、この後めっきを外部リードに施
すタイプのパッケージからなる半導体装置であれば他の
種々のものに適用して有効な技術である。[Field of Application] In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background thereof, which is an EPROM semiconductor device consisting of a side-brazed ceramic package, but the invention is limited thereto. For example, it is an effective technology that can be applied to a variety of other products, such as semiconductor devices consisting of packages in which external leads are brazed to the package using a brazing paste, and then plating is applied to the external leads. It is.
第１図は、本発明の一実施例である半導体装；ｉｔの概
略断面図、
第２図は、本発明における外部リードの取り付は方法の
一例についてその概略を説明するたべ）の部分断面図、
第３図は本発明の他の一実施例である半導体装置の概略
を示す拡大部分断面図である。
１・・・外部リード、１ａ・・・ソゲ・ノ１−差し込み
部、２・・・パッケージ、３・・・外’ｆｉ”Ｉ ｆ＠
＋Ｔｉ、４・・・ニッケル層、５・・・金層、６・・
・４−ヤビテイ、７・・・ペレ・ノド、８・・・Ａ ｕ
−Ｓｌ共晶、９・・・導電層、１０・・・ライ４フ、
１１・・・ガラスキャ・ノブ、１２・・・低！ｉｒｈ
ｊＦＡ力′ラス、１３・・・銀ろう、１４・・・ダム、
１５・・・鋸歯形状。FIG. 1 is a schematic sectional view of a semiconductor device that is an embodiment of the present invention; FIG. 2 is a partial cross-sectional view of an example of a method for attaching external leads in the present invention; FIG. 3 is an enlarged partial sectional view schematically showing a semiconductor device according to another embodiment of the present invention. 1...External lead, 1a...Soge no 1-insertion part, 2...Package, 3...Outside 'fi'I f@
+Ti, 4...nickel layer, 5...gold layer, 6...
・4-Yabitei, 7... Pere Nodo, 8... A u
-Sl eutectic, 9... conductive layer, 10... life 4 life,
11...Glass Kya Knob, 12...Low! irh
jFA force'ras, 13...silver wax, 14...dam,
15...Sawtooth shape.
Claims (1)
後、外部リードにめワきしてなる半導体装置において、
外部リードをろう付けする際にろう材が該外部リードの
ソケット差し込み部へ流出移動することを防止し、該差
し込み部のめっき面を平坦に形成したことを特徴とする
半導体装置。 ２、外部リードのろう付は面を凹凸形状にしたことを特
徴とする特許請求の範囲第１項記載の半導体装置。[Claims] (1) In a semiconductor device in which the external leads are soldered to the external electrodes of the package and then the external leads are wired,
What is claimed is: 1. A semiconductor device, characterized in that when brazing an external lead, a brazing material is prevented from flowing into a socket insertion part of the external lead, and the plated surface of the insertion part is formed flat. 2. The semiconductor device according to claim 1, wherein the external lead is brazed with an uneven surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58160331A JPS6053065A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58160331A JPS6053065A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6053065A true JPS6053065A (en) | 1985-03-26 |
Family
ID=15712650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58160331A Pending JPS6053065A (en) | 1983-09-02 | 1983-09-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6053065A (en) |
-
1983
- 1983-09-02 JP JP58160331A patent/JPS6053065A/en active Pending
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