JP3826776B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP3826776B2
JP3826776B2 JP2001368562A JP2001368562A JP3826776B2 JP 3826776 B2 JP3826776 B2 JP 3826776B2 JP 2001368562 A JP2001368562 A JP 2001368562A JP 2001368562 A JP2001368562 A JP 2001368562A JP 3826776 B2 JP3826776 B2 JP 3826776B2
Authority
JP
Japan
Prior art keywords
electroless
plating layer
heat sink
solder
thickness dimension
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2001368562A
Other languages
Japanese (ja)
Other versions
JP2003168771A (en
Inventor
中瀬　　好美
善次 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2001368562A priority Critical patent/JP3826776B2/en
Publication of JP2003168771A publication Critical patent/JP2003168771A/en
Application granted granted Critical
Publication of JP3826776B2 publication Critical patent/JP3826776B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、例えばヒートシンク（金属体）の上面に半導体素子を半田付けするように構成された半導体装置に関する。
【０００２】
【従来の技術】
例えば高耐圧・大電流用の半導体素子は、使用時の発熱が大きいため、チップからの放熱性を高める構成が必要である。このため、ＣｕやＡｌ等の放熱性の良い金属体からなるヒートシンクの上面に、上記半導体素子を直接半田付けして接合し、放熱性を向上させている。この場合、半田付けに使用する半田としては、Ｐｂを含む通常の半田を使用している。また、ヒートシンクの表面には、無電解Ｎｉ−Ｐめっきを施しており、この無電解Ｎｉ−Ｐめっき層により、ヒートシンクの耐蝕性及び半田付け性を向上させている。
【０００３】
【発明が解決しようとする課題】
ところで、近年、環境保護の観点から、Ｐｂを含む半田を使用しないようにする対策が求められている。そこで、Ｐｂを含まない半田として、Ｓｎリッチ半田例えばＳｎ−Ｓｂ系ろう材を使用することが考えられている。そして、本発明者らは、実際にＳｎ−Ｓｂ系ろう材を使用して、ヒートシンクの上面に半導体素子を半田付けしてみた。すると、ヒートシンクの表面にめっきされていた無電解Ｎｉ−Ｐめっき層が剥離するという不具合が発生した。
【０００４】
ここで、本発明者らは、上記無電解Ｎｉ−Ｐめっき層の剥離が発生する原因を調べてみたところ、次のことがわかった。Ｓｎ−Ｓｂ系ろう材は、多量のＳｎを含んでいるため、溶融した状態では他の金属と活発に反応して、他の金属を溶融ろう材中に溶け込ませるという性質があった。従って、無電解Ｎｉ−Ｐめっき層に含まれるＮｉが、Ｓｎ−Ｓｂ系ろう材中に溶融し、Ｎｉ−Ｓｎの金属化合物が生成される。
【０００５】
この結果、無電解Ｎｉ−Ｐめっき層と被接着部材であるヒートシンクとの界面付近は、無電解Ｎｉ−Ｐめっき層に含まれるＰが濃化した状態となり、Ｎｉ３Ｐが主成分のＰリッチ層が形成される。このＰリッチ層が形成されると、ヒートシンクと無電解Ｎｉ−Ｐめっき層との間の接着力が低下するため、無電解Ｎｉ−Ｐめっき層の剥離が発生するのである。特に、半導体装置に熱的ストレスや機械的ストレスが加わると、無電解Ｎｉ−Ｐめっき層ひいては半田層の剥離が発生し易くなることがわかった。
【０００６】
そこで、本発明の目的は、半田付けにＳｎリッチ半田を使用しながら、金属体の表面に施された無電解Ｎｉ−Ｐめっき層の剥離を防止することができる半導体装置を提供することにある。
【０００７】
【課題を解決するための手段】
請求項１の発明によれば、表面に無電解Ｎｉ−Ｐめっき層がめっきされた金属体の上面に半導体素子をＳｎリッチ半田を介して接合してなり、前記半導体素子の全体並びに前記金属体の一部を除きその大部分を樹脂でモールドするように構成された半導体装置において、無電解Ｎｉ−Ｐめっき層の厚み寸法を、金属体と無電解Ｎｉ−Ｐめっき層との界面に、半田付け時にＰリッチ層が到達しないようにする厚み寸法に構成したので、Ｓｎリッチ半田を使用しても、金属体と無電解Ｎｉ−Ｐめっき層との界面にＰリッチ層が形成されなくなる。従って、金属体と無電解Ｎｉ−Ｐめっき層との間の接着力が低下しなくなるため、無電解Ｎｉ−Ｐめっき層の剥離を防止することができる。
【０００８】
請求項２の発明によれば、前記無電解Ｎｉ−Ｐめっき層の厚み寸法を、約５μｍ以上に設定したので、無電解Ｎｉ−Ｐめっき層の剥離を防止することができる。尚、本発明者らは、実験及び試作を行うことにより、無電解Ｎｉ−Ｐめっき層の厚み寸法を、約５μｍ以上に設定すれば、無電解Ｎｉ−Ｐめっき層の剥離を防止できることを確認している。
【０００９】
【発明の実施の形態】
以下、本発明の一実施例について図面を参照しながら説明する。まず、図１は、本実施例の半導体装置の概略構成を示す断面図である。この図１に示すように、本実施例の半導体装置１は、半導体チップ（半導体素子）２と、下側ヒートシンク（金属体）３と、上側ヒートシンク（金属体）４と、ヒートシンクブロック（金属体）５とを備えて構成されている。
【００１０】
上記半導体チップ２は、例えばＩＧＢＴやＭＯＳＦＥＴやサイリスタ等のパワー半導体素子から構成されている。この半導体チップ２の形状は、本実施例の場合、例えば矩形状の薄板状である。また、下側ヒートシンク３、上側ヒートシンク４及びヒートシンクブロック５は、例えばＣｕで構成されている。尚、Ｃｕに代えて、Ａｌ等の熱伝導性及び電気伝導性の良い金属で構成しても良い。
【００１１】
更に、下側ヒートシンク３、上側ヒートシンク４及びヒートシンクブロック５の表面には、図２に示すように、無電解Ｎｉ−Ｐめっき層６がめっきされている。そして、この無電解Ｎｉ−Ｐめっき層６の厚み寸法は、本実施例の場合、約５μｍ以上に設定されている。
【００１２】
また、上記構成の半導体装置１においては、半導体チップ２の下面と下側ヒートシンク３の上面との間は、接合部材である例えば半田７によって接合されている。この半田７としては、Ｓｎリッチ半田（Ｐｂを含まない半田）、例えばＳｎ−Ｓｂ系のろう材が使用されている。尚、上記Ｓｎ−Ｓｂ系のろう材に代えて、Ｓｎ−Ａｇ系のろう材やＳｎ−Ｃｕ−Ｎｉ系のろう材等を使用しても良い。
【００１３】
そして、半導体チップ２の上面とヒートシンクブロック５の下面との間も、上記Ｓｎ−Ｓｂ系のろう材からなる半田７によって接合されている。更に、ヒートシンクブロック５の上面と上側ヒートシンク４の下面との間も、上記Ｓｎ−Ｓｂ系のろう材からなる半田７によって接合されている。尚、上記各半田７の層の厚み寸法は、約１００μｍ程度に設定されている。このように接合することにより、上記構成においては、半導体チップ２の両面からヒートシンク３、４及びヒートシンクブロック５を介して放熱される構成となっている。
【００１４】
尚、上記構成の場合、下側ヒートシンク３及び上側ヒートシンク４は、半導体チップ２の各主電極（例えばコレクタ電極やエミッタ電極等）に半田７を介して電気的にも接続されている。
【００１５】
一方、半導体チップ２の制御電極（例えばゲートパッド等）は、図１に示すように、リードフレーム８にワイヤーボンディングされている。即ち、例えばＡｌやＡｕ等製のワイヤー９によって半導体チップ２の制御電極とリードフレーム８とが接続されている。
【００１６】
また、下側ヒートシンク３及び上側ヒートシンク４は、厚さ寸法が約１ｍｍ程度の板材で形成されており、それぞれ端子部３ａ及び４ａが突設されている。更に、ヒートシンクブロック５は、半導体チップ２よりも１回り小さい程度の大きさの矩形状の板材である。更にまた、上記構成の場合、下側ヒートシンク３の上面と上側ヒートシンク４の下面との間の距離は、例えば１〜２ｍｍ程度になるように構成されている。
【００１７】
そして、図１に示すように、一対のヒートシンク３、４の隙間、並びに、チップ２及びヒートシンクブロック５の周囲部分には、樹脂（例えばエポキシ樹脂）１０が充填封止されている。この構成の場合、ヒートシンク３、４等を樹脂１０でモールドするに当たっては、上下型からなる成形型（図示しない）を使用している。また、上記構成の場合、下側ヒートシンク３の下面及び上側ヒートシンク４の上面が、それぞれ露出するように樹脂モールドされている。これにより、ヒートシンク３、４の放熱性を高めている。
【００１８】
尚、樹脂１０とヒートシンク３、４との密着力、樹脂１０と半導体チップ２との密着力、並びに、樹脂１０とヒートシンクブロック５との密着力を強くするために、上記樹脂１０をモールドする前に、コーティング樹脂例えばポリアミド樹脂（図示しない）をヒートシンク３、４、ヒートシンクブロック５及びチップ２の表面に塗布しておくことが好ましい。
【００１９】
また、上記した構成の半導体装置１の製造方法（即ち、製造工程）の具体例は、本出願人がすでに出願した特願２００１−１２７５１６や特願２００１−２２５９６３等に記載されており、これらに記載されている方法を適宜使用すれば良い。
【００２０】
ここで、下側ヒートシンク３、上側ヒートシンク４及びヒートシンクブロック５の表面に施した無電解Ｎｉ−Ｐめっき層６の厚み寸法を、約５μｍ以上に設定した理由について説明する。
【００２１】
本発明者らは、無電解Ｎｉ−Ｐめっき層６の厚み寸法を、２μｍから６μｍまで１μｍ単位で変化させたヒートシンク３、４、５を試作し、Ｓｎ−Ｓｂ系のろう材（半田７）を使用した半田付けを実行し、冷熱サイクル試験を２０００サイクル行った後、無電解Ｎｉ−Ｐめっき層６の剥離の発生率を調べる実験（試作）を実行した。この実験結果を、図３に示す。
【００２２】
この図３から、無電解Ｎｉ−Ｐめっき層６の厚み寸法を、約５μｍ以上に設定すると、剥離発生率が０となることから、無電解Ｎｉ−Ｐめっき層６（ひいては半田層７）の剥離を確実に防止できることがわかる。尚、図３のグラフにおいて、横軸は無電解Ｎｉ−Ｐめっき層６の厚み寸法を示し、縦軸は剥離発生率を示し、プロットが試作品を示している。
【００２３】
ここで、本発明者らは、無電解Ｎｉ−Ｐめっき層６の厚み寸法を、約５μｍ以上に設定したヒートシンク３、４、５に、Ｓｎ−Ｓｂ系のろう材（半田７）を使用して半田付けを実行しものについて、ヒートシンク３、４、５と半田７との界面における金属元素のデプスプロファイル（depth profile ）を測定してみた。この測定結果を、図４に示す。
【００２４】
この図４において、Ｃｕはヒートシンクの母材物質であり、Ｎｉはめっき層の主成分物質であり、Ｐはめっき層の添加物質であり、Ｓｎはろう材（半田）の主成分物質であり、Ｓｂはろう材（半田）の添加物質である。上記図４によれば、無電解Ｎｉ−Ｐめっき層６に含まれるＮｉが、Ｓｎ−Ｓｂ系ろう材７中に溶融し、Ｎｉ−Ｓｎの金属化合物が生成され、無電解Ｎｉ−Ｐめっき層に含まれるＰが濃化した状態となり、Ｐリッチ層（Ｐ濃化層）が形成されるが、このＰリッチ層は、無電解Ｎｉ−Ｐめっき層６とヒートシンク３、４、５との界面には到達していない。
【００２５】
このため、無電解Ｎｉ−Ｐめっき層６とヒートシンク３、４、５との界面には、健全な層（半田付け前の状態の層）が残るので、無電解Ｎｉ−Ｐめっき層６とヒートシンク３、４、５との間の接着力が十分な強度のまま保持される。従って、無電解Ｎｉ−Ｐめっき層６の厚み寸法を、約５μｍ以上に（十分厚く）設定すると、無電解Ｎｉ−Ｐめっき層の剥離が発生しない。
【００２６】
ここで、比較例として、無電解Ｎｉ−Ｐめっき層６の厚み寸法を３μｍに設定したヒートシンク３、４、５に、Ｓｎ−Ｓｂ系のろう材（半田７）を使用して半田付けを実行しものについて、ヒートシンク３、４、５と半田７との界面における金属元素のデプスプロファイルを測定してみた。この比較例の測定結果を、図５に示す。
【００２７】
この図５によれば、無電解Ｎｉ−Ｐめっき層６に含まれるＰが濃化した状態のＰリッチ層が、無電解Ｎｉ−Ｐめっき層６とヒートシンク３、４、５との界面に到達している。即ち、無電解Ｎｉ−Ｐめっき層６とヒートシンク３、４、５との界面まで、すべてＰリッチ層となっている。このような状態では、ヒートシンク３、４、５と無電解Ｎｉ−Ｐめっき層６との間の接着力が低下するため、無電解Ｎｉ−Ｐめっき層６の剥離が発生するのである。
【００２８】
ちなみに、従来、ヒートシンクにめっきされている無電解Ｎｉ−Ｐめっき層６の厚み寸法は、１〜２μｍ程度であり、かなり薄い。このように無電解Ｎｉ−Ｐめっき層６の厚み寸法を薄くする理由は、製造コストを安くするためである。即ち、無電解Ｎｉ−Ｐめっき層６の厚み寸法を薄くすると、めっき工程に要する時間を短くすることができ、それだけ生産性が向上するためである。
【００２９】
尚、上記実施例では、無電解Ｎｉ−Ｐめっき層６の厚み寸法を約５μｍ以上に設定したが、これに限られるものではなく、無電解Ｎｉ−Ｐめっき層の厚み寸法を、ヒートシンク（金属体）と無電解Ｎｉ−Ｐめっき層との界面に、Ｐリッチ層が到達しないようにする厚み寸法を実験や試作等によって求め、この求めた厚み寸法に設定するように構成すれば良い。
【００３０】
また、上記実施例においては、半導体チップ２を１対のヒートシンク３、４で挟む構成の半導体装置１に適用したが、半導体チップを１つのヒートシンクの上面に載せて半田付けする構成の半導体装置に適用しても良い。
【図面の簡単な説明】
【図１】本発明の一実施例を示す半導体装置の縦断面図
【図２】半導体装置の要部の拡大縦断面図
【図３】無電解Ｎｉ−Ｐめっき層の厚み寸法と剥離発生率との関係を示すグラフ
【図４】無電解Ｎｉ−Ｐめっき層の厚み寸法を十分厚くした場合のヒートシンクと半田との界面における金属元素のデプスプロファイルを示す図
【図５】無電解Ｎｉ−Ｐめっき層の厚み寸法を薄くした場合のヒートシンクと半田との界面における金属元素のデプスプロファイルを示す図
【符号の説明】
１は半導体装置、２は半導体チップ（半導体素子）、３は下側ヒートシンク（金属体）、４は上側ヒートシンク（金属体）、５はヒートシンクブロック（金属体）、６は無電解Ｎｉ−Ｐめっき層、７は半田（Ｓｎリッチ半田）、１０は樹脂を示す。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device configured to solder a semiconductor element to an upper surface of a heat sink (metal body), for example.
[0002]
[Prior art]
For example, a semiconductor device for high withstand voltage and large current generates a large amount of heat during use, and therefore requires a configuration that improves heat dissipation from the chip. For this reason, the semiconductor element is directly soldered and joined to the upper surface of a heat sink made of a metal body having good heat dissipation, such as Cu or Al, to improve heat dissipation. In this case, normal solder containing Pb is used as solder used for soldering. Moreover, the surface of the heat sink is subjected to electroless Ni—P plating, and the electroless Ni—P plating layer improves the corrosion resistance and solderability of the heat sink.
[0003]
[Problems to be solved by the invention]
By the way, in recent years, from the viewpoint of environmental protection, there is a demand for measures to prevent the use of solder containing Pb. Therefore, it is considered to use Sn-rich solder, for example, Sn—Sb brazing material, as the solder not containing Pb. Then, the present inventors actually soldered the semiconductor element on the upper surface of the heat sink by using a Sn—Sb brazing material. Then, the trouble that the electroless Ni-P plating layer plated on the surface of the heat sink peeled occurred.
[0004]
Here, the present inventors examined the cause of the peeling of the electroless Ni—P plating layer, and found the following. Since the Sn—Sb brazing filler metal contains a large amount of Sn, it has a property of reacting actively with other metals in a molten state and causing the other metals to be dissolved in the molten brazing filler metal. Therefore, Ni contained in the electroless Ni—P plating layer is melted in the Sn—Sb brazing material, and a metal compound of Ni—Sn is generated.
[0005]
As a result, in the vicinity of the interface between the electroless Ni—P plating layer and the heat sink as the adherend member, P contained in the electroless Ni—P plating layer is concentrated, and P 3 rich mainly composed of Ni 3 P. A layer is formed. When this P-rich layer is formed, the adhesive force between the heat sink and the electroless Ni—P plating layer is reduced, so that the electroless Ni—P plating layer is peeled off. In particular, it has been found that when thermal stress or mechanical stress is applied to the semiconductor device, peeling of the electroless Ni—P plating layer and the solder layer easily occurs.
[0006]
Accordingly, an object of the present invention is to provide a semiconductor device capable of preventing peeling of an electroless Ni—P plating layer applied to the surface of a metal body while using Sn-rich solder for soldering. .
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, a semiconductor element is joined to the upper surface of a metal body having an electroless Ni-P plating layer on its surface via Sn-rich solder, and the entire semiconductor element and the metal body are joined together. In the semiconductor device configured to mold most of the resin with resin except for a part of the thickness, the thickness dimension of the electroless Ni—P plating layer is soldered to the interface between the metal body and the electroless Ni—P plating layer. Since the thickness dimension is set so that the P-rich layer does not reach at the time of application, the P-rich layer is not formed at the interface between the metal body and the electroless Ni—P plating layer even if Sn-rich solder is used. Therefore, since the adhesive force between the metal body and the electroless Ni—P plating layer does not decrease, peeling of the electroless Ni—P plating layer can be prevented.
[0008]
According to invention of Claim 2, since the thickness dimension of the said electroless Ni-P plating layer was set to about 5 micrometers or more, peeling of an electroless Ni-P plating layer can be prevented. In addition, the present inventors have confirmed by experiments and trial production that peeling of the electroless Ni—P plating layer can be prevented if the thickness dimension of the electroless Ni—P plating layer is set to about 5 μm or more. is doing.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, FIG. 1 is a cross-sectional view showing a schematic configuration of the semiconductor device of this embodiment. As shown in FIG. 1, a semiconductor device 1 of this embodiment includes a semiconductor chip (semiconductor element) 2, a lower heat sink (metal body) 3, an upper heat sink (metal body) 4, and a heat sink block (metal body). ) 5.
[0010]
The semiconductor chip 2 is composed of a power semiconductor element such as an IGBT, MOSFET, or thyristor. In the case of this embodiment, the shape of the semiconductor chip 2 is, for example, a rectangular thin plate. The lower heat sink 3, the upper heat sink 4, and the heat sink block 5 are made of Cu, for example. Note that, instead of Cu, a metal having good thermal conductivity and electrical conductivity such as Al may be used.
[0011]
Furthermore, as shown in FIG. 2, an electroless Ni—P plating layer 6 is plated on the surfaces of the lower heat sink 3, the upper heat sink 4 and the heat sink block 5. And the thickness dimension of this electroless Ni-P plating layer 6 is set to about 5 micrometers or more in the case of a present Example.
[0012]
In the semiconductor device 1 having the above-described configuration, the lower surface of the semiconductor chip 2 and the upper surface of the lower heat sink 3 are bonded by, for example, solder 7 that is a bonding member. As the solder 7, Sn-rich solder (solder not containing Pb), for example, Sn—Sb brazing material is used. In place of the Sn—Sb brazing material, an Sn—Ag brazing material or an Sn—Cu—Ni brazing material may be used.
[0013]
The upper surface of the semiconductor chip 2 and the lower surface of the heat sink block 5 are also joined by the solder 7 made of the Sn—Sb brazing material. Further, the upper surface of the heat sink block 5 and the lower surface of the upper heat sink 4 are also joined by the solder 7 made of the Sn—Sb brazing material. The thickness dimension of each solder 7 is set to about 100 μm. By joining in this way, in the said structure, it is the structure which radiates heat | fever through the heat sinks 3 and 4 and the heat sink block 5 from both surfaces of the semiconductor chip 2. FIG.
[0014]
In the case of the above configuration, the lower heat sink 3 and the upper heat sink 4 are also electrically connected to each main electrode (for example, collector electrode, emitter electrode, etc.) of the semiconductor chip 2 via the solder 7.
[0015]
On the other hand, the control electrodes (eg, gate pads) of the semiconductor chip 2 are wire bonded to the lead frame 8 as shown in FIG. That is, for example, the control electrode of the semiconductor chip 2 and the lead frame 8 are connected by a wire 9 made of Al or Au.
[0016]
The lower heat sink 3 and the upper heat sink 4 are formed of a plate material having a thickness dimension of about 1 mm, and terminal portions 3a and 4a are provided so as to project from the plate. Further, the heat sink block 5 is a rectangular plate having a size slightly smaller than the semiconductor chip 2. Furthermore, in the case of the above configuration, the distance between the upper surface of the lower heat sink 3 and the lower surface of the upper heat sink 4 is configured to be about 1 to 2 mm, for example.
[0017]
As shown in FIG. 1, a resin (for example, epoxy resin) 10 is filled and sealed in the gap between the pair of heat sinks 3 and 4 and the peripheral portions of the chip 2 and the heat sink block 5. In the case of this configuration, when molding the heat sinks 3, 4, etc. with the resin 10, a molding die (not shown) composed of upper and lower molds is used. Moreover, in the case of the said structure, the resin molding is carried out so that the lower surface of the lower heat sink 3 and the upper surface of the upper heat sink 4 may each be exposed. Thereby, the heat dissipation of the heat sinks 3 and 4 is improved.
[0018]
Before the resin 10 is molded in order to increase the adhesion between the resin 10 and the heat sinks 3 and 4, the adhesion between the resin 10 and the semiconductor chip 2, and the adhesion between the resin 10 and the heat sink block 5. In addition, it is preferable to apply a coating resin such as polyamide resin (not shown) to the surfaces of the heat sinks 3 and 4, the heat sink block 5 and the chip 2.
[0019]
Further, specific examples of the manufacturing method (that is, the manufacturing process) of the semiconductor device 1 having the above-described configuration are described in Japanese Patent Application Nos. 2001-127516 and 2001-225963 filed by the present applicant. The methods described may be used as appropriate.
[0020]
Here, the reason why the thickness dimension of the electroless Ni—P plating layer 6 applied to the surfaces of the lower heat sink 3, the upper heat sink 4, and the heat sink block 5 is set to about 5 μm or more will be described.
[0021]
The inventors prototyped heat sinks 3, 4, and 5 in which the thickness dimension of the electroless Ni—P plating layer 6 was changed in units of 1 μm from 2 μm to 6 μm, and Sn—Sb brazing material (solder 7). After performing 2000 cycles of the thermal cycle test, an experiment (prototype) for examining the rate of occurrence of peeling of the electroless Ni—P plating layer 6 was performed. The experimental results are shown in FIG.
[0022]
From FIG. 3, when the thickness dimension of the electroless Ni—P plating layer 6 is set to about 5 μm or more, the peeling occurrence rate becomes 0. Therefore, the electroless Ni—P plating layer 6 (and thus the solder layer 7) It can be seen that peeling can be reliably prevented. In the graph of FIG. 3, the horizontal axis represents the thickness dimension of the electroless Ni—P plating layer 6, the vertical axis represents the separation occurrence rate, and the plot represents the prototype.
[0023]
Here, the present inventors use Sn—Sb-based brazing material (solder 7) for the heat sinks 3, 4 and 5 in which the thickness dimension of the electroless Ni—P plating layer 6 is set to about 5 μm or more. Then, the depth profile of the metal element at the interface between the heat sinks 3, 4, 5 and the solder 7 was measured. The measurement results are shown in FIG.
[0024]
In FIG. 4, Cu is a base material of the heat sink, Ni is a main component of the plating layer, P is an additive of the plating layer, Sn is a main component of the brazing material (solder), Sb is an additive material of brazing material (solder). According to FIG. 4 described above, Ni contained in the electroless Ni—P plating layer 6 is melted in the Sn—Sb brazing material 7 to produce a metal compound of Ni—Sn, and the electroless Ni—P plating layer. P is concentrated, and a P-rich layer (P-rich layer) is formed. This P-rich layer is an interface between the electroless Ni—P plating layer 6 and the heat sinks 3, 4, 5. Has not reached.
[0025]
For this reason, since a sound layer (layer before soldering) remains at the interface between the electroless Ni—P plating layer 6 and the heat sinks 3, 4, 5, the electroless Ni—P plating layer 6 and the heat sink Adhesive force between 3, 4, and 5 is maintained with sufficient strength. Therefore, when the thickness dimension of the electroless Ni—P plating layer 6 is set to about 5 μm or more (sufficiently thick), the electroless Ni—P plating layer does not peel off.
[0026]
Here, as a comparative example, soldering was performed using Sn—Sb brazing material (solder 7) on the heat sinks 3, 4, and 5 in which the thickness dimension of the electroless Ni—P plating layer 6 was set to 3 μm. With respect to the shimono, the depth profile of the metal element at the interface between the heat sinks 3, 4, 5 and the solder 7 was measured. The measurement results of this comparative example are shown in FIG.
[0027]
According to FIG. 5, the P-rich layer in the state where P contained in the electroless Ni—P plating layer 6 is concentrated reaches the interface between the electroless Ni—P plating layer 6 and the heat sinks 3, 4, 5. is doing. That is, the P-rich layer is entirely formed up to the interface between the electroless Ni—P plating layer 6 and the heat sinks 3, 4, and 5. In such a state, the adhesive force between the heat sinks 3, 4, 5 and the electroless Ni—P plating layer 6 is reduced, so that the electroless Ni—P plating layer 6 is peeled off.
[0028]
Incidentally, the thickness dimension of the electroless Ni—P plating layer 6 conventionally plated on the heat sink is about 1 to 2 μm, which is quite thin. The reason for reducing the thickness of the electroless Ni—P plating layer 6 in this way is to reduce the manufacturing cost. That is, if the thickness dimension of the electroless Ni—P plating layer 6 is reduced, the time required for the plating process can be shortened, and the productivity is improved accordingly.
[0029]
In the above embodiment, the thickness dimension of the electroless Ni—P plating layer 6 is set to about 5 μm or more. However, the thickness dimension of the electroless Ni—P plating layer is not limited to this. The thickness dimension that prevents the P-rich layer from reaching the interface between the electroless Ni-P plating layer and the electroless Ni-P plating layer may be obtained by experiment, trial manufacture, or the like, and set to the obtained thickness dimension.
[0030]
In the above-described embodiment, the semiconductor chip 2 is applied to the semiconductor device 1 having the structure in which the semiconductor chip 2 is sandwiched between the pair of heat sinks 3 and 4. However, the semiconductor chip is mounted on the upper surface of one heat sink and soldered. It may be applied.
[Brief description of the drawings]
FIG. 1 is a vertical cross-sectional view of a semiconductor device showing an embodiment of the present invention. FIG. 2 is an enlarged vertical cross-sectional view of a main part of the semiconductor device. FIG. FIG. 4 is a graph showing the depth profile of the metal element at the interface between the heat sink and the solder when the thickness dimension of the electroless Ni—P plating layer is sufficiently thick. FIG. Figure showing the metal element depth profile at the interface between the heat sink and the solder when the thickness of the plating layer is reduced.
1 is a semiconductor device, 2 is a semiconductor chip (semiconductor element), 3 is a lower heat sink (metal body), 4 is an upper heat sink (metal body), 5 is a heat sink block (metal body), and 6 is electroless Ni-P plating A layer, 7 is solder (Sn rich solder), and 10 is resin.

Claims (2)

表面に無電解Ｎｉ−Ｐめっき層がめっきされた金属体の上面に半導体素子をＳｎリッチ半田を介して接合してなり、前記半導体素子の全体並びに前記金属体の一部を除きその大部分を樹脂でモールドするように構成された半導体装置において、
前記無電解Ｎｉ−Ｐめっき層の厚み寸法を、前記金属体と前記無電解Ｎｉ−Ｐめっき層との界面に、半田付け時にＰリッチ層が到達しないようにする厚み寸法に構成したことを特徴とする半導体装置。A semiconductor element is joined to the upper surface of a metal body plated with an electroless Ni-P plating layer on the surface via Sn-rich solder, and most of the semiconductor element and a part of the metal body are excluded. In a semiconductor device configured to mold with resin ,
The thickness dimension of the electroless Ni—P plating layer is configured such that the P rich layer does not reach the interface between the metal body and the electroless Ni—P plating layer during soldering. A semiconductor device. 前記無電解Ｎｉ−Ｐめっき層の厚み寸法を、約５μｍ以上に設定したことを特徴とする請求項１記載の半導体装置。The semiconductor device according to claim 1, wherein a thickness dimension of the electroless Ni—P plating layer is set to about 5 μm or more.
JP2001368562A 2001-12-03 2001-12-03 Semiconductor device Expired - Lifetime JP3826776B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001368562A JP3826776B2 (en) 2001-12-03 2001-12-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001368562A JP3826776B2 (en) 2001-12-03 2001-12-03 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2003168771A JP2003168771A (en) 2003-06-13
JP3826776B2 true JP3826776B2 (en) 2006-09-27

Family

ID=19178136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001368562A Expired - Lifetime JP3826776B2 (en) 2001-12-03 2001-12-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3826776B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013015158A1 (en) * 2011-07-28 2013-01-31 電気化学工業株式会社 Heat dissipating component for semiconductor element

Also Published As

Publication number Publication date
JP2003168771A (en) 2003-06-13

Similar Documents

Publication Publication Date Title
US7400002B2 (en) MOSFET package
JP2001230360A (en) Semiconductor integrated circuit device and method of manufacturing the same
JP2014007363A (en) Method of manufacturing semiconductor device and semiconductor device
JPH11340409A (en) Lead frame and its manufacture and resin encapsulated semiconductor device and its manufacture
TW200522328A (en) Semiconductor device and manufacturing method thereof
JP2000223634A (en) Semiconductor device
CN104025287A (en) Semiconductor device
JP2003110064A (en) Semiconductor device
JP2018056451A (en) Semiconductor device
JP5125975B2 (en) Resin case manufacturing method
JP2023030046A (en) Semiconductor device and method for manufacturing the same
US20150262965A1 (en) Wire bonding method and structure
TWI745516B (en) Semiconductor device and manufacturing method thereof
JP3826776B2 (en) Semiconductor device
JP2012004594A (en) Semiconductor device
JP6653235B2 (en) Semiconductor device manufacturing method and semiconductor device
JPWO2020017574A1 (en) Semiconductor devices and methods for manufacturing semiconductor devices
WO2018018849A1 (en) Intelligent power module and method for manufacturing same
JP2017108191A (en) Semiconductor device
JP5017228B2 (en) Semiconductor device
JP4357492B2 (en) Semiconductor device
JP4357493B2 (en) Semiconductor device
JP3827442B2 (en) Manufacturing method of semiconductor package
JPH05145004A (en) Manufacture of semiconductor device
JP2005150602A (en) Semiconductor device

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040109

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040109

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20041005

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20051004

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051201

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060613

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060626

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 3826776

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090714

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100714

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110714

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120714

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130714

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term