JPS6052737U - BCH single error correction/double error detection code decoding circuit - Google Patents
BCH single error correction/double error detection code decoding circuitInfo
- Publication number
- JPS6052737U JPS6052737U JP14451783U JP14451783U JPS6052737U JP S6052737 U JPS6052737 U JP S6052737U JP 14451783 U JP14451783 U JP 14451783U JP 14451783 U JP14451783 U JP 14451783U JP S6052737 U JPS6052737 U JP S6052737U
- Authority
- JP
- Japan
- Prior art keywords
- bch
- code decoding
- decoding circuit
- detection code
- correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のＢＣＨ３ＥＣ−ＤＥＤ符号復号化回路を
示すブロック図。第２図は本考案の一実施例の構成を示
すブロック図。
１および３・・・計算回路、２・・・シリアルーパラレ
、ル変換回路、４・・・検出回路、７・・・ラッチ回路
、１０・・・ラッチ回路、１３・・・パターン検出回路
。FIG. 1 is a block diagram showing a conventional BCH3EC-DED code decoding circuit. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. 1 and 3... Calculation circuit, 2... Serial-to-parallel conversion circuit, 4... Detection circuit, 7... Latch circuit, 10... Latch circuit, 13... Pattern detection circuit.
Claims (1)
的に前値保持する補正手段を備えたＢＣＨ単−誤り訂正
・二重誤り検出符号復号化回路において、出力されるべ
き情報ビットのビットパターンが不必要なビットパター
ンであることを検出するパターン検出回路と、訂正動作
および非訂正動作にかかわらず優先して前記パターン検
出回路の出力により前記補正手段を駆動する駆動手段と
を備えてなることを特徴とするＢＣＨ単−誤り訂正・二
重誤り検出符号復号化回路。In a BCH single-error correction/double error detection code decoding circuit equipped with a correction means for selectively retaining the previous value of the information bits to be output in the information bits of one frame before, the bit pattern of the information bits to be output is A pattern detection circuit for detecting an unnecessary bit pattern, and a driving means for driving the correction means with the output of the pattern detection circuit with priority regardless of correction operation or non-correction operation. A BCH single error correction/double error detection code decoding circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14451783U JPS6052737U (en) | 1983-09-20 | 1983-09-20 | BCH single error correction/double error detection code decoding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14451783U JPS6052737U (en) | 1983-09-20 | 1983-09-20 | BCH single error correction/double error detection code decoding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6052737U true JPS6052737U (en) | 1985-04-13 |
| JPH0138998Y2 JPH0138998Y2 (en) | 1989-11-21 |
Family
ID=30322251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14451783U Granted JPS6052737U (en) | 1983-09-20 | 1983-09-20 | BCH single error correction/double error detection code decoding circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052737U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0389630A (en) * | 1989-08-31 | 1991-04-15 | Matsushita Electric Ind Co Ltd | Error correcting method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5381223A (en) * | 1976-12-27 | 1978-07-18 | Matsushita Electric Ind Co Ltd | Signal error detecting and correcting system |
| JPS55157114A (en) * | 1979-05-23 | 1980-12-06 | Matsushita Electric Ind Co Ltd | Muting circuit |
| JPS5725048A (en) * | 1980-07-23 | 1982-02-09 | Fujitsu Ltd | Memory error check and control system |
-
1983
- 1983-09-20 JP JP14451783U patent/JPS6052737U/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5381223A (en) * | 1976-12-27 | 1978-07-18 | Matsushita Electric Ind Co Ltd | Signal error detecting and correcting system |
| JPS55157114A (en) * | 1979-05-23 | 1980-12-06 | Matsushita Electric Ind Co Ltd | Muting circuit |
| JPS5725048A (en) * | 1980-07-23 | 1982-02-09 | Fujitsu Ltd | Memory error check and control system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0389630A (en) * | 1989-08-31 | 1991-04-15 | Matsushita Electric Ind Co Ltd | Error correcting method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0138998Y2 (en) | 1989-11-21 |
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