JPS6052731U - pulse modulation circuit - Google Patents

pulse modulation circuit

Info

Publication number
JPS6052731U
JPS6052731U JP14492783U JP14492783U JPS6052731U JP S6052731 U JPS6052731 U JP S6052731U JP 14492783 U JP14492783 U JP 14492783U JP 14492783 U JP14492783 U JP 14492783U JP S6052731 U JPS6052731 U JP S6052731U
Authority
JP
Japan
Prior art keywords
circuit
pulse modulation
modulation circuit
operational amplifier
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14492783U
Other languages
Japanese (ja)
Inventor
杉田　朗
Original Assignee
昌栄電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昌栄電機株式会社 filed Critical 昌栄電機株式会社
Priority to JP14492783U priority Critical patent/JPS6052731U/en
Publication of JPS6052731U publication Critical patent/JPS6052731U/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本箸案の一実施例を示す図、第２図乃至第４
図は、その作動説明のための波形図で、Ｔｉ：入力端子
、Ｔｏ：出力端子、Ｔｃ・・・共通端子、Ｔや及びＴ−
：電源接続端子、０ＰＡＩ及び０ＰＡ２　：演算増幅器
、Ｃ■：積分コンデンサ、Ｒ１ないしＲ４：入力抵抗、
Ｒ５：電流制限抵抗、ｚＤ：ツェナダイオード、ＤＩな
いしＤ４：ダイオードである。Figure 1 is a diagram showing an example of the proposed chopsticks, Figures 2 to 4
The figure is a waveform diagram for explaining its operation, where Ti: input terminal, To: output terminal, Tc...common terminal, T and T-.
: Power supply connection terminal, 0PAI and 0PA2 : Operational amplifier, C■: Integrating capacitor, R1 to R4: Input resistance,
R5: current limiting resistor, zD: Zener diode, DI to D4: diodes.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 演算増幅器より成る積分回路及びこの積分回路出力の導
入される比較回路より成るパルス発振回路と、前記演算
増幅器の反転入力端子に変調信号を加える入力回路とよ
り成ることを特徴とするパルス変調回路。1. A pulse modulation circuit comprising: a pulse oscillation circuit comprising an integrating circuit comprising an operational amplifier; a comparing circuit into which the output of the integrating circuit is introduced; and an input circuit applying a modulation signal to an inverting input terminal of the operational amplifier.
JP14492783U 1983-09-19 1983-09-19 pulse modulation circuit Pending JPS6052731U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14492783U JPS6052731U (en) 1983-09-19 1983-09-19 pulse modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14492783U JPS6052731U (en) 1983-09-19 1983-09-19 pulse modulation circuit

Publications (1)

Publication Number Publication Date
JPS6052731U true JPS6052731U (en) 1985-04-13

Family

ID=30323047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14492783U Pending JPS6052731U (en) 1983-09-19 1983-09-19 pulse modulation circuit

Country Status (1)

Country Link
JP (1) JPS6052731U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501618A (en) * 1973-05-04 1975-01-09
JPS56122523A (en) * 1980-03-03 1981-09-26 Mitsubishi Electric Corp Pulse width modulating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501618A (en) * 1973-05-04 1975-01-09
JPS56122523A (en) * 1980-03-03 1981-09-26 Mitsubishi Electric Corp Pulse width modulating circuit

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