JPS6051712B2 - raster scan display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a raster scan type display device.

Currently, there are many display devices in use that use the so-called raster scan method, which has an image memory corresponding to each pixel, and reads coded data written in the image memory while synchronizing with various synchronization signals and converts it into a video signal. .

These devices have a binary counter that operates with a reference clock, and are configured to use the output of the binary counter to address a pixel memory and to create a synchronizing signal system via gates. When a color signal is used, the gates become quite complex in order to generate the generation period of the horizontal synchronizing pulse, the burst signal, the front porch and back porch signals from the binary counter output through the gates.
When a ripple counter is used as a binary counter, it is necessary to consider time delays and other factors, which cannot be realized with a simple logic circuit. Furthermore, once the timing of each synchronization signal is determined, the timing cannot be adjusted unless the hardware configuration is significantly changed. The present invention eliminates these drawbacks, allows easy creation of a synchronization signal system, and eliminates synchronization signal ties. The purpose of this invention is to provide a device that can be easily modified and has various functions.

Hereinafter, the present invention will be explained based on illustrated embodiments.

In FIG. 1, 1 is a processor, 2 is an image processor. This memory temporarily stores coded data at addresses corresponding to pixels.

Coded data is written into the image memory 2 according to the judgment and instructions of the processor 1. On the other hand, reading from the image memory 2 is carried out by using the output signal of the address counter 4 operated by the output from the reference clock signal generator 3 as the address signal of the image memory 2.

The address counter 4 is a binary counter, has a bit number that can correspond to the entire screen of the display device, and is reset every time one field is scanned. Address conversion for writing from the processor 1 to the image memory 2 and reading from the address counter 4 from the image memory 2 is performed via the multiplexer 5. Writing to the image memory 2 is executed during a period that does not affect reading of the image signal, but at this time the multiplexer 5 is switched. The output of the address counter 4 is further input to a horizontal synchronization system gate signal generator 6.

In the case of a color display, the horizontal synchronization signal includes a horizontal synchronization pulse, a burst signal, a pedestal level corresponding signal, and the like.

The horizontal synchronization system gate signal generator 6 generates pulses corresponding to the entire period during which the horizontal synchronization system signal is output.
The coded data output from the image memory 2 is distributed to the video signal processing circuit 8 and the horizontal synchronization signal conversion circuit 9 by the data switch 7 which is switched depending on the output state of the horizontal synchronization system gate signal generator 6. Ru. When the output pulse of the horizontal synchronous gate signal generator 6 is off, the video signal processing circuit 8 takes in the output from the image memory 2 and outputs coded data as a video signal. The horizontal synchronization system signal conversion circuit 9 takes in the output from the image memory 2 when the output pulse of the horizontal synchronization system gate signal generator 6 is on, and converts the coded data into horizontal synchronization pulses, burst signals, pedestal level corresponding signals, etc. Convert and output. For example, when the image memory 2 is composed of 2 bits in parallel, the coded data is the horizontal synchronization pulse at Rl,L, the burst signal at Rl, OJ, and the pedestal level corresponding signal at r'0,0yo. The signal is generated from the signal conversion circuit 9. FIGS. 2A, 2B, and 2C are diagrams respectively showing the storage position of the horizontal synchronizing signal in the image memory 2, the corresponding output pulse waveform of the horizontal synchronizing system gate signal generator 6, and the combined video signal waveform.

The image memory 2 sequentially outputs data at the address indicated by the output of the address counter 4. The image memo IJ2 is accessed from left to right every horizontal scan.

22 is a horizontal synchronizing pulse, 24 is a burst signal, 21
, 23 and 25 store coded data that can be generated when the pedestal level is passed through the horizontal synchronization system signal conversion circuit 9.

The coded data stored in the image memory 2 can be used as an input signal of the video signal processing circuit 8 or as an input signal of the horizontal synchronization signal conversion circuit 9 depending on the output state of the horizontal synchronization system gate signal generator 6. I feel relaxed. The composite video signal waveform of the video signal and the synchronization signal is shown in FIG. 2C. According to the present invention, the synchronization signal pulses generated from the address counter 4 via the gates are only generated by the horizontal synchronization system gate signal generator 6, and each of the horizontal synchronization pulses, burst signals, pedestal level corresponding signals, etc. Since the generation timing is determined by the data in the image memory 2, it can be realized with a simple circuit.

Data for horizontal synchronization signals in the image memory 2 can be written and erased via the processor 1 in the same way as video data.

Various functions can be implemented by lengthening the ON period of the output pulse of the horizontal synchronization system gate signal generator 6 and moving the data storage position of the horizontal synchronization system signal in the image memory 2 within the period during which the output pulse is ON. It can be added. By uniformly shifting the data storage position of the horizontal synchronization signal to the left and right, the overall position of the image will shift accordingly, making it possible to easily adjust the image position. If you do this, you can generate vibrations in the image. Furthermore, by changing the data storage position of the horizontal synchronization signal with respect to the horizontal scanning line, it is also possible to generate distortion in the horizontal direction of the image. Although these can be achieved by completely rewriting the video data, the method according to the present invention is much simpler and the rewriting speed is faster. Note that although only the horizontal synchronization system signal has been described above, a similar configuration can be applied to the vertical synchronization system signal as well. Of course, the aforementioned methods of adjusting the image position and vibrating the image are also effective when applied to vertical synchronization signals. Note that when the synchronization signal is created using data in the image memory, if the data in the image memory is destroyed by noise, the synchronization signal will be disturbed thereafter.

Therefore, such a case can be dealt with by repeatedly writing coded data to a predetermined location in the image memory.
Further, although this embodiment deals with signals for a color display, it can be similarly implemented for a monochrome display.

Furthermore, instead of a system using a processor, writing to the image memory may be performed using other well-known means.
Further, the image memory does not necessarily have to correspond to the entire display screen, but it is also effective to correspond to a portion of the screen, for example, several scanning lines, and to constantly update the data.

[Brief explanation of drawings]

Fig. 1 is a block diagram of main parts of an embodiment of the present invention, Fig. 2A
, B, and C are diagrams showing signal storage positions and signal waveforms at various parts in the image memory of the same embodiment. DESCRIPTION OF SYMBOLS 1... Processor, 2... Image memory, 3... Reference clock signal generator, 4... Address counter, 5
...Multiplexer, 6...Horizontal synchronization system gate signal generator, 7...Data switcher, 8...Video signal processing circuit, 9...Horizontal synchronization system signal conversion circuit.

Claims (1)

[Scope of Claims] An image memory corresponding to one pixel, an address counter operated by a reference clock signal, a synchronous gate signal generator operated by the output of the address counter, and an output of the synchronous gate signal generator. and a synchronous system signal conversion circuit operated by the synchronous system gate, which specifies the address of the image memory using the output of the address counter, sequentially outputs the coded data stored in the image memory, and operates the synchronous system gate. When the output of the signal generator is off, the coded data is processed as a video signal, and when the output of the synchronous gate signal generator is on, the coded data is processed through the synchronous signal conversion circuit. What is claimed is: 1. A raster scan display device, characterized in that the raster scan display device is configured to convert a signal into a synchronous signal. 2. In the description of claim 1, the synchronization system gate signal generator generates a horizontal synchronization system gate signal that generates a signal corresponding to the entire signal period of the horizontal synchronization system, such as a horizontal synchronization pulse and a signal corresponding to a pedestal level. The synchronous system signal conversion circuit is configured as a generator, and the synchronous system signal conversion circuit is configured with a horizontal synchronous system signal conversion circuit operated by the output of the horizontal synchronous system gate signal generator, and the output of the horizontal synchronous system gate signal generator is When the output of the horizontal synchronization system gate signal generator is off, the coded data is processed as a video signal, and when the output of the horizontal synchronization system gate signal generator is on, the coded data is processed as a horizontal synchronization pulse, A raster scan display device characterized in that it is configured to be converted into a horizontal synchronous signal such as a pedestal level compatible signal. 3. In the description of claim 1, the code is stored in the image memory and is converted into a synchronous signal via the synchronous signal conversion circuit when the output of the synchronous gate signal generator is on. A raster scan display device characterized in that the entire position of the image memory can be adjusted by uniformly shifting the storage position of the image data in the image memory. 4. In the description of claim 1, the code is stored in the image memory and is converted into a synchronous signal via the synchronous signal conversion circuit when the output of the synchronous gate signal generator is on. 1. A raster scan display device, characterized in that the raster scan display device is configured to generate vibrations in the image memory by temporally changing the storage position of the image data in the image memory. 5. In the description of claim 2, the image data is stored in the image memory and converted into a horizontal synchronization signal via the horizontal synchronization signal conversion circuit when the output of the horizontal synchronization gate signal generator is on. A raster scan display, characterized in that the raster scan display is configured to generate distortion in the horizontal direction of the image by changing the storage position of the encoded data in the image memory with respect to the horizontal scanning line. Device. 6. In the description of claim 1, the code is stored in the image memory and is converted into a synchronous signal via the synchronous signal conversion circuit when the output of the synchronous gate signal generator is on. 1. A raster scan display device, characterized in that it is configured to repeatedly write converted data to a predetermined location.