JPS605686A - Memory device - Google Patents

Abstract

PURPOSE:To obtain an economical memory device by storing the sound of a television broadcast in conm with the sound of a microphone to a memory storing a video signal. CONSTITUTION:Whether a signal to be stored is a sound of a television broadcast or an input of a microphone is selected by a switch 22. A timing generating circuit 13 generates a sound sampling clock and this signal is applied to a memory 15 via a sound/video changeover switch 24. The refreshment at sound recording is executed by using an address at video signal recording as it is. To read the recorded sound, a 6-bit parallel signal produced by applying serial conversion to a 10-bit parallel signal at each bit is supplied to a sound demodulating section 26 via the sound/video selecting switch 25 at the post-stage, the 6-bit parallel signal is converted into a serial signal and also the digital modulation is decoded and an analog sound signal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is intended to record a video signal in a memory, reproduce it, and display it on a cathode ray tube.It is an object of the present invention to record and reproduce memory audio in a memory device.

Stop TV, which cuts out one screen of a television broadcast and freezes the screen, or transmits information using part of the vertical blanking period, and combines the signals of multiple vertical blanking periods for one screen. A teletext receiver that displays text and graphic information on a picture tube requires a memory for at least one screen, and some use a semiconductor memory or the like as the memory. An example of the memory capacity of such a receiver is 960 bits for stop television and 64 bits for a teletext receiver.
That's a bit.

The present invention is intended to enable a television receiver or an adderfree equipped with such a memory to be used as a memory for storing the audio of the television broadcast or the audio input from the microphone. .

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a television signal received by an antenna 1 is supplied to a video detector 4 through a tuner 2, a video intermediate frequency amplifier 3, and a switch 6. The luminance signal processing circuit 6 and color signal demodulation circuit 8 convert the signal into a predetermined signal and supply it to the picture tube drive circuit 7 to drive the picture tube 10. On the other hand, the deflection circuit 9 generates phase-matched vertical and horizontal scanning signals.
” is supplied to the coil 11. More notes +7 Bronok 12
, a timing generation circuit 13, and AD converters 14 and 16 that convert analog video signals into digital signals.
It consists of a memory section 15 mainly consisting of a bit random access memory, and a DA converter 16 that converts the digital signal into the original analog video signal and also shapes the horizontal and vertical synchronization signals as necessary.

Next, the audio part will be explained. From the video detector 4 through the audio intermediate frequency amplifier and detector 17, the switch 18
The signal is supplied to the audio amplifier 19 via the audio amplifier 19 to drive the speaker 20. Audio output of video detector 4 and microphone 21
The output of the modulator 23 is switched by a changeover switch 22 and applied to the modulation unit 23, and the output of the modulation unit 23 is applied to the memory unit 16 via a changeover switch 24. The output of the memory section 16 is applied to the demodulation section 26 via the changeover switch 25, and the demodulated signal is applied to the changeover switch 18. The control circuit 28 is operated by operating the switch group 27, and each switch 6, 18
, 22 , 24 , and 26 and controls the timing generation circuit.

First, processing of video signals will be explained. The video signal detected by the video detector 4 is input to a timing generation circuit 13 and an Al converter 14. The timing generation circuit 13 generates a vertical synchronization signal of the video signal.

Based on the horizontal synchronization signal, Carano (-) signal, the sampling clock for AD conversion, the memory address,
Timing signals for memory control, including memory read/write signals, etc.

Occurs. In the AD converter 14, after clamping the video signal, for example, 37 seconds (fs is the number of color subcarriers, approximately 3
．． 5a MHz) and PGM (Pulse Coat Modulation) K, J:,! 2
For example, it is a 6-bit digital signal. This faith 2J'
is supplied to the memory section 15 via the audio/video changeover switch 24 in the previous stage. The memory has a capacity of 160 bits for each bit of the 6-bit signal, and this 1eoK bit is made up of ten 16-bit dynamic random access memories (RAMs) connected in parallel.

To explain in detail with reference to FIG. 2, the third bit data is converted into a 10-bit parallel signal by the serial/parallel conversion circuit 62c through the terminal SVC, and is stored in each of the memories 66 to 66 constituting the memory SSC. do. 3
When sampling with /S, the third
As shown in the figure, 682.6 samples are performed, but parts before and after the horizontal synchronization signal are discarded, and 640 samples of data are stored in the memory 63G. In FIG. 3, 42 samples are discarded from the horizontal synchronization front porch and the remaining 640 samples are stored in memory. In order to convert the data from serial to parallel as described above, each of the 16-bit memories stores data for 64 samples per 1H, and this becomes 64×256=16384 for 256H, making the 16-bit memories exactly full. That is, the vertical direction 26
Memory for 6H.

If a dynamic memory is used as the 16-bit memory, it is necessary to refresh the data at predetermined intervals, but if the memory has a 7-bit matrix configuration and can be refreshed by specifying only the "column", the column address will change from O to 1H in the 1H. 63.2H
It goes from 64 to 127 in the 3rd hour, and goes back to 0 to 63 in the 3rd H. Therefore, refresh can be performed every 2 hours.

When reading the data stored in the memory in this way, the 10-bit parallel data is serialized at a predetermined timing by the address parallel-to-serial conversion circuit 64C, and the subsequent audio/video selection switch 26 is connected to the terminal 66G. The 6-bit PGM signal is sent to the DA converter 6 via the analog video (G). At this time, as mentioned above, it is necessary to reproduce the part that was discarded in the horizontal and vertical synchronization parts, and The video selection switch 5 determines whether to display the broadcast signal or the stored still signal on the picture tube.

Next, a description will be given of how the memory having the above configuration is also used for recording audio. Whether the signal to be recorded is the sound of television broadcasting or the input of the microphone 1 is selected by the audio signal source selector switch I22. A timing generation circuit 13 generates an audio sampling clock. - For example, sampling is performed at the TV horizontal frequency /H (approximately 15.76 KH2) and coding is performed using delta modulation. In this method, one pulse is generated every 1H (approximately 63.6 μs). This is serial-parallel converted into a 6-bit parallel signal.

These processes are performed by the audio modulation section 33.

This signal is supplied to the memory section 16 via the audio/video changeover switch 24 at the previous stage. In the memory section 15, as in the case of video, each 1 bit frJ of 6 bits is stored in parallel, and further:
It is converted into a 10-bit parallel signal and recorded in a 16-bit memory. In this way, one piece of data is written into each of the 6o 16-bit memories every 6×10=60H.

This data writing is performed during "A" of the 42 samples shown in FIG. 4 in which video is not recorded, and refresh is performed at the same address used for video during other periods. Therefore, the timing generation circuit 13 has two systems of address generation circuits, one of which is used for read/write refresh during video recording (- and a Frenonyu 7 trace for audio recording), and the other is used for read/write refresh during video recording, and the other is for audio recording. This is the read/write address at the time of .By the above means, it is possible to perform refreshing during audio recording by using the refreshing address during video recording as is.

To read out the recorded audio, a 6-bit parallel signal obtained by converting a 10-bit parallel signal into a serial signal is sent to the audio demodulator 26 via the audio/video selection switch 25 in the subsequent stage.
It converts the 6-bit parallel signal into a serial signal, and at the same time decodes the delta modulation to create an analog audio signal. The output from the speaker 20 is performed by the audio selection switch 18. Note that all timing signals are supplied in parallel to the 60 memories.

Commands such as whether to record audio or video, playback thereof, record microphone input, or record the audio signal of television broadcasting are issued by the switch group 27, and a circuit system based on these commands is issued. A control signal is generated by the control circuit 28.

The audio selection switch 18, the video selection switch 5, the audio video selection switches 24, 26, etc. are electronically opened and closed based on the output of the control circuit 28. In addition, in the case of stomp television, the video is recorded for one field, and the audio is recorded for 60 seconds. Such timing signals, which differ depending on whether video recording or audio recording, are generated in the timing circuit 13 according to instructions from the control circuit 28.

Similarly, in the case of a teletext receiver, the memory for storing text information can also be used as the memory for recording audio. If 64 has a bit capacity, 16 bits of memory 15 will be 4
Let's consider the case of .

The timing for recording character information is different from that for recording broadcast signals, and the timing for recording character information is different from that for recording broadcast signals.
In the example, only 1H minutes) are recorded in one field, but the readout and refresh timings are the same, and audio recording and playback are also exactly the same. In the example, 1 is used as memory.
6 is explained using a bit dynamic ram, a static ram may also be used, and audio coding can be done by PCM or other appropriate means, limited to delta modulation.

As described above, according to the present invention, an economical memory device can be obtained since the memory for recording video signals is also used for storing audio signals.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention, FIG. 2 is a block diagram of a memory section of the memory device, and FIG. 3 is a waveform diagram for explaining the device. 1...Antenna, 2...-Chew, 3.
・1F amplifier, 5, 24, 25, 22, 18
・All changeover switch, 1o...Cathode ray tube, 20...
...Speaker, 13...Timing generation circuit, -
14... AD converter 1', 16... memory section,
16...DA converter, 23...Modulation section,
21...Microphone, 27...Switch group, 28...Control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3

Claims (1)

[Claims] Record video signals such as television broadcast signals in memory,
means for reproducing this and displaying it on a cathode ray tube screen; and recording an audio signal such as an audio signal in the television broadcast signal or an audio signal from a microphone in the memory;
A memory device comprising a means for reproducing and emitting sound, and a switching means for switching between the two means.