JPS605120B2 - Information scanning processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention autonomously scans a plurality of scanning points, stores the scanning results in a temporary storage memory, and when a final reading request is received from a central controller, the temporary storage memory The present invention relates to an information scanning processing system configured to transfer data of data to a central control unit.

FIG. 1 shows a conventional example of an information scanning processing method for a stored program electronic exchanger.

In FIG. 1, 1 is a central control device, 2 is a signal reception distribution device, 3 is a main scanning control device, 41 is a secondary scanning control device, and 5 is a main scanning control device.
indicate the scanning matrices, respectively. The central control device 1 performs various controls based on programs. Various control signals from the central control device 1 are sent to the signal reception and distribution device 2 through a control line 6. Signal reception distribution device 2
receives the control signal, decodes it, checks for errors, and distributes the control signal to the various control devices concerned. In addition to the control layer shown in FIG. 1, the storage program electronic exchanger is provided with a switch control, a relay groove controller (not shown), and the like. The scanning matrix 5 is composed of contacts, diodes, resistors, etc., and is used to detect call origination, monitor the call status, and detect selection signals. Each of the parent scan control devices has a memory device, a memory control section, a clock scan control section, a counter, etc. inside. Each parent scan control device 3 has a plurality of child scan control devices. A device 4 is provided, one scanning matrix 6 for each thousand-scan control device 4.

The child scan control device 4 converts the level of the scan signal selected from the parent scan control device 3 to drive the scan matrix 5, and also converts the level of the status information read from the scan matrix 5 to drive the scan signal selected from the parent scan control device 3. The parent scanning control device 3 sequentially stores the status information of the scanning points in an internal memory device.The scanning of the scanning matrix S is carried out autonomously independently of the central control device 1. When a reading request signal, which is one of the communication path system control commands, is sent from the central control device 1, the signal receiving and distributing device 2 receives the discussion request signal, decodes it, performs various error checks, and then processes the signal. An argument request signal is sent to the corresponding parent scanning control device 3 via line 7.

The communication line system control command is, for example, a 32-bit parallel signal, and includes device specification "address information, etc." Note that the control signal specifies the parent scanning control device, or is a relay controller or Identification as to whether a switch controller is specified can be made using 1 or 2 bits in the parallel signal.The parent scanning control device 3 that receives the transaction request signal sets the memory device in its own device to the “read mode”. This is changed and the read data is sent to the central control unit 1 via the signal lines 8 and 9.By the way, the signal receiving and distributing unit 2 performs ``reception, decoding, and various error checks, so the discussion is interrupted. A considerable amount of time is required between receiving the request signal and sending it out.Then, as mentioned above, the main scanning control device 3 receives the above-mentioned read request signal and then switches the memory device to the read mode. Therefore, the conventional method shown in FIG. 1 has the disadvantage that the access time required from when the central controller 1 sends the discussion request signal to when it receives the discussion data is longer. The present invention is based on the above considerations and aims to shorten the substantial access time seen from a central control unit in an information scanning processing system that employs an autonomous scanning system.

Therefore, the information scanning processing method of the present invention includes a scanning section that autonomously scans a plurality of scanning points and has a memory device into which the scanning results are written, and sends out a negotiation request signal that specifies at least the scanning section. In an information scanning processing method comprising a central control unit and a signal reception and distribution device that receives a control signal from the central processing unit and distributes the discussion request signal to the corresponding scanning unit, the signal reception and distribution device When it receives a memory bidding request signal from the central control unit, it immediately sends a memory bidding request presence signal indicating that the memory bidding request signal exists to the scanning unit, and then The present invention is characterized in that it is configured to send detailed information to the scanning unit designated by the memory negotiation request signal.Hereinafter, the present invention will be explained with reference to the drawings. The figure shows an outline of one embodiment of the present invention, and shows a signal line up to 10' for transmitting a discussion request presence signal indicating that a memory discussion request signal is present.

Note that the same reference numerals as in FIG. 1 indicate the same parts. FIG. 3 shows the signal receiving and distributing device 2 in detail.
is a judgment circuit, turtle 2 is a decoder, box 3 is a parity check circuit, 14 is a 1/N check circuit, 15 is a decoder,
16 is a 1/X check circuit, and 17 and 1 crab are AND circuits. Note that the signal lines 8 and 9 are omitted. The determination circuit 11 determines whether the control signal from the central control device 1 specifies the parent scanning control device 3 or not. It is broadly classified into whether the Ikebukuro layer is specified, such as a controller or a relay controller. Decoder 2 "distributes control signals to one control device.
As mentioned earlier, it is determined whether the control signal specifies the parent scanning control device 3 or the scanning device by checking one or two bits of the 32-bit control signal, for example.
It can be easily identified by bits. The 1/N check circuit 14 checks the normality of the device by detecting whether a signal is generated on only one of the output lines of the decoder.

The decoder 15 operates in substantially the same manner as the decoder 2, and the 1/X check circuit 16 operates in substantially the same manner as the 1/N check circuit 14. FIG. 4 shows a normal scanning cycle, each cycle consisting of a write period W and a read period R.

SCNO indicates the scan cycle for the 0th scan matrix 5, and SCNn indicates the scan cycle for the n-th scan matrix 5. In each write cycle W, the scan results are written to a memory device within the parent scan control device 3. Next, the operation of the apparatus shown in FIG. 3 will be explained.

When a control signal is sent from the central controller 1 via the control line 6, the determination circuit 11 determines whether the control signal is a memory reservation request signal, and if it is a memory reservation request signal. , immediately sends an argument request presence signal to all parent scanning control devices 3. A control signal (in this case a memory negotiation request signal) is decoded by a decoder 2 which issues a signal on one output line. At this time, various checks are performed by the check circuits 13 and 16, and if all the checks are good, the AND circuit 18 outputs logic "1". When the output of AND circuit 18 is logic "1", AND circuit 17 is opened and "
Detailed information such as discussion address information is notified to the parent scanning control device 3 specified by the discussion request signal. The corresponding parent scanning controller 3 retrieves the data from the memory device in the eye device and transfers this read data to the central controller 1. FIG. 5A explains the operation when the negotiation request presence signal occurs during the write period W. In this case, the order of the write period W and the discussion period R of the scan cycle is not changed, and data is retrieved from the memory device in the read period R when detailed information is notified. Note that in FIG. 5, the write cycle W and the read cycle R are equal, and the time required for the signal reception and distribution device 2 to receive and distribute a control device such as a read request signal is It is assumed that the period W or the discussion period R is equal. FIG. 5 shows the case where the read request presence signal occurs during the read period R. In this case, ``All parent scanning control devices 3 change the writing period W which would normally be the writing period W to the planning period R' and wait for detailed information to be notified. Specified by the read request signal. The parent scanning control device 3 is
When detailed information is received, the data is immediately retrieved from the memory device within the device itself and transferred to the central control device 1. In the conventional method, for example, as shown in FIG.
When the signal reception and distribution device 2 receives a discussion request signal in the write cycle W of CNi, the discussion request is notified to the corresponding parent scanning control device 3 in the read cycle R of the scan cycle SCNi. However, since the parent scan control device 3 starts operating from this point, it is not possible to obtain discussion data from the memory during the discussion period R of the scan cycle SCNi. Therefore, the relevant parent scanning control device 3 changes the next write cycle W to the read cycle R, and changes the next write cycle W to the read cycle R.
The controller 1 reads data from the memory device and transfers this data to the central controller 1. As can be seen from the above description, according to the present invention, the substantial access time seen from the central control device 1 can be shortened. FIG. 6 shows switching means for switching between the write cycle W and the read cycle R.

In the figure, R/D is read data, R/0 is a read request presence signal, R/W is a write designation input terminal for the memory, a memory device provided in the Futagawa main scan control device 3, and an FFI.
Or FF3 is a flip-flop, "21 none, 2
5 are AND circuits, 26 and 27 are NOR circuits, 28
None and 37 represent NAND circuits, and 38 represents a time delay circuit, respectively. The write designation signal is logic "1" (/-level) during read operation and logic "0" during write operation.
(low level). In addition, W.DATA is write data that corresponds to detection information from the scanning matrix 5, and ROADRS is address information and W.ADR.
S is write address information, W pulse is write signal, PL
A and PLB each represent a periodic repeating control signal whose phases are mutually synchronized, and CLI to CL3 each represent a clock. The operation of the configuration shown in FIG. 6 will be explained with reference to the time chart shown in FIG.

Signals PLA and PLB are control signals that have a mutually common relationship as shown in FIG.
Clock CL2 is emitted at the falling edge of signal PLB, and clock CL3 is emitted at the falling edge of signal PLB.
It is emitted in combination with L2.

Further, the write signal "W pulse" is applied as shown in FIG. 7B immediately before each of the signals PLA and PLB rises.
In FIG. 7, it is shown that there is a read cycle R period when the main button signal PLA is at a high level. In the state where the negotiation request presence signal R.0 from the signal reception distribution device 2 is not present, the flip-flop FFI
is in a reset state.

Therefore, the signal PLB is input to the AND circuit 25 and the NOR circuit 27.
, passes through the NAND circuit 30. Therefore, in the memory device 20, when the signal PLB is at a high level, it is a write cycle, and when the signal PLB is at a low level, it is a discussion cycle. Then, during the write period, the detection information from the scan matrix 5 is written into the memory device 20. In this state, if the discussion request presence signal #OR.0 is issued in the current write cycle as shown in FIG. 7, the flip-flop FFI is still maintained in the reset state.

Therefore, the signal PLB passes through the NAND circuit 30, and the write cycle W and read cycle R are not switched. In this state, read address information R.ADRS is supplied to the memory device 201 in the read period R, and the written detection information is extracted and output from the AND circuit 23. Next, if the read request presence signal #IR.0 is issued in the read period R, the flip-flop F
FI is set in synchronization with clock CLI. Therefore, the signal PLA now passes through the NAND circuit 30, and the write cycle and read cycle are switched. Even in the discussion cycle caused by this switching, the discussion address R.
Since ADRS is applied and AND circuit 23 is also turned on, the read detection information is transferred to the central controller side. In the period indicated as "return" in FIG. 7, flip-flop FFI is reset. For this reason, when the signal PLA is at the /.-- level again, the discussion cycle is resumed. ◎Han9
■Hada■nu■■Mom◎ is the following belief. ◎：CLI
This is a control signal that is generated when R.0 and R.0 overlap, and is used internally.

■: This is a control signal that is output when CL2 and R.0 overlap, and is used internally.

■: This is a signal that gives an address to the memory.

■: This is a signal that gives a write address to the memory.

■: Lecture data sending timing signal.

■: Write designation signal for memory. ■:CL3
This is a control signal that is generated when R.0 and R.0 overlap, and is used internally. ◎: Data read timing signal. In addition, all the signals are logic "1" and high level, and logic "1" is high level, and logic "1" is high level.
0", which is a low level.

As is clear from the above description, according to the present invention, when the signal reception and distribution device receives the discussion request signal, it immediately notifies the parent scanning control device of the existence of the discussion request. The scan controller can preliminarily control the memory device to enter a negotiation mode, thereby reducing the effective memory access time seen by the central controller.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional example of an information scanning processing method;
Figure 3 is a block diagram of an embodiment of the present invention, Figure 3 is a block diagram of an embodiment of the invention showing a signal reception and distribution device in detail, Figure 4 is a diagram explaining a scanning cycle, and Figure 5 is an illustration of an embodiment of the present invention. , and are diagrams for explaining the operation of the present invention, FIG. 6 is a block diagram of a switching means for switching between a write cycle and a read cycle, and FIG. 7 is a time chart thereof. 1...Central control device 2...Signal reception distribution device, 3...
Parent scan control device, 4... Child scan control device, 5... Scan matrix, 11... Judgment circuit, 12... Decoder, 13... Parity check circuit, 14... 1/
N check circuit, 15...decoder, 16...1/× check circuit. Na red light 2' size 3 leg size 4 evil light S female (a) ryo S broadside (mouth) size 6 leg g pu

Claims (1)

[Scope of Claims] 1. A scanning unit that autonomously scans a plurality of scanning points and has a memory device in which scan results are written, and a central control unit that sends out a read request signal that specifies at least the scanning unit; An information scanning processing system comprising: a signal receiving and distributing device that receives a reading request signal from the central control device and distributes the reading request signal to the corresponding scanning unit;
When the signal receiving and distributing device receives a memory read request signal from the central control device, it immediately sends a memory read request presence signal indicating that the memory read request signal exists to the scanning section, and The memory device is characterized in that it is configured to put the device in a readable state and then send detailed information for reading information from the memory device to the scanning section specified by the memory read request signal. Information scanning processing method. 2 The scanning unit receives the memory read request presence signal,
2. The information scanning processing method according to claim 1, wherein the state of the memory device is controlled so that data can be read immediately from the memory device at the time when detailed information is received. 3. The scanning unit is configured to sequentially scan a plurality of scanning points according to a predetermined scanning cycle, each cycle consisting of a writing period and a reading period, and write the scanning results to the memory device in each of the writing periods. An information scanning processing method according to claim 1 or 2, characterized in that: 4. Claims characterized in that the scanning unit is configured to forcibly change the next write cycle to the read cycle when the read request presence signal is received during the read cycle of the scan cycle. The information scanning processing method described in Section 3.