JPS6050938A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6050938A
JPS6050938A JP58160685A JP16068583A JPS6050938A JP S6050938 A JPS6050938 A JP S6050938A JP 58160685 A JP58160685 A JP 58160685A JP 16068583 A JP16068583 A JP 16068583A JP S6050938 A JPS6050938 A JP S6050938A
Authority
JP
Japan
Prior art keywords
terminal
circuit
power supply
supply voltage
functional block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58160685A
Other languages
Japanese (ja)
Other versions
JPS6339100B2 (en
Inventor
Keiichi Miyata
宮田　慶一
Takeshi Inoue
剛至 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP58160685A priority Critical patent/JPS6050938A/en
Publication of JPS6050938A publication Critical patent/JPS6050938A/en
Publication of JPS6339100B2 publication Critical patent/JPS6339100B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To contrive the reduction of testing time and the improvement of reliability by a method wherein a testing terminal that tests the relation between the detection level of a detecting circuit and the range of operating voltages of an IC is provided in the IC having this circuit for detecting the power source voltage in a chip. CONSTITUTION:The output A of a power source voltage detecting circuit 2 is inputted to an OR-gate 4, and the output B of the gate 4 is used as a reset signal for a functional block 3. The other input of the gate 4 is connected to an IC terminal C as the testing terminal. In this construction, when the terminal C is kept connected to a GND, the terminal C turns to an L level, and then the action test for the IC can be carried out. On the other hand, the output B always turns to H by connection of the terminal C to the power source terminal VDD, therefore the minimum operating voltage of the functional block 3 can be measured independently of the detected level of the circuit 2. In the case of variations of the detected level of the circuit 2 and the minimum operating voltage of the block 3 with the dispersion in manufacture, this construction enables the reduction of testing time and the improvement in reliability.

Description

【発明の詳細な説明】 く技術分野〉 本発明は、ある電源電圧以下で回路の誤動作を防止する
ため、チップ内に電源電圧の検出回路を有する半導体集
積回路に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor integrated circuit having a power supply voltage detection circuit within a chip in order to prevent the circuit from malfunctioning below a certain power supply voltage.

〈従来技術〉 半導体集積回路（ｒｌｃＪと略す。以下同じ）は近年、
非常に広い分野で使用されており、ＩＣの機能及び性能
に対する市場の要求は、年々、多様化してきている。<Prior art> In recent years, semiconductor integrated circuits (abbreviated as rlcJ, the same shall apply hereinafter) have
They are used in a very wide range of fields, and market requirements for IC functions and performance are becoming more diverse year by year.

制御機器の分野に於ては、機器の誤動作を防止する意味
からＩＣの動作電源電圧範囲に関する要求が非常に厳し
く、電源電圧が低下してＩＣが正常に動作しない電圧に
なったとき、ＩＣは誤動作をせず機能を停止することを
要求される場合が多い。この様なＩＣではチップ内に電
源電圧の検出回路（単に「検出回路」と略す。以下同じ
）を内蔵し、この検出回路が判定したある電圧（単に［
−検出レベル」と略す。以下同じ）以下ではＩＣの機能
をリセットしたり、ＩＣの出力を禁止するなどの対応が
必要となる。In the field of control equipment, there are very strict requirements regarding the operating power supply voltage range of ICs in order to prevent equipment malfunctions. It is often required to stop functions without malfunctioning. Such an IC has a built-in power supply voltage detection circuit (simply abbreviated as "detection circuit"; the same applies hereinafter) in the chip, and a certain voltage determined by this detection circuit (simply [
- detection level". (The same applies hereafter) In the following cases, it is necessary to take measures such as resetting the IC function or prohibiting the IC output.

この様に、電源電圧検出回路を内蔵したＩＣに於ては、
検出ンベルと、ＩＣの正常動作電圧の関係を常に一定に
保つ必要があり、この関係をテストすることが非常に困
難である。即ち、電源電圧が検出レベル以上のときＩＣ
は正常に動作し、電源電圧が検出レベル以下のときＩＣ
の機能はリセットされなければならないから、ＩＣがリ
セットされるためには検出レベル以下でＩＣのりセント
機能が正常に動作する必要がある。いいかえれば、ＩＣ
の内部回路は検出レベル以上で動作しなければならない
。検出回路はＩＣに内蔵されるから製造上のばらつきに
よシ、検出レベルがばらつき、しかもＩＣの動作電圧下
限値もばらつくので、ＩＣの動作電圧範囲下限値を検出
レベルと規定する場合にテストが非常に複雑になる。In this way, in an IC with a built-in power supply voltage detection circuit,
It is necessary to always keep the relationship between the detection level and the normal operating voltage of the IC constant, and it is very difficult to test this relationship. That is, when the power supply voltage is higher than the detection level, the IC
The IC operates normally and the power supply voltage is below the detection level.
Since the function of the IC must be reset, the IC function must operate normally below the detection level in order for the IC to be reset. In other words, IC
The internal circuitry of the device must operate at or above the detection level. Since the detection circuit is built into the IC, the detection level will vary due to manufacturing variations, and the lower limit of the IC's operating voltage will also vary. It gets very complicated.

第１図に電源電圧検出回路を内蔵する従来のＩＣ１の溝
成図を示す。図に於て電源電圧検出回路２は、ＩＣの電
源端子○と接地端子（亙メとの間に接続され第２図に示
す様に電源電圧（以下「ＶＤＤ」と略す）をＯから上げ
ていくとＶＤＤ　−ＶＤＤＩで出力■を“Ｌ”　レベル
から”Ｈ”　レベルに変化する。FIG. 1 shows a diagram of a conventional IC 1 having a built-in power supply voltage detection circuit. In the figure, the power supply voltage detection circuit 2 is connected between the IC's power supply terminal ○ and the ground terminal (T), and increases the power supply voltage (hereinafter abbreviated as "VDD") from O as shown in Figure 2. As time goes on, the output ■ changes from "L" level to "H" level at VDD - VDDI.

第１図の電源電圧検出回路２の出力■はＩＣの機能ブロ
ック３のリセット信号Ｒとして入力される。機能ブロッ
クは、１個の入力端子、」個の出力端子およびに個の入
出力端子を持ち、ＩＣが所期の機能を行う様に設計され
た回路である。この機能ブロックにはり七ノド機能が伺
けられておシ、入力を“Ｌ”とすると機能ブロックは動
作を停止し、“Ｈ”とすると機能する様になっている。The output (2) of the power supply voltage detection circuit 2 in FIG. 1 is inputted as a reset signal R to the functional block 3 of the IC. A functional block is a circuit having one input terminal, two output terminals, and two input/output terminals, and is designed so that the IC performs the intended function. This functional block has a seven-point function, and when the input is set to "L", the functional block stops operating, and when the input is set to "H", it becomes functional.

また機能ブロックには電源、接地端子があり、これらは
電源電圧検出回路と共通に接続されている。The functional block also has a power supply and ground terminal, which are commonly connected to the power supply voltage detection circuit.

第１図の回路に於て、ＶＤＤをＯから上けていくと、的
圧ｆ←←←与器妙奨≠≠寺−＝−ｖＤＤ　ｌまでは電源
電圧検出回路２の出力■か“≠°゛レベルであるため機
能ブロック３はリセットされており機肯旨を停止してい
る。ＶＤＴ）がＶＤＤ１　を越えると電源′醒圧検出回
路の出力■が“Ｈｏ”レベルとなるだめ機能ブロックの
リセ・ントは解除され、ＶＤＤＩて機肯旨ブロックが正
常に動作すればＩＣは全体として所期の目的が達成され
る。ところか、機能フ゛ロンクの最低動作電源電圧ＶＤ
Ｄ２がＶＤＤＩより高けれは、Ｉ　ＣＩｄ、　ＶＤＤ　
カＶＤＤがＶＤＤＩとＶｆ）Ｄ２の１川にあるとき誤動
作を起すことになる。この様子を第３図に示す。In the circuit shown in Fig. 1, as VDD is increased from O, the output voltage f←←←Yokiyosho≠≠Te-=-vDD Until l, the output of the power supply voltage detection circuit 2 is ``≠''. Since the voltage is at the "Ho" level, the functional block 3 has been reset and has stopped validating.When VDT) exceeds VDD1, the output of the power supply voltage wake-up detection circuit goes to the "Ho" level. If the reset is canceled and the VDDI activation block operates normally, the intended purpose of the IC as a whole will be achieved.On the other hand, the minimum operating power supply voltage of the functional
If D2 is higher than VDDI, I CId, VDD
When VDD is in one line between VDDI and Vf)D2, a malfunction will occur. This situation is shown in FIG.

第３図で＠は機能プロ・ツクの最低動作電圧〃（電源電
圧検出回路の検出レベルＶｌ）Ｄ＋　より低い場合類あ
る。この場合は、電源電圧検出Ｉ司「各の、ｊｔ　１．
ソＪ■により機能ブロックのリセ・ントが解除されると
きには、すでに機能ブロックは正常動作できる状態にな
っているのでＩＣの動作として問題はない。In FIG. 3, there are cases where @ is lower than the minimum operating voltage of the functional program (detection level Vl of the power supply voltage detection circuit) D+. In this case, the power supply voltage detection circuit "Jt 1.
When the reset of the functional block is canceled by SOJ■, the functional block is already in a state where it can operate normally, so there is no problem in the operation of the IC.

のの場合は機能ブロックの最低動作電圧ＶＤＤ２が電源
電圧検出回路の検出レベ／’ＶＤＩＮ　より高い例で、
この場合は電源電圧検出回路の出力■により機能ブロッ
クのリセットが解除されるとき、機能ブロックは正常動
作できない状態であるから、ＶＤＤがＶＤＤＩとＶＤＤ
２の間では機能ブロックは誤動作をすることになる。In this case, the minimum operating voltage VDD2 of the functional block is higher than the detection level /'VDIN of the power supply voltage detection circuit.
In this case, when the reset of the functional block is canceled by the output ■ of the power supply voltage detection circuit, the functional block is in a state where it cannot operate normally, so VDD is between VDDI and VDD.
Between 2 and 2, the functional block will malfunction.

したがって、所期の目的を達成するためには、なわちＶ
ＤＤ　２　＜　ＶＤＤＩ　・　式（１）でなければなら
ない。Therefore, in order to achieve the intended purpose, V
DD 2 < VDDI ・Equation (1) must be satisfied.

上記のことから第１図の構成のＩＣをテストする場合、
式（１）の関係をテストすることが不可欠である。従来
のデス１一方法では式（１）の関係をテストするために
第４図に示す様に電源電圧を少しずつ上げて行きＩＣが
正常に機能するかどうかをテストしていた。即ち、ＩＣ
の設計値及びサンプル値から電源電圧検出回路の検出レ
ベルの最小値（ＩＣ製造工程上のバラツキのため検出レ
ベルが変動するため）を予測し、それより若干マージン
を見込んだ低い電源電圧ＶＤＤｏからテストを開始し、
ＩＣがリセットされているを確認していく。From the above, when testing an IC with the configuration shown in Figure 1,
It is essential to test the relationship in equation (1). In the conventional method, in order to test the relationship of equation (1), the power supply voltage was gradually increased as shown in FIG. 4 to test whether the IC functioned normally. That is, I.C.
Predict the minimum detection level of the power supply voltage detection circuit from the design value and sample value (because the detection level fluctuates due to variations in the IC manufacturing process), and test from a lower power supply voltage VDDo with a slight margin above that value. start,
Check that the IC has been reset.

この方法では、まずＶＤＤｏでテヌ１−を行い、ＩＣか
りセントされていることを確認し、次にＶＤＤを少し上
けて（△ＶＤＤ上げる）テヌ１−を行い、ＩＣＶＤＤ２
　＜　ＶＤＤＩ　ｆＡ＋ｎＪｆＶＤｎ＝　ＶＤＤＩ　ト
；’！ｚ−１１だときＩＣが正常動作する。ＶＤＤ２が
第４図のＶ　ＤＤ２　’の位置にある場合にはＶＤＤが
ＶＤｒ）＋〜ＶＤＤ２’の間延 にあるどきＩＣは誤動作を→すためＶＤＤＩ　＜　Ｖ　
Ｉ）Ｄ　２と女っているＩＣは排除することができる。In this method, first perform tenu1- on VDDo, confirm that the IC has been sent, then raise VDD a little (increase △VDD) and perform tenu1-, and then perform tenu1- on ICVDD2.
<VDDI fA+nJfVDn= VDDI t;'! When it is z-11, the IC operates normally. When VDD2 is at the position of VDD2' in Fig. 4, the IC will malfunction when VDD is in the interval between VDr)+ and VDD2', so VDDI < V.
I) ICs with D 2 can be eliminated.

しかしながら、このテスト方法では （１）　テストを繰り返すことによりＶｌ）Ｄ＋をさが
すため、テストに時間がかかる。However, this test method (1) searches for Vl)D+ by repeating the test, so the test takes time.

（２）△ＶＤＤノ範囲内テｖＤＤ１〈ＶＤＤ２となッテ
イるＩＣを排除することができない。(2) It is not possible to exclude ICs in which ΔVDD falls within the range of vDD1<VDD2.

の欠点がある。There are drawbacks.

〈発明の目的〉 本発明は、この様なＩＣに於て、テスト端子を１つ用意
することにより簡単にテストする方法を提供するもので
ある。<Objective of the Invention> The present invention provides a method for easily testing such an IC by preparing one test terminal.

〈実施例〉 第５図に、上記欠点を改善した本発明のＩＣの構成を示
す。<Embodiment> FIG. 5 shows the configuration of an IC of the present invention that improves the above-mentioned drawbacks.

第５図の各ブロックは、第１図と同じ機能を持つ。電源
検出回路２の出力■はオアゲート４に入力されオアゲー
ト４の出力■が機能ブロック３のリセット信号として使
用される。オアゲート４の他の入力はテヌ１一端子とし
てＩＣの端子Ｏに接続されている。この構成に於て、Ｉ
Ｃの端子０をＧＮＤに接続しておけば、端子Ｏは“Ｌ”
　レベルであり第１図の構成と同じである。テスト端子
０を使用することにより、前述の第１図の構成に於ける
テスト上の問題を解決することができる。Each block in FIG. 5 has the same function as in FIG. The output (2) of the power supply detection circuit 2 is input to the OR gate 4, and the output (2) of the OR gate 4 is used as a reset signal for the functional block 3. The other input of the OR gate 4 is connected to the terminal O of the IC as the TENU1 terminal. In this configuration, I
If terminal 0 of C is connected to GND, terminal O will be “L”
This level is the same as the configuration shown in FIG. By using test terminal 0, the test problem in the configuration shown in FIG. 1 described above can be solved.

その方法を次に示す。The method is shown below.

ＩＣの設計値及びサンプ／Ｌ／測定値から機能ブロック
の最低動作電圧の最大値Ｖ　ＤＤＡを決める。第５図の
構成にしておけば、テスト端子ＯをＶＤＤに接続するこ
とにより■は常に“Ｈ゛となっているから電源電圧検出
回路の検出レベルに関係なく、機能ブロックの最低動作
電圧を測定することができる。次に電源電圧検出回路の
検出レベ／’ＶＤＤ＋を見込む。設計値はＶＤＤ　１＞
　ＶＤＤＡとなっているはずである。第６図で説明する
。第６図でＶＤＤ＞ＶＤＤＡなる斜線の部分が機能ブロ
ックの動作電圧領域である。The maximum value V DDA of the minimum operating voltage of the functional block is determined from the IC design value and the sample/L/measured value. With the configuration shown in Figure 5, by connecting the test terminal O to VDD, ■ is always "H", so regardless of the detection level of the power supply voltage detection circuit, the lowest operating voltage of the functional block can be measured. Next, consider the detection level /'VDD+ of the power supply voltage detection circuit.The design value is VDD 1>
It should be VDDA. This will be explained with reference to FIG. In FIG. 6, the shaded area where VDD>VDDA is the operating voltage region of the functional block.

捷ず、テスト端子０をＶＤＤに接続して、ＶＤＤＡ＜　
ＶＤＤＢ　＜　ＶＤＤ　ｌ　々るＶ　ＤＤＢでＩＣの動
作テヌ１′を行う。ＶＤＤＢ　＞　ＶＤＤＡであり、且
つデス１一端子Ｃ）ｅ”Ｈ”としているから機能ブロッ
クは正常に動作するはずである。次にテスト端子ＯをＧ
ＮＤに接続してＩＣの動作テストを行う。テスト端子０
が′”Ｌ”であり且つＶＤＤＢ　＜　ＶＤＤＩであるか
ら機能ブロックはリセットされているはずである。Connect test terminal 0 to VDD without switching, and make VDDA<
IC operation tenu 1' is performed at VDDB < VDD l. Since VDDB>VDDA and the terminal C)e is set to "H", the functional block should operate normally. Next, connect the test terminal O to G.
Connect to ND to test IC operation. Test terminal 0
Since is ``L'' and VDDB < VDDI, the functional block should have been reset.

この２回のテストによ’Ｄ　ＶＤＤＡ　＜　ＶＤＤＩ　
であることが確認できる。もし、１回目のテストで不良
となればＶＤＤＢ　＜　ＶＤＤＡであシ、２回目のテス
トで不良となればＶＤＤＢ＞ＶＤＤｌのためである。Through these two tests, DVD VDDA < VDDI
It can be confirmed that If it fails in the first test, it is because VDDB<VDDA, and if it fails in the second test, it is because VDDB>VDDl.

電源電圧検出回路の検出レベル、機能ブロックの最低動
作電圧が製造上のばらつきにょシデバイヌごとに変動す
る場合、第５図の構成にすれはテスト時間の短縮及び信
頼性が高いことは明らかである。If the detection level of the power supply voltage detection circuit and the minimum operating voltage of the functional block vary depending on manufacturing variations, it is clear that the configuration shown in FIG. 5 reduces test time and is highly reliable.

〈効　果〉 以上説明したように本発明によれば、テスト時間の短縮
及び信頼性の向上をはかることができる、きわめて有用
な半導体集積回路を得ることができるものである。<Effects> As explained above, according to the present invention, it is possible to obtain an extremely useful semiconductor integrated circuit that can shorten test time and improve reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＩＣの構成を示す構成図、第２図は電源
電圧検出回路の説明に供する図、第３図は機能ブロック
の最低動作電圧と電源電圧検出回路の検出レベルとの関
係によって、誤動作領域が玉じることの説明に供する図
、第４図は従来のテスト方法の説明に供する図、第５図
は本発明に係るＩＣの構成を示す構成図、第６図は本発
明に係るチアド方法の説明に供する図である。 符号の説明 １：ＩＣ１２：電源電圧検出回路、　３：機能ブロック
、　４ニオアゲ−１−５Ｏ：テスト端子。 代理人　弁理士　福　士　愛　彦（他２名）第１図 り’５２ｔ４ ｖＤＩ’ｍｔ　Ｔｒａｎｓ　’Ｖ（，０昏塀１電力り 第３（３） （ｆ１１回欽）　日キ嗜嘴 手続補正書 （ｆう許庁　殿） １　事件の表示 特願昭　５８−１６０６８５ ２、発明の名称 半導体集積回路 ３　補正をする者 ・１１件との関係　特許出願人 イ１　所　曇５４５大阪市阿倍野区長池町２２番２２号
４　代　理　人 イ］　所　曇５４５大阪市阿倍野区長池町２２番２２号
自　発 Ｇ、補正の対象 ） ７　補正の内容 明細書の第３頁第１行の「検出レベル以上」を「検出レ
ベル以下」と訂正します。 以　」ニFig. 1 is a block diagram showing the configuration of a conventional IC, Fig. 2 is a diagram for explaining the power supply voltage detection circuit, and Fig. 3 is a diagram showing the relationship between the minimum operating voltage of the functional block and the detection level of the power supply voltage detection circuit. , FIG. 4 is a diagram for explaining the conventional test method, FIG. 5 is a configuration diagram showing the configuration of the IC according to the present invention, and FIG. 6 is a diagram for explaining the configuration of the IC according to the present invention. FIG. Explanation of symbols 1: IC12: Power supply voltage detection circuit, 3: Functional block, 4Nioage-1-5O: Test terminal. Agent Patent Attorney Aihiko Fukushi (and 2 others) 1st Plan '52t4 vDI'mt Trans'V (, 0 Kobe 1 Electric Power 3rd (3) (f11th Qin) Japan-Ki Suzuki Procedural Amendment ( 1. Indication of the case Patent application No. 58-160685 2. Name of the invention Semiconductor integrated circuit 3. Person making the amendment/Relationship with the 11 cases Patent applicant 1. Address: 22 Nagaike-cho, Abeno-ku, Osaka-shi, Kumo 545 No. 22, 4 Deputy Administrator, 22-22, Nagaike-cho, Abeno-ku, Osaka City, 545 Kumoji, Subject of amendment) 7 Changed ``detection level or higher'' to ``detection level'' in the first line of page 3 of the detailed description of the amendment. below the level,” I corrected. ” ni

Claims (1)

【特許請求の範囲】[Claims] １　ある電源電圧以下で、回路の誤動作を防止するため
、チップ内に電源電圧の検出回路を有する半導体集積回
路に於て、電源電圧検出回路の検出レベルと回路の動作
電圧範囲の関係のテストを簡単に行うことを目的とした
テスト端子を有することを特徴とした半導体集積回路。1. In order to prevent circuit malfunctions below a certain power supply voltage, in semiconductor integrated circuits that have a power supply voltage detection circuit within the chip, tests are conducted to determine the relationship between the detection level of the power supply voltage detection circuit and the operating voltage range of the circuit. A semiconductor integrated circuit characterized by having test terminals for the purpose of easy testing.
JP58160685A 1983-08-30 1983-08-30 Semiconductor integrated circuit Granted JPS6050938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58160685A JPS6050938A (en) 1983-08-30 1983-08-30 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58160685A JPS6050938A (en) 1983-08-30 1983-08-30 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPS6050938A true JPS6050938A (en) 1985-03-22
JPS6339100B2 JPS6339100B2 (en) 1988-08-03

Family

ID=15720250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58160685A Granted JPS6050938A (en) 1983-08-30 1983-08-30 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6050938A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6340404U (en) * 1986-09-01 1988-03-16

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6340404U (en) * 1986-09-01 1988-03-16

Also Published As

Publication number Publication date
JPS6339100B2 (en) 1988-08-03

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