JPS605070B2 - Manufacturing method of MOS structure field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a MOS structure field effect transistor (hereinafter abbreviated as MOSFET) formed on an insulating single crystal substrate.

Conventionally, a silicon epitaxial growth layer formed on an insulating single crystal substrate is called SOI (Silicon Insulator), and especially when this insulating single crystal substrate is sapphire, it is called SOS (Silicon Insulator).
MOSFETs made using this SOS silicon epitaxial growth layer, and semiconductor devices such as integrated circuits that use these MOSFETs as components, have high-speed operation characteristics and low power consumption. It is attracting attention and expectations are high.

However, semiconductor devices fabricated using this SOS silicon epitaxial growth layer require expensive sapphire substrates, are weak against thermal stress, and must be placed in a high-temperature diffusion furnace, for example, to avoid rapid heating and cooling. Insertion and removal operations require a long time of several minutes, and the workability is poor, and because the potential of the Safya substrate is floating, the drain current of the MOSFET increases abnormally (abnormal current increase phenomenon). In addition, the power consumption of the semiconductor device that uses this MOSFET as a component increases, and the channel conductance decreases due to the low mobility caused by the imperfection of the crystal of the SOS epitaxially grown layer. There were many drawbacks, such as a decrease in source-drain leakage current and an increase in source-drain leakage current due to its large number of crystal defects.

Z In this specification, S
MOSFETs and semiconductor devices made using OI or SOS silicon epitaxial growth layers,
SOIMOS FET and SOI device, respectively
Alternatively, they will be referred to as SOSMOS FETs and SOS devices. The present invention was made in view of the above-mentioned drawbacks of the SOS device, and an object of the present invention is to obtain an SOI device that is inexpensive and has stable operation. Hereinafter, one embodiment of the SOIMOSFET manufacturing method according to the present invention will be described.
This will be explained with reference to longitudinal cross-sectional views shown in Figures a to d, respectively.

Figure a shows a first step of growing a silicon carbide SIC layer 2 on a silicon Si substrate 1 in a vapor phase.

In this step, the SIC layer 2 is grown using a vapor phase growth method on the Si substrate 1 using, for example, monosilane (SiH4) and propane (C3).
(ratio) is pyrolyzed at high temperature and grown to a layer thickness of about 1. The SIC layer 2 grown by this vapor phase growth method has a lattice spacing that matches that of Si over a long range, so it is a single crystal and has a high resistivity of several tens of KQ/arc. It can be considered an insulator. This SIC layer 2 is a single crystal insulator that is much cheaper than saphire, and is also resistant to thermal stress and can be used for work that requires rapid heating and cooling. Figure b is the above-mentioned S.
A second step is shown in which selective etching is performed on the IC layer 2 using a mask 3 made of a photoresist material having a desired shape pattern to form a gate part 4 exposing the Si substrate 1.

The opening 4 formed in this step is a SO
This is provided so that the Si epitaxial growth layer in which the channel region of the IMOSFET is formed can be epitaxially grown in direct contact with the surface of the Si substrate 1 within this gateway 4.

FIG. c shows the third step of covering the surface of the Sj substrate 1 in the opening 4 and growing a silicon epitaxial growth layer 5 on the SIC layer 2 by an epitaxial growth method.

In this step, Si is added to the Si epitaxial growth layer 5.
A recess 6 having a shape pattern corresponding to the pattern of the gate part 4 is formed on the substrate 1 .

Needless to say, the Si epitaxial growth layer 5 on the Si substrate 1 in this recess 6 is also single crystal. Thus, it is an important basis of this invention that the Si epitaxial growth layer 5 is single crystal. FIG. d shows a fourth step in which a drain region 9 and a source region 10 are formed in the Si epitaxially grown layer 5 on the SIC layer 2 so that a channel forming region 8 is formed in the Si epitaxially grown layer 5 in the recess 6. The process is shown below.

In this step, the Si epitaxial growth layer 5 is formed by selective etching into the Si epitaxial growth layer 5 having a desired shape pattern consisting of the recess 6 and its surrounding area, and the recess 6 is formed on the Si epitaxial growth layer 5.
A gate insulating film 7 having a desired shape is provided across the inside and a part of the periphery, and a channel forming region 8 is formed in the Si epitaxial growth layer 5 formed directly under the gate insulating film 7 in direct contact with the Si substrate 1. By selectively diffusing impurities so that all or most of the drain regions 9,
and source region 10 are formed.

A diffusion bond 11 between the channel forming region 8 and the drain region 9 formed during selective diffusion of impurities is formed on the edge of the SIC layer 2 in the recess 6 and on the Si substrate 1 at a distance indicated by S and the channel. A diffusion junction 12 between the formation region 8 and the source region 10 is formed on the SIC layer 2 .
The post-processes of the steps described above are completely dependent on the SOSMOSF.
Similar to the ET manufacturing process, a gate electrode 13 with a desired shape pattern is provided on the gate insulating film 7, and then a desired shape pattern is formed on the surfaces of the gate electrode 13, drain region 9, and source region 10, respectively. A field insulating film 14 having closed portions is applied, and the gate electrode 1 within these closed portions is formed.
3. Aluminum film wirings 15a, 15b and 15c are formed in resistance contact with the drain region 9 and the source region 10, respectively, to create a required SOIMOSFET.

SOIMOSFE according to this invention created in this way
T differs from a conventional SOSMOSFET in that the diffusion junction 11 formed between the drain region 9 and the channel forming region 8 and the channel forming region 8 are both in direct contact with the Si substrate 1. ing.

That is, in the SOIMOSFET according to the present invention, both the diffusion junction 11 and the channel forming region 8 are made of Si.
The conventional SOSMO is formed of a homoepitaxial growth layer epitaxially grown on the substrate 1.
The SFET is formed of a heteroepitaxially grown layer epitaxially grown on a sapphire substrate. This difference has a very large effect on the performance of semiconductor devices, and in the case of a homoepitaxially grown layer, lattice defects, such as dislocation density, are Since it can be reduced by more than three orders of magnitude compared to the conventional case, carrier mobility can be improved and channel conductance can be improved. In addition, in this case, the floor current in the drain depletion layer can also be reduced, so unlike conventional SOS devices, there is no need to limit the application to C-MOS static operation, and dynamic operation is also possible. Furthermore, since the channel formation region is of the same conductivity type as the Si substrate, the potential of the substrate does not float, and the phenomenon of abnormal increase in drain current is prevented. It can be prevented. Furthermore, in the SOI device according to the present invention, not only can the isolation between elements, which is an advantage of the conventional SOS device, be completely achieved by selectively removing the Si epitaxial growth layer 5, but also the drain junction capacitance can be removed from the SIC layer. It can be reduced by 2. In the above embodiment, since the diffusion bonding 11 is formed inside the gate part 4, the capacitance corresponding to the distance S increases. Therefore, it is necessary to make the distance S as small as possible so that it is in contact with the edge of the SIC layer 2. Delicious.

Furthermore, it is not always necessary that the diffusion bonding 11 be formed within the gate part 48. In the above embodiment, a SIC layer is formed on a silicon semiconductor substrate, and a silicon epitaxial layer formed on this SIC layer is formed on a silicon semiconductor substrate. SOI using grown layers
Although the method for manufacturing a MOSFET has been described, the present invention is not limited thereto, and includes forming an insulating single crystal layer on a semiconductor single crystal substrate other than Si, and depositing the above semiconductor single crystal layer on this insulating single crystal layer. It is possible to form an epitaxially grown layer of the same semiconductor as the crystal substrate and apply it to a method of manufacturing a MOS structure field effect semiconductor device using this semiconductor epitaxially grown layer.

As described above in detail, the method for manufacturing a MOS structure field effect semiconductor device according to the present invention involves forming an insulating single crystal layer on a semiconductor single crystal substrate, selectively removing the insulating single crystal layer, and then removing the insulating single crystal layer by selective etching. By providing a gate portion that exposes the semiconductor single crystal substrate, covering this closing portion, and forming an epitaxial growth layer of the semiconductor crystal on the insulating single crystal layer, the exposed gate portion of the semiconductor crystal substrate is formed. According to the present invention, a homoepitaxially grown layer of the semiconductor crystal is formed in the semiconductor crystal, and at least a part of the channel forming region of the semiconductor device is formed in this homoepitaxially grown layer. The semiconductor device described above has few lattice defects in the semiconductor crystal layer in the channel formation region, which improves carrier mobility and has effects such as improving channel conductance and reducing layer current in the drain depletion layer. be.

[Brief explanation of the drawing]

Boxes a to d are SOIMOSFETs according to the present invention, respectively.
FIG. In the figure, 1 is a silicon substrate, 2 is a silicon carbide layer,
3 is a mask, 4 is an opening, 5 is a silicon epitaxial growth layer, 6 is a recess, 7 is a gate insulating film, 8 is a channel forming region, 9 is a drain region, 10 is a source region, 11
, and 12 are diffusion junctions, 13 is a gate electrode, 14 is a field insulating film, and 15a, 15b, and 15c are aluminum film wirings, respectively. Note that the same reference numerals in the figures indicate the same or corresponding parts. (Q) (b) (C) (〆)

Claims (1)

[Claims] 1. A first step of forming an insulating single crystal layer on a semiconductor single crystal substrate, in which the insulating single crystal layer is selectively etched to expose the semiconductor single crystal substrate in a desired shape pattern. a second step of forming an opening; a third step of growing an epitaxial growth layer of the same semiconductor as the semiconductor single crystal substrate over the semiconductor single crystal substrate and the insulating single crystal layer within the opening; and a fourth step of forming a source region and a drain region such that all or most of the channel forming region is formed in a portion of the epitaxial growth layer in contact with the semiconductor single crystal substrate. Effect semiconductor device manufacturing method. 2. M according to claim 1, in which the bonding surface between the channel forming region and the drain region is within the opening.
A method for manufacturing an OS structure field effect semiconductor device. 3. M according to claim 1, in which the bonding surface between the channel forming region and the drain region is located at the end of the opening.
A method for manufacturing an OS structure field effect semiconductor device. 4. A method for manufacturing a MOS structure field effect semiconductor device according to any one of claims 1 to 3, characterized in that a silicon single crystal substrate is used as the semiconductor single crystal substrate. 5. The method of manufacturing a MOS structure field effect semiconductor device according to claim 4, characterized in that a silicon carbide single crystal layer is used as the insulator single crystal layer.