JPS6049663U - 配線基板 - Google Patents
配線基板Info
- Publication number
- JPS6049663U JPS6049663U JP1983143209U JP14320983U JPS6049663U JP S6049663 U JPS6049663 U JP S6049663U JP 1983143209 U JP1983143209 U JP 1983143209U JP 14320983 U JP14320983 U JP 14320983U JP S6049663 U JPS6049663 U JP S6049663U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- glaze layer
- semiconductor element
- thinner
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
第１図は従来の配線基板の断面図、第２図は本考案実施
例の配線基板の断面図である。 １・・・基台、２，３・・・グレーズ層、４，４・・・
配線 −パターン、５，５・・・半導体素子、６，
６・・・接着剤、７，７・・・金属細線。
例の配線基板の断面図である。 １・・・基台、２，３・・・グレーズ層、４，４・・・
配線 −パターン、５，５・・・半導体素子、６，
６・・・接着剤、７，７・・・金属細線。
Claims (2)
- （１）基台と、基台上に設けられたグレーズ層と、グレ
ーズ層上に接着剤等で載置された半導体素子とを具備し
、グレーズ層の半導体素子の載置場所はその周辺場所よ
り厚みかうすい事を特徴とする配線基板。 - （２）前記グレーズ層の上には配線パターンが設けてあ
り、半導体素子の周辺の配線パターン上にワイヤボンド
されている事を特徴とする前記実用新案登録請求の範囲
第１項記載の配線基板。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983143209U JPS6049663U (ja) | 1983-09-13 | 1983-09-13 | 配線基板 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1983143209U JPS6049663U (ja) | 1983-09-13 | 1983-09-13 | 配線基板 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6049663U true JPS6049663U (ja) | 1985-04-08 |
Family
ID=30319734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1983143209U Pending JPS6049663U (ja) | 1983-09-13 | 1983-09-13 | 配線基板 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6049663U (ja) |
-
1983
- 1983-09-13 JP JP1983143209U patent/JPS6049663U/ja active Pending
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