JPS6049451A - Data checking system - Google Patents

Abstract

PURPOSE:To identify the true cause of an error by preventing detection and holding of the error with use of an error correction code logic mechanism for write or read data in case an uncorrectable error is detected and held by the read or write data. CONSTITUTION:When a 2-bit error is detected at the side of a read data RD, the functions of both an error correction code logic EEC mechanism 12 and a holding mechanism 13 of the write data WD are blocked by the output signal of a holding mechanism 15 when an instruction of detection is closed. Then only the mechanism 15 of the RD side is turned on since the mechanism 12 has no actuation until a CPU2 executes a release instruction. In the same way, only the mechanism 13 is turned on when a write instruction is executed. The blocked mechanism 12 has no actuation in both read and write modes until the CPU2 executes the release instruction. Thus the true cause is identified for the error detected by the mechanism 12 just by reading mechanisms 13 and 15.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data checking method in a data processing system that performs data checking using an error correction code logic mechanism for both data written to and read from a storage device. .

(bl Background of the Technology) With the recent trend toward faster data processing systems, even if an error is detected in data written to or read from a storage device, the central processing unit is stopped at the machine cycle level and the failure state is maintained. It has become difficult to diagnose.

In particular, in a data processing system that performs a data check on both write data and read data to a storage device using, for example, an error correction code logic mechanism and holds the check results, even if the held results are directly searched, the read It has become difficult to distinguish whether the problem is caused by an error in data or an error in write data.

On the other hand, in recent data processing systems, a scan-out function is known for reading the state inside the data processing device as diagnostic data when a failure occurs. This involves reading out the data serially at a clock level from various flip-flops, registers, etc. in the data processing device, for example, based on instructions from a service processor, processing the data in the service processor, and displaying the data on a display.
This is intended to facilitate diagnosis of failure conditions in the data processing apparatus.

However, because the data processing speed of the service processor is slow, for example, when looking at the flip-flop block (FF) that holds errors related to read data and write data detected by the error correction code logic mechanism described above, ,
It is difficult to identify the context in which the error occurred,
At present, it is not possible to search for the true cause of the error.

Therefore, when error checking is performed on both sides of read/write data in a storage device, it is necessary to consider a method for identifying the true cause of errors by using the scan-out function to check the flip-flops that hold the check results. It was wanted.

(C) Conventional technology and problems In a data processing system that performs data checking using an error correction code logic (hereinafter referred to as ECC) mechanism for both write data (Wl) and read data (RD) of a storage device, The checking mechanism of the system is as shown in FIG. 1, where ■ is the main storage device, 11 is the memory section, 12.14 is the ECC mechanism (ECC), 13.
15 is a hold mechanism (I
OLD), 2 is the central processing unit.

21 is a write control section (WDC).

In such a system, when a partial write instruction is executed and a 2-pin error occurs in the read data (RD), the hold mechanism (HOLD) 15 is turned on, but it is difficult to determine in which bit position the error occurs. It is unknown whether there are any.

The central processing unit 2
When the write control unit (WIIC) 21 executes a partial write, the ECC mechanism (LIC
e) In 12, a 2-bit error of +111 may not be detected. (This can be converted into data.
ζ1.L: In order to prevent the data from becoming garbled, the UCCfi structure (IEcc) is used for the read data (R11).
14Te2 Hit uplink is detected and the hold mechanism (
IIOLD) When j5 is turned on, the old write control unit (WD(:) 21 is accessed 7 times and all bits including the C, I+CG check bits are set to "0".
Or by controlling to write all "l"),
Always ECCta structure (ECC) +2'j' 2-bit error is detected, hold mechanism (1101, 11) 1
3 can be turned on, resulting in both Hall 1 mechanism (IIOLD) 13.15°C being turned on.

However, as long as this state is read and checked using the scan-out function described in 11i1, it is possible to determine whether there was a 2-bit error in the read data caused by the execution of the above partial write instruction or by the execution of another store instruction from the central processing unit 2. There was a problem in that it was not possible to identify whether there was a 2-bit error in the written data.

+d) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides an E
In a data processing system that performs data checking using the CC1'' structure, when a 2-bit error is detected in the read data (RD) during the execution of one instruction, and the data is held, the stored data (RD) by another instruction is eye)
The object of the present invention is to provide a method for detecting a two-focus error in an ECC mechanism and preventing a hold from occurring.

According to the present invention, the structure and object of the invention are as follows: (1) A data processing system in which data checking is performed by an error correction code logic mechanism on both data written to a storage device and data read out. When a certain instruction is executed and an uncorrectable error is detected and held in the read data, the above-mentioned error correction code logic mechanism of the written data is executed until the circuit that detects and holds the error is reset. When an uncorrectable error is detected and retained in the written data, the read data is controlled so that the above error correction code logic mechanism does not perform error detection and retention. how to.

(In the data check method described in Section 21+11, controlling the write data or read data so that the error correction code logic mechanism does not perform error detection and retention is performed when an uncorrectable error occurs on the read data side or the write data side.) method at the end of the instruction where is detected.

This is achieved by providing a 2-bit error on the read data side or a 2-bit error on the write data side, which has the advantage of being easily distinguishable.

(fl　Embodiments of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, and 1.2. lL12, 13, 14, 15.21 are all the same as those explained in FIG. , the ECC mechanism (ECC) 12 and the hold mechanism (IIOLD) 13 on the write data (WD) side are controlled so that they do not function, and the output signal of the hold mechanism (Hot, D) 13 is used to
ECC mechanism (ECC) 14 on the read data (RD) side
The difference is that the hold mechanism (HOLD) 15 is controlled so that it does not function. This blocking function is implemented by the ECC mechanism (ECC) on the read data (RD) side.
44 and hold mechanism (IOLD) 15, or ECC mechanism (ECC) 12 and hold mechanism (110LD) 13 on the write data (WD) side are not released until they are reset by a release command executed by the central processing unit 2. It is characterized by the fact that it is controlled by

In a data processing system that has such functions in a single digit,
Considering the case where a partial write instruction is executed and a 2-bit error is detected in the read data, as explained in FIG. 1 of the conventional example, when the hold mechanism (IIOLD) 15 is turned on, the ECC mechanism (ECC) The write control unit (WDC) 21 is accessed by the error detection signal at 14, and operates to write all "1"s, for example.
Bold mechanism (IIOLD) on read data (RD) side
) 15 and the write data (WD) side hold mechanism (HOLD) 13 are both turned on.

Then, after that (for example, at the end of the instruction), with the output signal of the hold mechanism (IOLD) 15,
'M key included 9 (WD) side (7) ECCtatj&
(ECC) 12 and hold mechanism (HOLD) 13
is controlled so that it does not function.

However, when a general read instruction is executed, when the above 2-bit error is detected on the read data (RD) side, the hold mechanism (IIO) is activated at the end of the instruction.
The write data (HD
) side ECC @ structure (ECC) 12 and hold mechanism (
HOLD) 13 functions, until the central processing unit 2 executes the above-mentioned release command.
Since the ECCill mechanism on the write data (WD) side does not operate, the hold mechanism (IO
LD) operates so that only LD15 is turned on.

Similarly, when a write command is executed, the bold mechanism (HOLD) on the write data (WD) side
13 is turned on.

And in both cases, as mentioned above, the occluded E
Since the CC mechanism does not operate until the release command is executed by the central processing unit 2, the above-mentioned scan-out mechanism
By simply reading the hold mechanism ()IOLD>13.15, the true cause of the error detected by the ECC mechanism can be identified.

The above is the read data when a 2-bit error occurs in the read data (RD) and when a 2-bit error occurs in the write data (RD) when a read command 1 partial write command or write command is executed. (RD) side hold mechanism (HOLD) 15 and write data (
The relationship with the hold mechanism (HOLD) 13 on the WD) side is summarized as shown in FIG.

As is clear from this figure, when the present invention is implemented, any read to the main storage device 1 is performed.

Even when a 2-bit error occurs in a write operation, the true cause of the error can be identified by checking the value of each hold mechanism (IIOLD>) at the service processor.

In addition, the method of closing the ECC mechanism and bold mechanism is as follows: hold output (13 or 15) is F, CC mechanism (12 or 1
It goes without saying that it is also possible to block only 4) so that even if a 2-bit error occurs, it will not be bolded.

fgl Effects of the Invention As explained in detail above, the data check method of the present invention is a data processing method in which data is checked by the ECC mechanism on both write data (WD) and read data (RD) of the storage device. In the system, when a 2-bit error is detected in the read data (RD) and it is being held, the ECC for the write data (Wll) is
The mechanism is not allowed to detect and hold a 2-bit error, and when a 2-bit error is detected in the write data (WD) and is being held, the read data (1?D) is not detected and held.
) is controlled so that the ECC mechanism does not detect and hold a 2-bit error.
The respective bold mechanism (
By viewing the value of IOLD at the service processor, the true cause of the error can be identified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a 2-bit error detection and hold method using a conventional ECC45 structure, and FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing the relationship between error conditions and hold values in a storage device when the present invention is implemented. In the drawings, 1 is a main storage device, 2 is a central processing unit,
12.14 indicates an ECC mechanism (ECC), 13.15 indicates a hold mechanism (l (OLD)), and 21 indicates a write control unit (WDC).

Claims (1)

[Claims] (1) In a data processing system that uses an error correction code logic mechanism to check both the data written to the storage device and the data read, one instruction can be executed to detect uncorrectable data in the read data. When an error is detected and held, the write data is controlled so as not to be detected and held by the error correction code logic mechanism until the circuit that detects and holds the error is reset. When an uncorrectable error is detected and held, the read data is prevented from being detected and held by the error correction code logic mechanism until the circuit that detects and holds the error is reset. A data check method characterized by control. (2. In the data check method recited in claim 1, the read data side or the write A data check method is characterized in that it is performed at the end of execution of an instruction in which an uncorrectable error has been detected.