JPS60207937A - Data processor - Google Patents

Abstract

PURPOSE:To simplify debugging without damaging the debugger by allowing a support processor to execute a debugger program in a processor having a program debugging function. CONSTITUTION:A debugger program is stored in a main storage device 29 of a support processor 25. When receiving a status change interruption from a control part 23 in a CPU14, a control part 26 of a supporting processor 25 starts an OS of the supporting processor 25. Consequently, program debugging by the supporting processor 25 is started. Then, a control part 26 accesses the control part 23, reads out the contents of a control register 20 in the CPU14 through a buffer 24 and a data line 27 and detects the status of the CPU14 and an interruption factor.

Description

Detailed Description of the Invention [Technical Field of Komei] The present invention relates to a data processing device having a program debugging joint.

[Problems with the technical background of the invention] Conventionally, the operation test of programs in main memory has been carried out using software i~
The debugger program for this purpose was also placed in the main memory. Further, in the test, the corresponding CPU state was not Ti.

For this reason, there are problems such as the risk that the debugger may be destroyed by the program to be debugged, and debugging itself is also difficult. Furthermore, since the debugger is located on the main memory, if a multiprocessor configuration is to be realized, for example, the debugger itself must be aware of this, which has the disadvantage that the structure of the debugger itself becomes complicated.

[Purpose of Jfl Akira] This invention was made in view of the above-mentioned circumstances, and its purpose is to prevent the debugger from being destroyed by the program to be debugged, to allow easy debugging, and to provide a debugger that can be used even in a multiprocessor configuration. What about its own structure? !
! The object of the present invention is to provide a data processing device that does not need to be complicated.

[Overview of the light room] This light room is equipped with a support processor that can directly access the CPU. In addition, the CPU stores information indicating various states of the CPU, including special stop states that require debugging by a supporting processor, and can be read/written by the CPU control unit and readable by the supporting processor. a second register that stores information indicating the cause of the interrupt such as the above-mentioned special 1-stopped state, and that is readable/writable by the roll section of the CPU and readable by the support processor; means for determining whether or not to place the CPU in a special closed state when a factor occurs, and updating the contents of the first and second registers according to the determination result;
Means is provided for issuing a state change interrupt from the CPU to the support processor when the state of the support processor changes. ribo-
1 - The processor refers to the above ffil register in response to a state change interrupt from the CPU, and if this first register indicates that the CPU is in a special stop state, the processor determines the cause of the interrupt based on the contents of the second register. Make a determination.

[Embodiment of the Invention] The drawing shows the configuration of a data processing device according to an embodiment of the invention. In the figure, 11 is a main memory, and 12 is an interrupt vector placed in a storage area (main memory) of the main memory @11. Information necessary for performing interrupt processing is set in the interrupt vector 12. 13 is main storage device 1
1 memory bus, and 14 the above I via memory bus 13.
This is a CPtJ connected to the l device 11.

In the CPU 14, J3-C115 is the demonstration section, 1G is the register that stores the test stop factor mask (δ, 11 is the test stop register), and 21.22 is the demonstration section 1.
5 and an internal data bus connecting the registers 16 to 20; 23 is a control section of the CPU 14; and 24 is a buffer connected to the internal data bus 22. Buffer 24 is used to interface with CP IJ 14 and support processor 25, which will be described next.

25 is a 4 node processor which can directly access the CPU 14, and 2G is a control unit for the ribo-1 processor 25. The controller 1 to the roll unit 26 are connected to the buffer 24 of the CPU 14 via a data line 27, and are connected to the buffer 24 of the CPU 14 via a control line 28.
It is connected to the control section 23 of. 29 is a main storage device of the support processor 25. Main storage device 29
In the 10th area, debugger programs are popular.

Next, the operation of one embodiment of this lfl light will be explained.

Assume that some interrupt factor occurs R1 while the c p U 14 is in a normal operating state. At this time, c
The control section 23 of the p U 14 reads the PSW from the register 19 . In this PSW, if interrupts for the factors listed in "2" are prohibited, the CPU 14 operates as is according to the flow of the program. On the other hand, if interrupts are enabled, the CPU 14 follows the interrupt vector 12 and stores the information of the R1 instruction of the vj interrupt, the interrupt cause code, the contents of registers 16 to 20, etc. in the main memory 11, if necessary. Save to a predetermined area A or stack,
Branches to the rough 1-ware interrupt processing routine.

In this embodiment, the state of the CPU 14 is monitored. ! A support processor 25 is provided. The cpu 14 operates under the supervision of this four-node processor 25.
The state in which is tested is called test mode.

Now, suppose that when the CPU 14 is in the test mode, some reduction factor is R1, and the reduction υj can be corrected. Nowadays, depending on the factors, rough 1
- Ware interrupt processing may not be necessary. Therefore, in such a case, in order to avoid complicated hardware and software processing, the CP tJ
14 is in a stopped state.

Note that this state is distinguished from a normal stop state and is called a test stop state.

The test mode is set by a signal transferred from the control section 2G of the support processor 25 via the control line 28. This signal is "true" during the test mode period. Therefore, the controller 1 to the roll unit 23 of the CPU 14 can directly know that the test mode is in effect from this signal. When an interrupt occurs, , the control unit 23 of the CPU 14 determines whether or not to enter the dead stop state. Therefore, in this example, the control unit 23 outputs 1 to access from the control unit 23.
The writable register 1G is set as a test 17 stop factor mask.

This register 1G (test stop factor mask)
1 from the processor 25 to the controller 1 of c p U 14.
- By accessing the roll unit 23, the buffer 2
It is possible to continue/misspoke through 4. Further, in this example, in the initial setting of the Dest 1 stop factor mask, test stop is permitted only for some factors, but this can be rewritten from the support processor 25. The control unit 23 of the CPU 14 is
The test 1 stop factor mask is read out to determine whether the light pressure/permission for stopping the test is allowed. If disabled, normal interrupt processing is performed.

On the other hand, if permission is granted, the test will be stopped. In this case, it is necessary to indicate that the CPU 14 is in the test (stopped) state. Therefore, in this example, a bit indicating test +-p is prepared in the control register 20 that indicates various states of the CPU 14. When the control unit 23 determines that the test stop is permitted, the control unit 23 sets the test stop bit in the control register 20 together with the normal stop bit to indicate the test stop.
It can be read/written from the control unit 23 of the U 14 and can be continuously output from the support processor 25.

In addition, the controller 23 sets the register 17 that it can access (including 77 yen for reading) as the dest stop cause code in order to indicate what factor including υ1 caused the test to stop. . This register 17 (test stop l: factor" -1. By setting these, a test stop state is realized.

Next, even if interrupts are permitted for interrupts that occur during R1 during the operation of the CPU 14, unlike the case described above, if the CPU 14 is not in the dest mode or is in the test mode. Also, a case will be explained in which stopping of the dest IJ7 is prohibited for the interrupt factor. In this case, the operation differs depending on whether or not the interrupt vector 12 is set in the main storage device 11.

If the υj inclusion vector 12 is set, normal υ1 inclusion processing is performed. On the other hand, before the lid 12 is set to the interrupt, normal interrupt processing;
The CPU 14 is in a stopped state.

Note that this state is distinguished from a normal stop state and is called a check stop state.

When attempting to perform normal interrupt processing, if the control unit 23 of the CPU 14 knows that the interrupt vector 12 has not yet been set, the CPU 14 directly stops checking. If not, CP
The control unit 23 of U 14 is the vector 1 including υ1.
I published whether or not 2 is before setting! It is necessary to do this.

Therefore, in this example, in the initial setting of the interrupt vector 12, the new location in the interrupt vector 12 is set to 0, for example.
''. Therefore, when the control I-roll unit 23 is about to perform normal interrupt processing and execute J3, it first checks this new location one after another and determines whether or not to stop checking. By the way, when the check stops, it is necessary to indicate that the CPU 14 is in the check stop state. Therefore, in this example, the above-mentioned dest PP is written in the control register 20 to indicate the state of each row of the CPU 14. Similar to the bits 1 to 1 indicating stop, a bit indicating check stop is prepared.When the control unit 23 determines whether the check (?stop 1) is possible, the control unit 23 sets the bit indicating check stop in the control register 20 to It indicates a test stop by setting the bit together with a bit indicating a normal stop.In addition, the controller 1 roll unit 23 performs access (read/write) to the controller 1 in order to determine what interrupt factor caused the check 1 to stop state. The possible register 18 is set as the check stop cause code.This register 18 (check stop cause code) is
Support processors 25h) can be successively installed. By setting these, a check stop state is realized.

When the CPU 14 enters the dead lvl stop state or the check stop state, the control unit 23 of the CPU 14 issues an interrupt to the control unit 2G of the support processor 25 via the control line 28. This v1 interrupt is called a state change interrupt. This state change interrupt is only used when stopping a test or checking.
Occurs whenever the state of U14 changes.

The control section 26 of the lipo-1-processor 25 is as follows.

When a status change interrupt is received from the control unit 23 of the c p U 14, the support processor 25
(The Averating System prepared in the main storage device 29 of the 1-1 Brosset IJ25) is activated. This allows the support processor 25 to
0gram debugging is started. However, lipo-1-
Controller 1 to roll unit 261 of processor 25, CPU 1
4, the buffer 24,
The contents of the control register 20 in the CPU 14 are read via the data line 27 to know the state of the CPU 14. If the state is test i~stop or check stop, the control unit 2G of the ribo-1~processor 25 accesses the control unit 23 of the CPU 14 again and reads the test stop cause code (register 17) or the check stop. Read the stop cause code (register 18).

Therefore, ribo-1 to processor 25 are CPL114
It is possible to know the state of the computer and the cause of the interrupt.

[Optical Effects] As detailed above, according to the present invention, the debugger program is stored in the main memory of the processor from revo-1, and debugging is performed by the support processor. There is no risk of it being destroyed by a program that

Also, a special 1? that overrides the need for debugging operations by the processor (different from the normal CPU stop state)?
Since the stopped state and the factors that led to this state can be set, and the contents of these settings can be read from the supporting processor, debugging can be easily performed. Furthermore, according to the present invention, even if there are multiple processors (N), the debugger only needs to be aware of one CPU, so the structure of the debugger itself can be simple.

[Brief explanation of the drawing]

The drawing is a block diagram showing the structure of a data processing device according to an embodiment of this optical device. 11... the above ti device, 12... interrupt vector, 1
4...CPU, 1G...Register (test stop factor mask register), 17...Register (test stop factor code register), 18...Register (check 1
7 stop factor code resisque), 20...1ttll f
il register, 23.26...control section, 25
... Ribo-1 ~ Processusa. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] Stores information indicating various states of the CPU, including a support processor that can directly access the CPU, and special stop states that require debugging operations by this 1NOVO-1~BROSETZER, and can be read and written by the control unit of the CPU. 1fHfl, which indicates the interrupt factor that caused the special 17 stop state, is stored in a register that can be read by the support processor, and is readable by the roll unit in the controller 1 of the CPU. When an interrupt factor is generated, it is determined whether or not the CPU is to be placed in a special stop state, and the first and second registers are readable according to the result of this determination.
A means to update the contents of the register and when the CPU's condition changes: t! means for issuing a state change interrupt from the CPU to the CPU 1-processor; A data processing device characterized in that, when a second register indicates that the CPLI is in a special stop state, an interrupt factor is determined based on the contents of the second register.