JPS6048569A - Input/output processing device - Google Patents

Abstract

PURPOSE:To execute easily an inspection by providing a flag for setting a data turning-back mode, on a memory access part in an input/output processing device, and transferring a data by using a buffer by the input/output processing device. CONSTITUTION:In a memory access part 10, a turning-back mode is set by inputting a turning-back mode setting signal 71 to a register 54 from a channel control part 11. A request code 73 from a data transfer control part 12 is received by a reception control part 55, and a write data 63 is selected 51 and written in a write data register 50. Subsequently, the data of the register 50 is written in a buffer 53 by a turning-back mode flag signal 67. An output 1 of the reception controlling circuit 55 is a signal 68 of a level ''0'', therefore, an AND57 is closed and a signal 59 to a control device 2 is not sent out. Next, in accordance with a read-out request 73, the reception controlling circuit 55 outputs the data of the buffer to a line 66, and outputs a reply signal to a line 75 from a reply controlling circuit 56. In this way, an input data is turned back as it is, and a circuit is checked easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to an input/output processing device in a data processing device, and particularly relates to a data transfer method during device inspection.

(2) Description of the Prior Art Conventionally, when inspecting an input/output processing device, the entire system including the input/output device, system control device, main storage device, arithmetic processing unit, etc. is used to check I/O instructions and data. Inspection of input/output processing equipment such as transfer was conducted. In particular, when inspecting data transfer that includes input/output devices,
Data input/output operations were inspected using the system control unit and main storage. Therefore, if the system control device or main storage device cannot be used due to a failure, or if there is no host device such as the system control device, such as when testing a unit due to expansion, data transfer including input/output devices cannot be inspected. It had the disadvantage of not having

(3) Detailed Description of the Invention The present invention has been made by focusing on the above-mentioned drawbacks of the conventional technology, and therefore, an object of the present invention is to provide a data return mode flag in a buffer in an input/output processing device.
To provide a new input/output processing device which solves the above drawbacks and enables data transfer to and from the input/output device using a buffer in the input/output processing device even without a system control device or main storage device. There is a particular thing.

(4) Structure of the Invention In order to achieve the above object, an input/output processing device according to the present invention has a buffer that temporarily holds data from a main storage device, and has a buffer that allows communication between a plurality of input/output devices and the main storage device. An input/output processing device that controls data transfer includes a flag for setting a loopback mode in the buffer, a circuit for writing data to be written to the main storage device into the buffer during an input operation from the input/output device, and The circuit is configured to include a circuit that reads and sends data from the buffer during output operation to the input/output device, and when the loopback mode flag is set, data transfer between the input/output device and the main memory is controlled. It is characterized in that it is executed using the buffer in the output processing device.

(5) Detailed Description of the Invention Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, the system control device 2 includes a signal line 20
, 21 and 22, the main storage device 1, the input/output processing device 3,
It is connected to the arithmetic processing unit 4 and controls the traffic of requests from the input/output processing unit 3 and the arithmetic processing unit 4 to the main storage device 1 . The input/output processing device 3 also includes input/output devices 41 to 4.
n and I/O interfaces 291 to 29n, and controls data transfer between the main storage device 1 and the input/output devices 41 to 4n.

To explain the configuration of the input/output processing device 3, the input/output processing device 3 is connected to the system control device 2 by a signal line 21 and receives data transfer requests from the channel control section 11 and data transfer control section 12 to the main storage device 1. a memory access unit 10 that controls the execution of I/O instructions, a channel control unit 11 that controls execution of I/O instructions, etc. using microinstructions, a data transfer control unit 12 that controls data transfer, and a channel selection unit that determines the priority of data transfer. 13 and channels 141 to 14n, each of which has a signal line 23, 24, 25, 26, 27, 28.
1 to 28n.

Normal input/output operations are started by the arithmetic processing unit 4, control information for executing input/output instructions is brought from the main storage device 1 by the channel control unit 11, and this control information is transferred to the data transfer control unit 12. By setting the channels 141 to 14n, data transfer to the input/output devices 41 to 4n can be performed using the channels 141 to 14n, the channel selection unit 13,
The data transfer is performed with the main storage device 1 through the data transfer control section 12 and the memory access section 10.

Here, a detailed explanation will be given with reference to FIG. 2 showing the details of a memory access unit which is a main part of an embodiment according to the present invention.

FIG. 2 shows a memory access section 10 in the input/output processing device 3.
This is an example of executing data wrapping. The memory access section 10 includes a channel control section 11 and a data transfer control section 12.
are connected by write data 62, 63, requests and request information 72, 73, return mode setting signal line 71, read data 65, 66 and reply signals 74, 75 to channel control section 11 and data transfer control section 12. There is. The memory access section 10 is also connected to the system control device 2 through write data 57, read data 58, request information number 59, and reply signal 60, and performs data transfer with the input/output processing device. In the memory access unit 10, data from the channel control unit 11 and data transfer control unit 12 is selected by the selector 51, set in the write data register 50 by the signal line 61, and sent to the system control device 2 by the output signal line 57. Ru. Further, the signal approximately 57 is input to the selector 52 together with the read data 58 from the system control device 2, and the output signal 6 is inputted to the selector 52.
4 is input to the buffer 53 for temporary data storage,
Retained. Output signals 65 and 66 from this buffer 53 are sent to the channel control section 11 and data transfer control section 12 as reply data. The selection of write data 62 and 63 is performed by the reception control circuit 55 based on request signals and request information 72 and 73 from the channel control section 11 and data transfer control section 12.

The read data selector 52 normally selects the read data from the system control device 2, and is switched by the output signal 67 of the return mode flag register (acceptance flip-flop) 54 of the data return mode flag signal 71. Further, the output signal 67 is input to the reception control section 55. One output signal 68 of the return mode flag register 54 is inputted to the AND circuit 57 together with the request signal 70 from the reception control circuit 55 to generate a request signal 59 to the system control device 2. Further, the reception control circuit 55 is connected to the reply control circuit 56 by a signal line 76, and creates write and read addresses 69 for the buffer 53. Furthermore, the reply signal 60 from the system control device 2 is input to the reply control circuit 56 and is sent as a reply signal 74 to the channel control section 11 and data transfer control section 12.
．． 75 is generated.

Here, the operation when the return mode flag of the present invention is set will be explained in detail. Loopback mode flag register 54
It is assumed that the logic value "1" is set by the setting signal 71 from the channel control section 11. There are various methods of setting this register, including a setting method using a microinstruction, a setting method using a switch, and a setting method using a register shift. book flip flop 54
By becoming the logical value "1", the person input selector 52 for the buffer 53 selects the data to be written to the synudem control device 2. Further, an output signal 67 having a logical value of "1" is input to the reception control circuit 55, and controls the data write enable signal to the buffer 53 and the write and read addresses 69 to the buffer 53. The signal 76 is also input to the reply control circuit 56, and reply signals 74 and 75 to the channel control section 11 and data transfer control section 12 are also generated. In addition, one output signal 68 having a logic value of "0" is input to the AND input 57, and suppresses the request signal 59 to the system control device 2 when the return mode flag flip-flop 54 is set.

Here, input/output transfer from the input/output device when the return mode flag is set will be explained.

For input transfer from input devices 41 to 4n, channel 14
1 to 14n, write data 63 to the main storage device 1 is sent to the memory access unit 10 through the data transfer control unit 12 at the same time as the request request code 73. At the same time that the reception control unit 55 receives the request 73, the write data 63 is selected by the selector 51 and written to the write data register 50.The reception control circuit 55 also selects the write data 63 using the selector 51 and writes it to the write data register 50. Generates a write enable signal to the write address 69
Write the write data to the location, and then update the write address to the next write address.

Since the request signal 70 with the logic value "1" from the reception control circuit 55 is input to the AND circuit 57 together with the signal 68 with the logic value "0", the request signal 59 to the system control device 2 is not sent. Further, a reply signal 75 to the data transfer control section 12 is also generated by the replay control circuit 56 based on a signal 76 from the reception control circuit 55. In this way, each time a write data request comes, data is stored in the buffer 53 and the write address 69 is updated.

On the other hand, during output operation, when a main memory read request is received by a request signal and request code 73, it is processed by the reception control circuit 55 in the same way as a write request to the main memory 1, and the request to the system control device 2 is processed. Signal 59 does not appear. When the reception control circuit 55 receives a main memory read request, it reads the data set in the buffer 53 and returns it to the data transfer control unit 12 through the read data line 66, and at the same time, receives No. 46 and 76 from the reception control circuit 55 and replies. The control circuit 56 sets the reply signal 75 to the data transfer control unit 12 to logical value "1". Also, the read address 69 of the buffer 53 is updated.

In this way, in order to confirm the normality of input/output operations with the input/output device, during output operations, set data predetermined by the microprogram in the buffer 53 and then activate the channel. Data can be sent to the input/output device, and during input operation, data with a pattern different from the written data is written to the buffer, and after the input operation has started, the contents of the buffer are read by the microprogram and the microprogram By comparing the data with the block diagram, it is possible to check whether input/output operations were performed normally.

By creating a loopback mode flag as described above,
It is possible to provide an input/output processing device that can transfer data to and from the input/output device using a buffer within the input/output processing device.

(6) Detailed Description of the Invention As explained above, the present invention has a configuration in which a flag is provided to set the data loopback mode and data can be transferred using a buffer within the input/output processing device. ,
This has the advantage that data transfer of the input/output processing unit can be inspected without the need for a system control unit or main memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system configuration and an interior of an input/output processing device showing an embodiment of the present invention, and FIG. 2 is a detailed block diagram of a memory access section shown in FIG. 1. 1... Main storage device, 2... System control device, 4... Arithmetic processing device, 3... Input/output processing device, 41-4
n... input/output device, 10... memory access section, 11... channel control section, 12... data transfer control section, 13... channel selection section, 141-14n... channel, 51, 52... selector, 50... write data register, 53...Buffer, 5
4...Return mode flag register, 55...Reception control circuit, 56...Reply control circuit, 57...AND circuit lrM#'l' Applicant H Hondenki Co., Ltd. Representative Patent Attorney Yutabe Kumagai

Claims (1)

[Claims] An input/output processing device that has a buffer that temporarily holds data from a main storage device and controls data transfer between a plurality of input/output devices and the main storage device, a flag to be set; a circuit that writes data to be written to the main memory device into the buffer during an input operation from the input/output device; and a circuit that reads and sends data from the buffer during an output operation to the input/output device. an input/output device, characterized in that when the return mode flag is set, data transfer between the input/output device and the main storage device is performed using the buffer within the input/output processing device. .