JPS6048551A - List data access controlling system - Google Patents

Abstract

PURPOSE:To execute processing at a high speed by holding a list data read out by a memory controlling circuit, in plural registers, executing an access to one register selected among them, and executing continuously a memory access when an address is read out. CONSTITUTION:A list data read out of a memory 16 is accumulated in one of a CAR (chamber of the left side) register 27 or a CDR (chamber of the right side) register 28 by a multiplexer 26. Subsequently, the data is selected 19 by a microprogram control device 17, bypass paths 34, 35 are selected, and it is bypassed to a list address register 22 through a selector 20. A pointer stored in the register 22 is read out through a selector 25, and supplied as an access address to the memory 16. The CDR of the same cell is placed in the next address of the CAR in the memory, and a +1 adding circuit 23 adds ''1'' to the address of the CAR and executes read-out of the CDR continuously after the CAR. In such a way, as far as the data read out of the memory 16 is a pointer to other cell, it is bypassed and controlled at a high speed.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to an access control circuit C2 of a memory device.

In particular, the present invention relates to a list data access control method in which list-structured data is accessed (=, reading or by pre-controlling the next access using the list data pointer to access the list at high speed).

[Technology background]

Conventional memory access control methods are those in which data is accessed without advance control based on the address specified by CIU, or data at consecutive addresses is accessed in memory even when advance control is performed. It was assumed that data at the ninth address was read out in advance.

However, in devices such as the 17FF (Lis), where a series of data is not normally stored in concatenated addresses in memory, addresses at discontinuous locations must be set in the address register each time it is accessed. However, when data is read using the conventional advance control method described above, there is a drawback that there is little possibility that the read data will be used.

[Object and structure of the invention]

An object of the present invention is that when accessing list-structured data, if the data read from the memory indicates the address of the next cell, the next cell is retrieved in advance according to the address, and the list data is accessed. The goal is to make it a horse federation.

The present invention provides a data processing system that includes a memory device in which data having a list structure is stored and a memory control circuit that controls access to the memory device. The present invention is characterized in that it has a plurality of registers that hold read list data, and one of the registers performs continuous memory access when reading from a memory device or representing list data or an address.

[Embodiments of the invention]

Below (-1) The present invention will be explained in detail according to Examples.

Here, a data processing system that is capable of list data processing using the list processing language LIMP will be described as an example.

Figure 1 shows the cell structure of list data in the LISI language.In Figure 1, 1 is a cell, 2 is control data, and 3 is C
AR part, 4 represents CD, R part 0 CAR is a pick-up function that takes out the head of the list, CDR represents the rest of the list 14
) 1, a pointer to the storage position of the first value in the list is placed in the CAR section 3, and a pointer to the next cell in the list is placed in the CDR section 4.

FIG. 2 (α) shows an example of the structure of data written using the cells shown in FIG. 1.

FIG. 2(b) shows it in the form of a corresponding binary launch list. Note that NIL represents empty or false. In the figure, 5 to 10 are cells, 11 to 3 are data (
or the value 1-0, thus CAR and C
According to the method of the present invention, for example, in the case of accessing cell 5, the CAR (left side chamber) is first read. Data 11 (X
), then read the CDR (right side chamber) and access the CAR of cell 6 continuously and CI
) can be executed without U's intervention.

FIG. 3 is a block diagram of one embodiment of a memory fi7υ control circuit to which the 9-inventive method is applied.

In the figure, 14 is a CPU, and 15 is a memory control circuit.

16 is a memory, 17 is a microprogram control device, 1
8 is a decoder, 19 and 20 are selectors.

21 is an address addition circuit, 22 is a list/address register, 23 is a +1 addition circuit, 24 is an address register,
25 is a selector, 26 is a multi-flexor, 27 is a CAR
28 is a CDR register, 29 is a non-list register, and 30 is a selector.

31 is a data register, and 32 is an address bus.

33 represents a data bus.

The feature of this circuit is that between the CPU 14 and the memory 16,
Bypass paths 34 and 35 are provided so that data read from the memory 16 can be used immediately as an address.

First, there are two cases of access control for non-list data. The address output from the CPU 14 to the address register 24 is temporarily stored in the address register 24, and then read from the selector 25
6. Non-list data read from memory 16 is transferred from multiplexer 26 to non-list register 29.
After being once stored there, it is output to the data bus 33 via the selector 30 and data register 31, and then sent to the CPU 14.

On the other hand, in the case of list data access control, C2 is read from the memory 16 or stored in the CAR register 27 or CD by the multiplexer 26.
3.4.35 Bypassing from the CAR register 27 or the CI) R register 28 to the selector 19 by controlling the selector 19 by the microprogram control device 17 after the data is stored in one of the R registers 28.
Select.

It is bypassed to the list address register 22 via the selector 20. At this time, the selector 20 is the selector 1
It is controlled to select 9 outputs.

Note that the address adder circuit 21 is selectively used when address modification is required, and is not directly related to implementing the present invention, so a description thereof will be omitted.

The pointer stored in the list address register 22 is
It is read out via the selector 25 and supplied to the memory 16 as an access address. To read the CAR of a cell, follow the procedure described above.

The contents of CAR register 27 are listed in list address register 2.
2, and the CAR is read out from the memory 16 using the contents of the register as an address.

The CDR of the same cell is located at the next address of the CAH in memory. +] Adding circuit 23.

Add 1 to the CAR address or pointer and select this CD
Generate an address for R. This allows one cell's CA
After accessing R using a pointer, C
Reading of DR is performed.

In this way, as long as the data read from memory 16 is a pointer to another cell, bypass path 34.3
5, advance control of memory access is performed continuously.

FIG. 4 is an example of list data for explaining the operation of the embodiment circuit shown in FIG. 3, and FIG. 5 is an explanation showing the read program and the contents of each register when the program is executed. It is a diagram.

The list data shown in FIG. 4 includes three cells A.

Consists of B and C. The CAR of cell A is at address 100, and its contents are pointer address 1000 to the address indicating the memory location where the value X of CAH is stored. The CDR of cell A is located at address 101, and its content is a pointer address 200 that provides the CAR of cell B.

The content of CAR in cell B is a pointer address 2000 indicating the memory location where the value Y is stored. Also, the addresses of CD and R of cell B are 201, and the contents are pointer address 300 that gives the CAR of cell C.
It is. The contents of CDH of cell C are X dimension IL.

The program shown in 9 diagrams in FIG.

This is a LISP language program converted into an intermediate language M2 program using an ink printer. ■ to ■ represent each step. below.

The execution operations will be explained in order with reference to FIG.

In step ■, address もlO for Firefly's first cell person.
O” is stored in the list address register 22 by the CPU 14.
is set to

In step ■, the CAR of cell A located at address 00" in memory]6 is accessed, and its contents are OOO"
is taken out to the CAR register 27.

At this time, as advance access control, address ']01"
Access the CDR and copy the contents "'200" to the CDR.
CA stored in the register disk 28 and taken out earlier,
It identifies that the data in the R register 27 is a pointer address, accesses that address, and stores the contents 1X.
“ is taken out and placed in the CAR register 27.

In step (2), the contents of the CAR in cell A are read and the next CAR in cell B is accessed.

Therefore, in the previous step (2), data 1X", which is fetched from the CAR register 27, is transferred to the data register 31, and then memory access is performed using the CAR address 1200" of cell B (which is fetched from the CDR register 28). , reads its content '2000' to the CAR register 27. Here, in the same way as in step (3), as a preliminary access control, the CDR at address "201" is accessed, its contents 1300" are taken out to the CDR register 28,
Subsequently, it identifies that the data '2000' in the CAR register 27 is a pointer address, accesses that address, and takes out and stores the content 1Y'' in the CAR register 27.

In step (2), the content of CAR in cell B is 1Y'/.

The CAR of the primary cell C is accessed by reading from the CAR register 27 to the data register 31.

The CAR address is 1300'' taken out to the C]) R register in step (2), and this is used to access the memory, and the content ``NIL'' is taken out to the CAR register 27.

In step (2), the contents of the CAR in cell C are extracted from the CAR register 27 to the data register 31.

From the above (2), the list data X, Y, and NIL for each of cells A, B, and C can be easily viewed from the memory 16 to the CPU 14 by an instruction with a small number of program steps from the CPU 14.

〔Effect of the invention〕

According to the present invention, the memory access control circuit automatically inspects list data and performs advance access control when the list data is a pointer address to another cell, so that the list data access process as a whole is significantly improved. It can be made faster.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the equal structure of the cell, εIN Figure 2 (ex)
I (15) An explanatory diagram of purchasing beam strike data, Fig. 3 is a configuration diagram of one embodiment of the present invention, Fig. 4 is a diagram showing the purchase of beam strike data.
A diagram showing an example, Figure 5, is a certain LI! about the list data of Figure 4! It is an explanatory diagram of one example operation. In the figure, 14 is a CPU, and 1.5 is a memory control circuit. 16 is a memory, 17 is a microprogram controller a+
19.20, 25.30 are selectors, 22 is a list address register, and 26 is a multiplexer. 27 is a CA i< register, and 28 is a CDR register. 31 represents a data register. Patent applicant Fujitsu Limited

Claims (2)

[Claims] (1) In a data processing system that includes a memory device in which data having a list structure is stored and a memory control circuit that controls access to the memory device, the memory control circuit controls list data read from the memory device. With multiple registers to hold. an access means for accessing the memory device as a first data address in one register selected from the plurality of registers, and continuously accessing the memory when reading from the memory device or writing data represents an address 1. List data access control method. (2) In the list data access control method described in item 1 above, data with a list structure is
The plurality of registers that are in the form of a concatenation of cells consisting of DR and that are read from the memory device and hold the stored data include a CAR register and a CDR register, and the access to the CDH is performed following the CAR access, and the read C
I) A list data access control method characterized by continuously accessing the address indicated by R.