JPS6042492B2 - Processing phase execution control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processing phase execution control method, and in particular, a processing phase is divided into a plurality of partial processing phases and stored in an external storage device in advance, and the partial processing phases are sequentially transferred to the main memory during execution. In a data processing system, a processing phase that integrates multiple partial processing phases is prepared, and either the partial processing phase or the integrated processing phase is executed depending on the amount of memory available on the main memory. This invention relates to a processing phase execution control method.

In a large-scale processing program such as a compiler, if the load module size of one stage (phase) of the processing process exceeds the minimum required storage capacity in the design, conventional methods divide the phase into multiple parts and store intermediate text in each phase. This problem was solved by adopting a so-called bus division method in which the phases are sequentially processed. The code generation phase of a compiler will be explained as an example.

Now, the code generation phase of a certain compiler is instruction A,
Assume that code generation processing for B, C, D, E, F, G, and H is performed. The code generation routine for each instruction is 20KB each.
Assuming that the size of 1 processing phase is 40K, the minimum required storage capacity of this compiler is
Suppose that it is B. At this time, the code generation phase is divided into four parts as shown in FIG. 1 and executed sequentially. That is, first, phase 1 is loaded onto memory (main memory), processes instructions A and B, and writes intermediate text to external memory.

Next, phase 2 is loaded onto the memory, reads the intermediate text written by phase 1, processes instructions C and D, and writes the intermediate text to external storage. Phase 3 and phase 4 are subsequently loaded in the same manner. According to this, only one phase (size 40KB) is loaded at a time, so if there is 40KB of memory, instruction A-
This means that H can be processed. The above is the conventional technology.
By the way, in the above method, even if more memory than 40 KB (for example, 160 KB) is provided, the four phases will still be loaded in sequence and the intermediate text will still be read and written four times, which will reduce the processing time. is not shortened.

In other words, there is a drawback that the extra memory is not used effectively. An object of the present invention is to solve the above-mentioned problems, make effective use of memory, and shorten processing time, and for this purpose, the present invention divides a processing phase into a plurality of partial processing phases in advance. In a data processing system that stores data in an external storage device and sequentially transfers it to main memory during execution, a processing phase that integrates the plurality of divided processing phases is prepared in the external storage device, and a processing phase that integrates the plurality of divided processing phases is prepared in the external storage device. means for sequentially executing a plurality of processing phases, means for executing the integrated processing phase, size parameter holding means for holding size parameters of each of the processing phases, and the amount of usable memory on the main memory. a memory amount detecting means for detecting the amount of memory; a means for sequentially executing the plurality of processing phases by comparing the size parameter and the amount of available memory in the main memory; and executing the integrated processing phase. The present invention is characterized by comprising a memory amount determining means for activating one of the means, and variably controlling the execution method of the processing phase depending on the amount of usable memory on the main memory.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram illustrating a processing method according to the present invention. In the present invention, as shown in FIG. 2, a new processing path is provided in parallel with the conventional processing path, and by executing a phase that combines all instruction processing routines, processing of all instructions is carried out in one step.
Allows you to do it in one read and write. This new phase has a size of, for example, 160 KB, so a judgment is made before processing, and if the amount of memory given to the processing phase is 160 KB or more, the new phase is executed, otherwise the conventional Control is performed so that the four phases are executed in sequence. According to this, when 160KB or more of memory is given, phase 5 is loaded and all instructions are processed on one bus, so the number of phase loads is reduced from 4 to 1.
The number of times the intermediate text is read and written is reduced from four times to one time each time, and the processing time is significantly reduced.

In other words, the extra memory can be used effectively.
Here, for example, the processing routine for instruction A in phase 1 and the processing routine for instruction A in phase 5 can be exactly the same.

Therefore, each processing routine in Phase 5 can be developed in common with the routines in Phases 1 to 4, and the effort required to create them does not increase much. Hereinafter, the operation of the present invention will be explained using examples.

FIG. 3 is a functional block diagram of a data processing device according to an embodiment of the present invention, in which 1 is an external storage device for storing processing phases, 2 to 5 are partial processing phases, and 2 is an instruction A, B 3 is a phase for processing instructions C and D; 4 is a phase for processing instructions E and F; 5 is a phase for processing instructions G and H; 6 is a phase for processing instructions A - an integrated phase for processing H; 7 is an execution control means for sequentially executing divided processing phases; 8 is an execution control means for executing an integrated processing phase; 9 is a usable processing phase. means for detecting the amount of memory; 10 is a size parameter holding unit; 1
1 a means for determining whether the amount of available memory is equal to or greater than a threshold; 12 a processing phase storage section in the main memory;
Reference numeral 13 denotes an external storage device for storing input/output data of the processing phase. In FIG. 3, parameters indicating the size of each processing phase 2 to 6 in the external storage device 1, that is, the size of the memory capacity, are set in advance in the size/parameter holding unit 10.

Then, by a control means (not shown), commands A to H are
When instructed to perform the code generation process up to
First, the memory amount detection means 9 is activated. The memory amount detection means 9 detects the size of the processing phase storage section 12 by referring to a storage section (not shown) that holds information indicating the size of the processing phase storage section 12 in the main memory.
Note that the size of the processing phase storage section 12 is not constant, but is set variably as various processes in the data processing apparatus progress. The memory amount detection means 9 is the determination means 11.
At the same time, the detected memory amount information is sent to the determining means 11. The activated determining means 11 compares the memory amount information detected by the memory amount detecting means 9 and the size parameter held in the size parameter holding section 10. Note that the determining means 11 uses the sum of the size of the integrated processing phase 6 and the size of the resident control phase (not shown) as a threshold value, and compares this threshold value with the above-mentioned memory amount information. Then, when the memory amount information indicates less than the threshold value, the determination means 11 activates the execution control means 7. Further, when the memory amount information indicates a threshold value or more, the determination means 11 activates the execution control means 8. When the execution control means 7 is activated, the execution control means 7 executes the divided processing phases 2 to 2.
5 in sequence. That is, first, processing phase 2
is transferred to the processing phase storage unit 12 and executed. Processing phase 2 returns this result to external storage device 13. Next, processing phase 3 is transferred to the processing phase storage unit 12 and executed in the same manner as above. Thereafter, execution up to processing phase 5 is performed in the same manner. On the other hand, when the execution control means 8 is activated, the execution control means 8 transfers the integrated processing phase 6 to the processing phase storage section 12 and causes it to be executed. After the execution is completed, the results are returned to the external storage device 13. FIG. 4 is a diagram illustrating the state of the main memory, in which A indicates the case where the memory amount is less than the threshold value, and B indicates the case where the memory amount is greater than the threshold value.

Note that in A, the horizontal direction does not indicate the size of the memory amount, but indicates the change in the stored content. As explained above, according to the present invention, a new phase is provided that integrates the functions of each phase divided into buses, and when the amount of memory given is at least the minimum required amount of memory or slightly more than that, it is processed as before. Each phase divided into buses operates sequentially and processes are performed on multiple buses, and when the amount of memory provided is sufficiently greater than the minimum required amount of memory, the integrated phase operates and uses fewer buses. Since the processing can be performed, the number of buses can be reduced when a sufficient amount of storage is provided, and the processing speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing conventional division processing, FIG. 2 is a diagram explaining a processing method according to the present invention, FIG. 3 is a functional block diagram of a data processing device according to an embodiment of the present invention, and FIG. 4 is a main memory FIG.

Claims (1)

[Claims] 1. In a data processing system in which a processing phase is divided in advance into a plurality of partial processing phases and stored in an external storage device, and the partial processing phases are sequentially transferred to a main memory during execution, the plurality of divided processing phases are stored in the external storage device. A means for sequentially executing the plurality of divided processing phases, a means for executing the integrated processing phase, and a size/parameter for holding the size/parameter of each processing phase. a parameter holding means, a memory amount detection means for detecting the amount of usable memory on the main memory, and comparing the size parameter with the amount of usable memory on the main memory;
The method includes a means for sequentially executing the plurality of processing phases, and a memory amount determining means for activating either of the means for executing the integrated processing phases, depending on the amount of usable memory in the main memory. A processing phase execution control method characterized by variably controlling an execution method of a processing phase.