JPS6048546A - Resetting system - Google Patents

Abstract

PURPOSE:To realize a continuous processing by constituting a central processing unit so as to restart the processing from the processing which is executed before a runaway is generated, when an information processing system goes to a reset state. CONSTITUTION:If a central processing unit CPU falls into a runaway state when it is executing, for instance, a partial processing J3; it is feared that the stored contents of a storage device MEM or the accumulated contents of a built-in register of the CPU are broken down, but since a reset address selector SEL and a reset address register REG are protected by a key word identifying part KY, a reset address a3 which is being set to the reset address register REG is held without being broken down. When a monitor time limiting circuit TM transfers a reset signal (rst) to the central processing unit CPU, the CPU refers to the set address register REG, extracts the reset address a3, initializes the memory, the register, etc., and thereafter, it is restarted from the partial processing J3.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an information processing system, and in particular to an information processing system that enables resumption of interrupted partial processing when a central processing unit that has gone into a runaway state is reset. Regarding the method.

(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional reset method in this type of information processing system, and FIG. 2 is a diagram showing an example of the processing process in FIG. 1.

In FIG. 1, the central processing unit CPU is connected to the storage device MEM.
The address a is sequentially transmitted to the address a, and a predetermined process is executed based on the extracted data d. The entire processing process executed by the central processing unit CPU consists of three partial processes J1, J2 and J3, as shown in FIG. In addition, the central processing unit 1CPU always uses a monitoring time limit circuit TM during the entire processing process.
The access signal ac is transmitted to the access signal ac. The monitoring time circuit TM is
If the access signal ac is not transmitted again within a predetermined time after the access signal ac is transmitted from the central processing unit CPU, it is determined that the central processing unit CPU has fallen into a runaway state, and the central processing unit CPU is reset. A signal rst is transmitted. When the central processing unit CPU is executing the partial processing Jl to J3 in the royal palace, the central processing unit CPU monitors the access signal ac within the predetermined time period using the time limit circuit T.
However, the central processing unit cpu is transmitting the partial processing to J.
If a runaway condition occurs while executing I to J3, the access signal ac will not be transmitted to the monitoring time limit circuit TM until any time.
The monitoring time limit circuit TM transmits a reset signal rst to the central processing unit CPU after the predetermined time has elapsed. The central processing unit CPU that receives the reset signal rst enters the reset state, and all the stored contents of the storage device MEM that may have been destroyed due to the runaway state, as well as the stored contents of the built-in registers (not shown) of the central processing unit CPU are deleted. After initial settings,
The process restarts from the first partial process J1.

As is clear from the above explanation, in a conventional reset method, the central processing unit CPU that has fallen into a runaway state and has been transmitted with the cent signal rst from the monitoring time limit circuit TM and has entered the reset state is always in the first part. Since the process restarts from process J1, there is a drawback that continuity with the process before the runaway state cannot be maintained. Note that once the processing is interrupted, as a means of restarting from the interrupted processing, the interrupt program stored in the storage device MEM is reset by the reset signal rst.
It is also possible to start with the storage device MEM.
In a runaway state in which the stored contents of the system are uncertain, there is no guarantee that restarting by such interrupt processing will be successful.

(C) Object of the Invention The object of the present invention is to eliminate the drawbacks of the conventional reset method as described above, and to realize a means that enables restarting as much as possible of the processing process before the occurrence of the runaway state.

(d+ Structure of the Invention) This object is to provide an information processing system equipped with a monitoring circuit that monitors the operating state of a central processing unit and forcibly resets the central processing unit when a runaway state is detected. The entire processing process executed by the device consists of a plurality of partial processes, and there is a register for setting a predetermined address corresponding to each partial process when executing the partial process, and a register for setting a predetermined address corresponding to each partial process when executing the partial process. This is accomplished by providing means for preventing settings to the register, and restarting the interrupted partial processing based on the address being set in the register after the reset by the monitoring circuit.

(e) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing a reset method according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the processing steps shown in FIG. 1. Note that the same reference numerals refer to the same objects throughout the plan. In FIG. 3, the keyword identification section KY,
Reset address selector S 1 = 1- and reset address register REG are central processing unit Cl) U
is connected to boats P1 and P2. In FIGS. 3 and 4, the central processing unit CPU, before starting partial processing J1 as in FIG.
After transmitting a predetermined keyword to the keyword identification unit KY, the reset address selector SEL is notified of the start of partial processing J1. The reset address selector SEL selects a predetermined reset address a1 corresponding to the partial process J1 and sets it in the reset address register RIE G. After the above-mentioned sensor 1 head address setting process S1 is completed, the central processing unit CPU starts a partial process J1. After finishing the partial processing J1 and before starting the partial processing J2, the central processing unit CPU transmits the keyword from the boat P1 to the keyword identification unit KY, and then transmits the keyword to the reset address selector S E 1. , of the start of partial processing J2. The address selector SEL to recessor 1 selects a predetermined or set address a2 corresponding to partial processing J2, and selects recessor l-'7'.
Set to EG in the address register ■. After the above reset address setting process S2 is completed, the central processing unit CPU
Then, partial processing J2 is started. After finishing the partial processing J2, and before starting the partial processing J3, the central processing unit CI
) U is for 1- I) Keyword identification part KY from 1
After transmitting the keyword to , the reset address selector SEL is notified to start partial processing J3. The reset address selector SEL selects the reset address a3 in a predetermined manner corresponding to the partial processing J3, and sets it in the reset address register REG. After the above cent address setting process S3 is completed, the central processing unit cpU
If so, partial processing J3 is started. During this process, if the central processing unit CPU goes into a runaway state while executing, for example, partial processing J3, then 1. There is a risk that the memory contents of the a device MEM or the contents stored in the built-in registers of the central processing unit CPU will be destroyed, but they will be protected by the reset address selector SEL and the seven soto address registers REG Let keyword identification section KY. Therefore, the current address a3 being set in the reset address register REG is held without being destroyed. When the monitoring time limit circuit TM transmits the reset signal rst to the central processing unit CI) U in a process similar to that shown in FIG. R
After extracting the reset address a3 set in EG and initializing the storage device MEM and built-in registers, the process resumes from the corresponding partial process J3.

As is clear from the above explanation, according to the present embodiment, a runaway state occurs during execution of the partial process J3, and the monitoring time limit circuit TM
Central processing unit CP to which the Karascent signal rSL is transmitted
U refers to the reset address register REG and is set by the reset address setting process S3 prior to the start of the partial process J3, and is maintained without being destroyed even in a runaway state, or restarts from the partial process J3 based on the cent address a3. Therefore, continuity with partial processing J3 before the occurrence of the runaway state is maintained.

Note that FIGS. 3 and 4 are only one embodiment of the present invention, and for example, the runaway state is not limited to that which occurs during the execution of the partial process J3, and is not limited to that which occurs during the execution of the partial process J1 and J2. It is also considered that the problem may occur during execution, but the effect of the present invention does not change in either case. Furthermore, the entire processing process of the central processing unit CPU is not limited to one consisting of three partial processes Jl to J3, and many other modifications may be considered, but the effects of the present invention can be achieved in any case. It doesn't change. Furthermore, it goes without saying that the configuration of the information processing system is not limited to what is illustrated.

(f) Effects of the Invention According to the present invention, in the information processing system, the central processing unit that has entered the reset state can restart from the partial processing that was being executed before the runaway state occurred, thereby improving the continuity of processing. is achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional reset method, FIG. 2 is a diagram showing an example of the processing process in FIG. 1, FIG. 3 is a diagram showing a seven-node method according to an embodiment of the present invention, FIG. 4 is a diagram showing an example of the processing process in FIG. 3. In the figure, a is an address, al to a3 are reset addresses, ac is an access signal, CPU is a central processing unit, d is data, Jl to J3 are partial processing, KY is a keyword, and MEM is a keyword. Storage device, II) 1
and P2 are baud 1 to baud, REG is a reset address register, rst is a reset signal, Sl to S3 are reset address setting processing, SEL is a reset address selector, and 1゛M is a monitoring time limit circuit.

Claims (1)

[Claims] In an information processing system equipped with a monitoring circuit that monitors the operating state of a central processing unit and forcibly resets the central processing unit when a runaway state is detected, the entire processing process executed by the central processing unit includes a plurality of processes. Consists of partial processing,
A register for setting a predetermined address corresponding to each partial process when executing the partial process, and a means for preventing setting of the register while the partial process is being executed, and a means for preventing the setting by the monitoring circuit. The re-cent method is characterized in that after a reset, the suspended partial processing is resumed based on the address being set in the register.