JP2595702B2 - I / O control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an input / output control method for a data processing device, and in an input / output control device in which a command being executed is forcibly terminated by the occurrence of a system reset, the command is forcibly terminated when a command is re-input. A main control unit including a central processing unit, a main storage device, and a channel control device, and an input / output device via the input / output bus 7 for the purpose of enabling command execution from the execution state at the time. In a data processing system comprising an input / output control device for performing interface control of an output device, a system reset signal bus for transmitting a system reset signal from the main control unit between the channel control device and the input / output control device; A system reset input display unit for displaying an input of the system reset signal in a control device; Means for recognizing an input of a system reset signal by the system reset input display unit to identify whether or not the input / output control device is executing a command in the control device; Means for storing, in the input / output control device, the execution state of the command executed immediately before the system reset, forcibly terminating the execution of the command, and initializing the input / output control device; When the command that has been forcibly terminated is re-entered after the signal is removed, means for enabling execution of the command to be started from the command execution state at the time of the forcible termination is provided.

[Industrial applications]

The present invention relates to an input / output control method for a data processing device.

2. Description of the Related Art In recent years, the processing capacity and storage capacity of an input / output device in a data processing apparatus have been remarkably increased, and the storage capacity of a hard disk drive or the like has become extremely large. Along with this, the central processing unit of the data processing device,
When a command is sent from a main control unit including a main storage device and a channel control device to an input / output device via the input / output control device, the execution time of the input / output control device often becomes extremely long. In particular, when the input / output control device performs a full-scale read / write test on the hard disk device, the test often takes a long time. However, during such a long operation, there is a high possibility that a system reset signal is input from the main control unit to the input / output control device asynchronously with execution of the command.

When the system reset signal is input, the command being executed is forcibly terminated, and the input / output control device is initialized, so that the system reset state is released, and when the command is executed again, the main control unit returns to the input / output control device. It is necessary to start and execute the command from the beginning again.
Therefore, when the system reset is performed, the execution state of the input / output control device that is executing the command is stored, and when the command is restarted, the command execution can be resumed from the execution state at the time of the forced termination due to the system reset. Such an input / output control method is required.

[Conventional technology]

FIG. 3 is a configuration diagram of an embodiment of an input / output control method in a conventional data processing device.

In the figure, 11 is the main control unit of the data processing device, 12 is the central processing unit, 13 is the main storage device, 14 is the channel control device,
15 is an input / output control device, 15a to 15f are components in the input / output control device 15, 15a is a microprocessor (MPU), 15b is a control register, 15c is an input / output bus interface control unit, and 15d is a read-only memory ( ROM), 15e is a random access memory (RAM), 15f is a hard disk control device, 16a is a hard disk device, and 17 is an input / output bus.

In FIG. 3, for example, when performing an entire-surface read / write test of the hard disk, a command is sent from the main control unit 11 to the input / output control device 15 through the input / output bus 17.
The command is received by a control register 15b having a role of a software interface with the main control unit 11 in the input / output control device 15 via the input / output bus interface control unit 15c in the input / output control device 15, and 15a. The microprocessor 15a performs internal control using an input / output control program or the like stored in the read-only memory 15d, and executes the above-mentioned command, in this case, the entire read / write test of the hard disk 16a.

Now, when a system reset signal is input from the main control unit 11 through the input / output bus 17 during execution of the command as described above, the signal is transmitted to the microprocessor 15a via the input / output bus interface control unit 15c and the like. Then, the microprocessor 15a forcibly terminates the execution of the above command, and executes the initialization program stored in the read-only memory 15d. For this reason, all the running information and the like stored in the control register 15b and the random access memory 15e are cleared, and the input / output control device 15 is set to the initial setting state.

The system reset is usually performed under the control of the main control unit 11.However, in the event of a system failure or the like, in order to reconfigure the system, the input / output control device 15 or the like is asynchronously executed with the execution process and hardware. Forcibly initialize the system components of. Therefore, the extent to which the input / output control device 15 has executed a command immediately before the input / output control device 15 enters a system reset is also determined by the main control unit in the input / output control device 15.
The state is not stored even in 11.

When the system reset state is released, the main controller 11
Replaces the previously executed command with the I / O controller 15
Send to However, as described above, since the record of how far the previous command has been executed is not stored anywhere, the command to be input again is input as a completely new command, and the input / output control device 15 executes the command from the beginning. Will be done. Therefore, even if the read / write test of the hard disk is performed for a long time before the system reset, the test is performed again from the beginning, and the execution time of the command is unnecessarily increased.

[Problems to be solved by the invention]

As described above, in the conventional input / output control method, when a system reset is input during command execution, the command being executed is forcibly terminated and the input / output control device is initialized, so that the system reset state is resolved. Later, there was a problem that the command had to be executed from the beginning.

SUMMARY OF THE INVENTION It is an object of the present invention to enable a command to be executed from the execution state at the time of forced termination when re-inputting a command in an input / output control device in which a command being executed is forcibly terminated by the occurrence of a system reset.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

In the figure, reference numeral 1 denotes a main control unit of the data processing device, which comprises a central processing unit (CPU) 2, a main storage device (MM) 3, and a channel control device (CHC) 4. Reference numeral 5 denotes an input / output control device for executing interface control between the channel control device 4 and the input / output device 6, and reference numeral 5a denotes a microprocessor (MPU) for performing internal control of the input / output control device 15 including equipment not shown. , 15b are control registers having a role of transferring processing information between the main controller 1 and the input / output control device 5 in the input / output control device 5, 6 are input / output devices, 7 is a channel control device 4 and an input / output control device. An input / output bus for transferring information between the input and output terminals, a system reset input display unit for receiving and storing a system reset signal from the main control unit, and a system reset signal provided as a part of the input / output bus Is a system reset signal bus for transmitting the data.

The present invention has the following means in addition to the above configuration. That is, while the input / output control device 5 is executing the command,
When a system reset state occurs in the main control unit 1, a system reset signal is sent from the main control unit 1 to the input / output control device 5 through the system reset signal bus 9,
This is stored in the system reset input display section 8. The system reset signal is sent to the microprocessor
The microprocessor 5a enters an initial setting process in order to transmit the information to 5a. At this time, the microprocessor 5a checks whether or not a system reset signal is displayed on the system reset input display unit 8.
When recognizing that the system reset signal is displayed, it is distinguished from an unconditional initial setting such as when the power is turned on,
It begins to identify whether a command is being executed or not. If the command is being executed, the execution state of the command is stored in the control register 5b, and then the command is forcibly terminated and the input / output control device 5 is initialized.

When the state of the system reset is released and the previously executed command is re-input from the main control unit 1, the microprocessor 5a and the control register 5b check the execution state of the previous command, and before the forced termination by the system reset. To execute the command except for the part that has already been executed.

(Operation)

In FIG. 1, when operating the input / output device, a command is sent from the main control unit 1 to the input / output control device 5 through the input / output bus 7. The command is transmitted to the microprocessor 5a via the control register 5b in the input / output control device 5, and the microprocessor 5a performs internal control including related circuits in the input / output control device 5 not shown in the drawing. Execute a command.

When a system reset state occurs in the main control unit 1 during execution of the command, the main control unit 1 sends a system reset signal to the input / output control device 5 through the system reset signal bus 9. The input / output control device 5 stores the signal in the system reset input display unit 8, and
The system reset signal is also transmitted to the microprocessor 5a and the control register 5b. The microprocessor 5a enters the initial setting operation by this. First, the microprocessor 5a accesses the system reset input display section 8 to check whether the system reset input is displayed. If there is a display of the system reset input, the execution state of the command in the memory not shown is confirmed and stored in the control register 5b. With the above termination, the microprocessor 5a forcibly terminates the execution of the command being executed, and initializes the input / output control device 5.

After the system reset state is released, the main control unit 1 sends the command to the input / output control device 5 again to execute the previously interrupted command again. Control register
5b, upon receiving this command, checks the execution state of the previous command stored and sends it to the main control unit 1, and obtains an instruction of a restart point from the main control unit 1, and the input / output control unit 5 Command execution can be resumed except for the part that has been executed before the reset.

〔Example〕

FIG. 2 is a configuration diagram of one embodiment of the present invention, and shows an example in which a hard disk device is used as an input / output device.

In the drawing, the same components as those in FIG. 1 use the same symbols,
1 is a main control unit of the data processing device, 2 is a central processing unit, 3
Is a main storage device, 4 is a channel control device, 5 is an input / output control device, 5a to 5f are components in the input / output control device 5, 5a is a microprocessor, 5b is a control register, and 5c is an input / output bus interface control. Section, 5d is a read-only memory (RO
M) and 5e are random access memories (RAM) and 5f is a hard disk controller (HDC). 6a is a hard disk drive (HDD), and 7 is an input / output bus. Reference numeral 8 denotes a system reset input display section which is constituted by a flip-flop circuit. Reference numeral 9 denotes a system reset signal bus.

In FIG. 2, when operating the input / output device, the main control unit 1 sends a command to the input / output control device 5 through the input / output bus 7. The command is transmitted to the microprocessor 5a via the input / output bus interface control unit 5c and the control register 5b in the input / output control device 5, and the microprocessor 5a stores a processing program inside the input / output control device 5. The read only memory 5a, the random access memory 5e, the control register 5b, the hard disk controller 5f, and the like are controlled to execute the command.

If a system reset state occurs in the main control unit 1 asynchronously with the execution of the command during the execution of the command, the main control unit 1 sends a system reset signal to the input / output control device 5 through the system reset signal bus 9. send. In the input / output control unit 5, the flip-flop circuit of the system reset input display unit 8 is set by the system reset signal, and the microprocessor 5a
The system reset signal is also transmitted to the control register 5b. The microprocessor 5a receives the signal at a reset terminal (not shown) and starts an initial setting operation. In the initial setting operation, the microprocessor 5a first accesses the system reset input display section 8 through the bus in the input / output control device 5 and checks whether or not the system reset input is displayed. If there is an indication of the system reset input, the microprocessor 5a checks the execution state of the command in the random access memory 5e, and checks the content thereof in the control register 5b.
To save the execution state. By the end above,
The microprocessor 5a clears information on the command being executed, which is stored in the control register 5b and the random access memory 5e, forcibly terminates the execution of the command, and sets the input / output control device 5 to the initial setting state.

When the system reset state is released, the main control unit 1
Stops the system reset signal sent to the system reset signal bus, so that the flip-flop of the system reset input display section is reset by the microprocessor 5. Thereafter, when the previously executed command is executed again, the main control unit 1 transmits the contents of the command execution state stored in the control register 5b directly to the input / output bus interface control unit 5c and the input / output bus 7. The command is read through the CPU, the execution state of the command is checked, and the restart position of the command is determined. I / O controller 5
As a result, the execution of the command is resumed from the part already executed before the system reset. If the main control unit 1 determines that the command is to be executed from the beginning, the command is executed again from the beginning.

As described above, even if the input / output control device 5 receives the system reset signal during the execution of the command and suspends the execution of the command, when the command is received again after the system reset state is resolved, it is necessary to execute the command again from the beginning. And the command execution time is reduced.

〔The invention's effect〕

As described above, according to the present invention, when the input / output control device receives a system reset signal asynchronously from the main control unit during execution of a command having a long execution time, the input / output control device performs Because the execution status of the previous command is set in the I / O controller,
This eliminates the need to execute the command from the beginning, shortens the command execution time, and improves the system throughput.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of a conventional embodiment. In the figure, 1,11 ... Main control unit 2,12 ... Central processing unit 3,13 ... Main storage unit 4,14 ... Channel control unit 5,15 ... I / O control unit 5a, 15a ... Micro Processor 5b, 15b Control register 5c, 15c Input / output bus device interface control unit 5d, 15d Read-only memory 5e, 15e Random access memory 5f, 15f Hard disk controller 6 Input / output Devices 6a, 16a Hard disk drive 7, 17 Input / output bus 8 System reset input display unit 9 System reset signal bus

Claims (1)

(57) [Claims] A main control unit (1) comprising a central processing unit (2), a main storage device (3) and a channel control device (4), and the channel control device (4) and an input / output bus 7 A data processing system comprising an input / output control device (5) for executing interface control of the input / output device (6) through the main control unit between the channel control device (4) and the input / output control device (5) A system reset signal bus (9) for transmitting the system reset signal from (1), a system reset input display section (8) for displaying the input of the system reset signal in the input / output control device (5), and In the entry output control device (5), the system reset input display unit (8) recognizes the input of the system reset signal and identifies whether the input / output control device (5) is executing a command. Means for executing the command executed immediately before the system reset when the input / output control device (5) is executing the command.
Means for forcibly terminating the execution of the command after being stored therein, and for initializing the input / output control device (5); and means for re-inputting the forcibly terminated command after the system reset signal is removed. An input / output control method comprising means for enabling execution of the command from the command execution state at the time of the forced termination.