JPS6355089B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an information processing system, and in particular, when a central processing unit that has gone into a runaway state is reset,
This invention relates to a reset method that allows restarting from an interrupted partial process.

(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional reset method in this type of information processing system, and FIG. 2 is a diagram showing an example of the processing process in FIG. 1. In FIG. 1, the central processing unit CPU sequentially transmits addresses a to the storage device MEM and executes predetermined processing based on extracted data d. The entire processing process executed by the central processing unit CPU consists of three partial processes J1, J2 and J3, as shown in FIG. In addition, the central processing unit CPU is
The access signal ac is always transmitted to the monitoring time limit circuit TM during the entire processing process. The monitoring time limit circuit TM determines that the central processing unit CPU has fallen into a runaway state when the access signal ac is not transmitted again within a predetermined time after receiving the access signal ac from the central processing unit CPU, and A reset signal rst is transmitted to the device CPU. When the central processing unit CPU is normally executing partial processing J1 to J3, the central processing unit CPU transmits the access signal ac to the monitoring time circuit TM within the predetermined time; is partial processing J1 to J
If a runaway condition occurs during execution of step 3, the access signal ac will not be transmitted to the monitoring time limit circuit TM until any time, so the monitor time limit circuit TM will transmit the reset signal rst to the central processing unit CPU after the predetermined time has elapsed.
Central processing unit CPU to which reset signal rst is transmitted
enters a reset state, and after initializing all the memory contents of the storage device MEM that may have been destroyed due to the runaway state and the accumulated contents of the built-in registers (not shown) of the central processing unit CPU, the first partial processing J1 is started again. Restart from.

As is clear from the above explanation, in the conventional reset method, the central processing unit CPU that has entered the reset state after receiving the reset signal rst from the monitoring time limit circuit TM due to a runaway state always performs the first partial processing. Since the process restarted from J1, there was a drawback that continuity with the processing process before the runaway state could not be maintained. Note that once a process is interrupted, a reset signal is sent to the interrupt program stored in the storage device MEM as a means of restarting from the interrupted process.
Although starting by rst is considered, in a runaway state where the storage contents of the storage device MEM are uncertain, there is no guarantee that restarting by such interrupt processing will be successful.

(c) Object of the Invention The object of the present invention is to eliminate the drawbacks of the conventional reset method as described above, and to realize a means that allows restarting as much as possible the processing process before the occurrence of the runaway state.

(d) Structure of the Invention The object is to monitor the operating state of the central processing unit and detect a runaway state when the entire processing process consists of a plurality of partial processes, and when the central processing unit executes the partial processes. In the information processing system, the information processing system includes a monitoring circuit that forcibly resets the central processing unit when the central processing unit is configured to perform the partial processing, and a keyword identification unit that identifies a predetermined keyword sent from the central processing unit prior to execution of the partial processing. and register means for selecting and setting a reset address corresponding to the partial processing start notification sent after the keyword is sent from the central processing unit, and after the reset by the monitoring circuit, the reset address is set in the register means based on the address being set in the register means. This is achieved by restarting the interrupted partial processing.

(e) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a reset method according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the processing process in FIG. 1. Note that the same reference numerals indicate the same objects throughout the figures. In Figure 3, the keyword identification section KY, reset address selector SEL, and reset address register are shown.
REG is central processing unit CPU ports P1 and P
Connected to 2. 3 and 4, before starting partial processing J1 as shown in FIG. 1, the central processing unit CPU transmits a predetermined keyword from port P1 to keyword identification section KY, and then transmits a predetermined keyword to reset address selector SEL.
The start of partial processing J1 is notified to . The reset address selector SEL selects a predetermined reset address a1 corresponding to the partial process J1 and sets it in the reset address register REG. After the above reset address setting process S1 is completed,
The central processing unit CPU starts partial processing J1.
After finishing the partial process J1 and before starting the partial process J2, the central processing unit CPU transmits the keyword from the port P1 to the keyword identifying section KY, and then notifies the reset address selector SEL of the start of the partial process J2. The reset address selector SEL selects a predetermined reset address a2 corresponding to the partial process J2 and sets it in the reset address register REG. After the above reset address setting processing S2 is completed, the central processing unit CPU starts partial processing J2. Partial processing J
After completing 2, before starting partial processing J3,
After transmitting the keyword to the keyword identification unit KY from port P1, the central processing unit CPU notifies the reset address selector SEL to start partial processing J3. The reset address selector SEL is
A predetermined reset address a3 corresponding to partial processing J3 is selected and set in the reset address register REG. After the above reset address setting process S3 is completed, the central processing unit CPU starts partial process J3. In this process, if the central processing unit CPU falls into a runaway state while executing partial processing J3, for example, there is a risk that the memory contents of the storage device MEM or the accumulated contents of the built-in registers of the central processing unit CPU will be destroyed. However, since the reset address selector SEL and the reset address register REG are protected by the keyword identification unit KY, the reset address a3 being set in the reset address register REG is held without being destroyed. The monitoring time limit circuit TM sends the reset signal rst to the central processing unit in the same process as in Fig. 1.
When transmitted to the CPU, the central processing unit CPU refers to the reset address register REG and sets the reset address a3 set in the reset address register REG in the reset address setting process S3.
After extracting and initializing the storage device MEM and built-in registers, the process resumes from the corresponding partial process J3.

As is clear from the above explanation, according to this embodiment, the central processing unit CPU, which falls into a runaway state while executing partial processing J3 and receives the reset signal rst from the monitoring time limit circuit TM, refers to the reset address register REG. However, the process restarts from the partial process J3 based on the reset address a3, which is set by the reset address setting process S3 prior to the start of the partial process J3 and is maintained without being destroyed even in a runaway state. Therefore, partial processing J before the runaway state occurs
3 and continuity is maintained.

Note that FIGS. 3 and 4 are only one embodiment of the present invention, and for example, a runaway state can be handled by partial processing J3.
The present invention is not limited to what occurs during the execution of J1 and J2, and may occur during the execution of the partial processes J1 and J2, but the effects of the present invention remain the same in either case. Further, the entire processing process of the central processing unit CPU is not limited to one consisting of three partial processes J1 to J3, and many other modifications may be considered, but the effects of the present invention can be achieved in any case. remains unchanged. Furthermore, it goes without saying that the configuration of the information processing system is not limited to what is illustrated.

(f) Effects of the Invention As described above, according to the present invention, in the information processing system, the central processing unit that has entered the reset state can restart from the partial processing that was being executed before the runaway state occurred, thereby improving the continuity of processing. is achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional reset method, FIG. 2 is a diagram showing an example of the processing process in FIG. 1, FIG. 3 is a diagram showing a reset method according to an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the processing process in FIG. 3. FIG. In the figure, a is an address, a1 to a3 are reset addresses, ac is an access signal, CPU is a central processing unit, d is data, J1 to J3 are partial processing, KY is a keyword identification unit, MEM is a storage device,
P1 and P2 are ports, REG is a reset address register, rst is a reset signal, S1 to S
3 represents a reset address setting process, SEL represents a reset address selector, and TM represents a monitoring time limit circuit.

Claims (1)

[Scope of Claims] 1. The entire processing process consists of a plurality of partial processes, and when the central processing unit executes the partial processes, the operating state of the central processing unit is monitored, and if a runaway state is detected, the above-mentioned In an information processing system comprising a monitoring circuit for forcibly resetting a central processing unit, the keyword identification unit identifies a predetermined keyword sent from the central processing unit prior to execution of the partial processing; and register means for selecting and setting a reset address corresponding to a partial processing start notification sent after the keyword is sent from the processing device, and after the reset by the monitoring circuit, the processing is interrupted based on the address being set in the register means. A reset method characterized by restarting from the partial processing.