JPS6046829B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6046829B2
JPS6046829B2 JP4288577A JP4288577A JPS6046829B2 JP S6046829 B2 JPS6046829 B2 JP S6046829B2 JP 4288577 A JP4288577 A JP 4288577A JP 4288577 A JP4288577 A JP 4288577A JP S6046829 B2 JPS6046829 B2 JP S6046829B2
Authority
JP
Japan
Prior art keywords
region
gate
anode
thyristor
cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4288577A
Other languages
Japanese (ja)
Other versions
JPS53127279A (en
Inventor
弥一郎 渡壁
三樹生 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP4288577A priority Critical patent/JPS6046829B2/en
Publication of JPS53127279A publication Critical patent/JPS53127279A/en
Publication of JPS6046829B2 publication Critical patent/JPS6046829B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066Gate region of field-effect devices with PN junction gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置、特に電界効果形スイッチングサ
イリスタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a field effect switching thyristor.

最近開発された電界効果形スイッチングサイリスタは、
大電流を電界で制御でき、しかも従来の通常のサイリス
タに比してスイッチング速度の速い素子として注目され
ている。
Recently developed field effect switching thyristors are
Thyristors are attracting attention as devices that can control large currents using electric fields and have faster switching speeds than conventional thyristors.

すなわち、従来の通常のサイリスタではターンオフ時間
がたかだかAl−↓−ι一小ユ3、小彎[預、田 フ
I、ソェ、ノグサイリスタでは1μs以下にするのは容
易である。第1図および第2図はいずれもこの電界効果
形スイッチングサイリスタの従来例の構造を示す断面図
で、図において、1はN−形ベース領域、2はP*彩ア
ノード領域、3はN*彩カソード領域、4はP*彩ゲー
ト領域、5はアノード電極、6はカソード電極、7はゲ
ート電極、8は絶縁膜である。
In other words, in the conventional normal thyristor, the turn-off time is at most Al-
For I, SOE, and NOG thyristors, it is easy to reduce the time to 1 μs or less. Both FIG. 1 and FIG. 2 are cross-sectional views showing the structure of a conventional example of this field effect switching thyristor. In the figures, 1 is an N-type base region, 2 is a P* color anode region, and 3 is an N* A colored cathode region, 4 a P* colored gate region, 5 an anode electrode, 6 a cathode electrode, 7 a gate electrode, and 8 an insulating film.

P*彩ゲート領域4はN−形ベース領域1内に網目状も
しくは縞状に形成され、第1図の例ではこのP″″形ゲ
ート領域4が埋め込まれた構造を有しており、ゲート電
極7はこゝには表示されないが、この装置の適当な位置
に設けられる。ゲート電極7とカソード電極6との間に
ゲート電圧を印加して、ゲート領域4とベース領域1と
で形成されているPN接合を逆バイアスしたとき、ゲー
ト領域4の周囲に出来る空乏層(図で破線で範囲を示す
)がアノード電極5とカソード電極6との間を流れるア
ノード電流を阻止し得るよ”うにゲート領域4を形成す
る。
The P*color gate region 4 is formed in a mesh or striped shape within the N-type base region 1, and in the example shown in FIG. Electrodes 7 are not shown here, but are provided at appropriate locations on the device. When a gate voltage is applied between the gate electrode 7 and the cathode electrode 6 to reverse bias the PN junction formed by the gate region 4 and the base region 1, a depletion layer is formed around the gate region 4 (Fig. The gate region 4 is formed in such a way that the area (range indicated by a broken line) can block the anode current flowing between the anode electrode 5 and the cathode electrode 6.

第3図は各種ゲート電圧におけるアノード・カソード間
電圧VAK対アノード電流IA特性を示す図で、特性曲
線aはゲート電圧が零の場合の特性で、PfN−N″′
ダイオードの順方向特性に相当す・る。
Figure 3 is a diagram showing the anode-cathode voltage VAK vs. anode current IA characteristic at various gate voltages. Characteristic curve a is the characteristic when the gate voltage is zero, and PfN-N'''
Corresponds to the forward characteristics of a diode.

ゲート電圧を順次増加してゆくと順次特性曲線B,c,
dに示すような順方向阻止状態を示す。そしてゲートに
抵抗がある場合は、アノード電圧■AKがそれぞれのブ
レークオーバ電圧V8Ob,■BOc,■BOdを越え
ると、負性抵抗特性領域を経て導通状態となる特性を有
している。このように、この電界効果形スイッチングサ
イリスタは電流阻止状態から導通状態に移行(ターンオ
ン)させるには、また、この逆方向に移行(ターンオフ
)させるには、ゲート電圧もしくはゲート抵抗を変化さ
せることによつて行うことができる。以上述べたように
、この電界効果形スイッチングサイリスタは(1)ゲー
ト電圧によつてターンオフ電圧が変化する。
As the gate voltage is gradually increased, characteristic curves B, c,
The forward blocking state as shown in d is shown. If the gate has a resistance, it has a characteristic that when the anode voltage AK exceeds the respective breakover voltages V8Ob, BOc, BOd, the gate becomes conductive through a negative resistance characteristic region. In this way, this field effect switching thyristor can be made to change from a current blocking state to a conducting state (turn on), or in the opposite direction (turn off) by changing the gate voltage or gate resistance. You can do it by leaning. As described above, in this field effect switching thyristor, (1) the turn-off voltage changes depending on the gate voltage;

他に(2)導通状態にあつてもゲートの制御能力を失わ
ない。
In addition, (2) the gate control ability is not lost even in a conductive state;

(3)従来の通常のサイリスタではゲート直列抵抗を低
下できないが、このサイリスタではゲート直列抵抗を大
幅に低下してもよく、しかもゲートが網目状もしくは縞
状に形成されているので、電気容量も小さくでき、従つ
てゲート入力時定数が小さくなる。
(3) Conventional normal thyristors cannot reduce the gate series resistance, but this thyristor can significantly reduce the gate series resistance, and since the gate is formed in a mesh or striped shape, the electric capacitance can also be reduced. can be made smaller, thus reducing the gate input time constant.

などの利点をもつている。It has advantages such as

第2図に示した構造は表面にアルミニウム、チタン、ニ
ッケル、クロムなどの金属ゲート電極を構成した表面配
線形てあるので、ゲート抵抗を十分低下させることがで
きる。
Since the structure shown in FIG. 2 has a surface wiring type in which a metal gate electrode made of aluminum, titanium, nickel, chromium, etc. is formed on the surface, the gate resistance can be sufficiently reduced.

さて、この電界効果形スイッチングサイリスタの動作機
構は、導通時はP+N−N+ダイオードの順方向特性を
示し、遮断時にはゲート、ベース、アノードで構成され
るPNPトランジスタのベース電流零の場合の特性を示
す。
Now, the operating mechanism of this field-effect switching thyristor shows the forward characteristics of a P+N-N+ diode when conducting, and when cut off, shows the characteristics when the base current of a PNP transistor consisting of a gate, base, and anode is zero. .

ところで、このサイリスタのスイッチング損失を小さく
するためには、特にターンオフ時のアノード電流に注目
する必要がある。
By the way, in order to reduce the switching loss of this thyristor, it is necessary to pay particular attention to the anode current during turn-off.

第4図はこのターンオフ時のアノード電流の変化を示す
代表的な波形で、上述のスイッチング損失を減少させる
にはアノード電流の降下期間を短くすること、および第
4図に示すようなアノード電流波形のテール期間中の電
流値を小さくする必要がある。そのためには、アノード
電流が消え易いようにターンオフゲインを大きくするこ
と、つまり、PNPトランジスタの電流増幅率αを小さ
くすることが必要である。この電流増幅率αを小さくす
るには、例えば金などのキャリア捕獲中心となる不純物
をアノード側からドープすればよい。第5図はこのよう
にして製作された電界効果形スイッチングサイリスタの
断面図で、図中破線斜線を施した部分がキャリア捕獲中
心不純物ドープ領域てある。この構造では、順方向電圧
が印加され導通の状態から、ゲートに逆電圧を印加して
ターンオフするとき、P+形アノード領域2の多数キャ
リアの正孔はN一形の基板(ベース領域)1に注入され
、この正孔とN一形ベース領域1に存在する少数キャリ
アの正孔とはP+形ゲート領域4へ引き出される。
Figure 4 shows a typical waveform showing the change in the anode current at turn-off.In order to reduce the above-mentioned switching loss, it is necessary to shorten the drop period of the anode current and to change the anode current waveform as shown in Figure 4. It is necessary to reduce the current value during the tail period. For this purpose, it is necessary to increase the turn-off gain so that the anode current disappears easily, that is, it is necessary to decrease the current amplification factor α of the PNP transistor. In order to reduce this current amplification factor α, it is sufficient to dope an impurity such as gold, which is a center of carrier capture, from the anode side. FIG. 5 is a sectional view of a field effect switching thyristor manufactured in this manner, in which the dashed hatched area is the carrier trapping center impurity doped region. In this structure, when a reverse voltage is applied to the gate to turn it off from a conductive state when a forward voltage is applied, holes of majority carriers in the P+ type anode region 2 are transferred to the N type substrate (base region) 1. The injected holes and holes of minority carriers existing in the N-type base region 1 are drawn out to the P+-type gate region 4.

これらの過剰キャリアが消失すると電流が減少しはじめ
、ゲート逆電圧が確立し、その後N一形基板(ベース領
域)1における再結合によつて消失する。この再結合の
割合は、ドープされた金などの不純物によるキャリア捕
獲中心によつて増大する。
As these excess carriers dissipate, the current begins to decrease and a gate reverse voltage is established, which is then dissipated by recombination in the N-type substrate (base region) 1. This rate of recombination is increased by carrier trapping centers due to impurities such as doped gold.

しかし、電流増幅率αを小さくするためにドープした金
などの不純物はN一形基板の比抵抗を増大させ、サイリ
スタの順方向電圧降下が増し、電力損失の増大をきたし
、素子の熱的破壊を生ずるおそれがある。この発明はこ
のような点に鑑みてなされたもので、キャリア捕獲中心
を形成する不純物を選択的にドープすることによつて、
スイッチング損失が少なく、しかも順方向電圧降下も小
さい電界効果形スイッチングサイリスタを提供すること
を目的とするものである。
However, impurities such as gold doped to reduce the current amplification factor α increase the resistivity of the N-type substrate, increasing the forward voltage drop of the thyristor, increasing power loss, and causing thermal breakdown of the device. There is a risk that this may occur. This invention was made in view of these points, and by selectively doping impurities that form carrier trapping centers,
It is an object of the present invention to provide a field effect switching thyristor with low switching loss and low forward voltage drop.

第6図はこの発明の一実施例の構造を示す断面図で、こ
の例では図示のようにN一形ベース層1のゲート領域4
の近傍に金などのキャリア捕獲中心となる不純物を選択
的にドープしてある。
FIG. 6 is a sectional view showing the structure of an embodiment of the present invention, in which the gate region 4 of the N-type base layer 1 is
The impurity, such as gold, which acts as a carrier trapping center is selectively doped near the .

この図でもこの不純物ドープ領域を配線斜線で示す。こ
のドープ領域のN一形ベース領域1内での層の厚さは少
数キャリア(この場合は正孔)の拡散長程度あればよい
。例えば、金の濃度を2×1015c!n(とすると、
少数キャリア(正孔)のライフタイムτ2は約0.01
μsであるから、拡散長LpはLp・=JDpTp(D
pは正孔の拡散係数)で計算され約4μmとなる。この
ような構造をもつ電界効果形スイッチングサイリスタを
形成するには、従来の金拡散技術による。
In this figure as well, this impurity doped region is indicated by diagonal lines. The thickness of this doped region in the N-type base region 1 may be approximately the same as the diffusion length of minority carriers (holes in this case). For example, the concentration of gold is 2×1015c! n(, then
The lifetime τ2 of minority carriers (holes) is approximately 0.01
μs, the diffusion length Lp is Lp・=JDpTp(D
p is the hole diffusion coefficient) and is approximately 4 μm. A field effect switching thyristor having such a structure can be formed using conventional gold diffusion techniques.

ゲート領域4の表面にのみ選択的に金を蒸着し、その後
、熱拡散をさせればよいが、ゲート領域表面全面に蒸着
すると熱拡散時に横方向拡散を生じ、金拡散力幼ソート
領域3にまで及び、サイリスタの順方向電圧降下の低下
を阻害することがある。従つて、金の蒸着をゲート領域
4の表面の一部にのみ選択的に行い、その上で熱拡散さ
せて、所望の不純物ドープ領域を得る。このようにして
構成した電界効果スイッチングサイリスタはゲート領域
4の周辺に不純物ドープ領域を有するので、前述の遮断
時のアノード電流の消滅が速く、従つてスイッチング損
失を小さく、例えば、500Vの素子で10kHzの動
作で1%程度あつたものを0.1%程度に100kHz
の動作で10%程度あつたものを1%程度にすることが
でき、しかもアノード・カソード間の電流通路には不純
物がドープされていないので順方向電圧降下も低く、例
えば1.2V程度に抑えることができる。
It is sufficient to selectively deposit gold only on the surface of the gate region 4 and then thermally diffuse it, but if gold is deposited on the entire surface of the gate region, lateral diffusion will occur during thermal diffusion, and the gold diffusion force will be low in the sorting region 3. This may even hinder the reduction of the forward voltage drop of the thyristor. Therefore, gold is selectively deposited only on a part of the surface of the gate region 4 and thermally diffused thereon to obtain a desired impurity-doped region. Since the field-effect switching thyristor constructed in this manner has an impurity-doped region around the gate region 4, the anode current disappears quickly during the above-mentioned cutoff, and therefore the switching loss is small. 100kHz to reduce the temperature of about 1% to about 0.1% with the operation of
With this operation, it is possible to reduce the voltage from about 10% to about 1%, and since the current path between the anode and cathode is not doped with impurities, the forward voltage drop is low, for example, about 1.2V. be able to.

以上詳述したように、この発明では電界効果スイッチン
グサイリスタのゲート領域を含み、ゲート領域からベー
ス領域内へ少なくともキャリアの−拡散長だけ伸びると
ともに、アノード領域とカソード領域との間の電流路を
閉じない範囲の領域にキャリア捕獲中心となる不純物を
拡散させたので、サイリスタのターンオフ時のアノード
電流の消滅を速くし、従つてスイッチング損失が小さく
、しかも動作時の順方向電圧降下も小さくすることがで
き、スイッチングサイリスタとしての性能が大幅に向上
できる。
As detailed above, the present invention includes a gate region of a field effect switching thyristor, which extends from the gate region into the base region by at least the -diffusion length of carriers, and closes the current path between the anode region and the cathode region. Since the impurity, which is the center of carrier trapping, is diffused in the region where the thyristor is not present, the anode current disappears quickly when the thyristor is turned off, and therefore the switching loss is small, and the forward voltage drop during operation is also small. The performance of the switching thyristor can be greatly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はいずれも電界効果形スイッチング
サイリスタの従来例の構造を示す断面図、第3図はこの
サイリスタの各種ゲート電圧におけるアノード・カソー
ド間電圧■AK対アノード電流h特性を示す図、第4図
はサイリスタのターンオフ時のアノード電流を示す波形
図、第5図は改良された従来例を示す断面図、第6図は
この発明の一実施例を示す断面図てある。 図において、1はN一形ベース領域、2はP+形アノー
ド領域、3はN+形カソード領域、4は巴形ゲート領域
である。
Figures 1 and 2 are both cross-sectional views showing the structure of a conventional field-effect switching thyristor, and Figure 3 shows the anode-cathode voltage AK vs. anode current h characteristics at various gate voltages of this thyristor. 4 is a waveform diagram showing the anode current when the thyristor is turned off, FIG. 5 is a sectional view showing an improved conventional example, and FIG. 6 is a sectional view showing an embodiment of the present invention. In the figure, 1 is an N-type base region, 2 is a P+-type anode region, 3 is an N+-type cathode region, and 4 is a tomoe-shaped gate region.

Claims (1)

【特許請求の範囲】[Claims] 1 第1の導電形を有するアノード領域と、第2の導電
形を有し上記アノード領域との間に接合を形成するベー
ス領域と、第1の導電形を有し上記ベース領域の内部に
埋め込まれもしくは表面に所定パターンに形成されたゲ
ート領域と、高不純物濃度の第2の導電形を有し上記ベ
ース領域の表面に上記ゲート領域自体には妨げられるこ
となく上記アノード領域との間に電流を通じ得るように
設けられたカソード領域とを有するものにおいて、上記
ゲート領域を含み上記ゲート領域から上記ベース領域内
へ少なくともキャリアの拡散長だけ伸びるとともに上記
アノード領域とカソード領域との間の電流路を閉じない
範囲の領域にキャリアの捕獲中心となる不純物を拡散さ
せたことを特徴とする半導体装置。
1. An anode region having a first conductivity type, a base region having a second conductivity type forming a junction with the anode region, and a base region having a first conductivity type embedded within the base region. A current flows between the gate region formed in a predetermined pattern on the surface thereof and the anode region having a second conductivity type with a high impurity concentration on the surface of the base region without being hindered by the gate region itself. and a cathode region provided so as to be able to pass through the anode region, the cathode region including the gate region and extending from the gate region into the base region by at least a carrier diffusion length, and providing a current path between the anode region and the cathode region. A semiconductor device characterized in that impurities that serve as carrier capture centers are diffused into an unclosed region.
JP4288577A 1977-04-13 1977-04-13 semiconductor equipment Expired JPS6046829B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4288577A JPS6046829B2 (en) 1977-04-13 1977-04-13 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4288577A JPS6046829B2 (en) 1977-04-13 1977-04-13 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS53127279A JPS53127279A (en) 1978-11-07
JPS6046829B2 true JPS6046829B2 (en) 1985-10-18

Family

ID=12648483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4288577A Expired JPS6046829B2 (en) 1977-04-13 1977-04-13 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6046829B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4848021B2 (en) * 2009-01-14 2011-12-28 イオンモール株式会社 Fire alarm and anti-tamper device for fire alarm

Also Published As

Publication number Publication date
JPS53127279A (en) 1978-11-07

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