JPS6046667B2 - logic tester - Google Patents

Description

[Detailed description of the invention] The present invention relates to logic testers.

Conventional logic testers used to check semiconductor integrated logic circuit element parts and functionalized logic circuit blocks on printed circuit boards usually have a judgment circuit that judges the state logic value for each cycle during the test period. The state logic waveform (logic signal under test) 1 output from the unit under test is driven by a single clock, that is, as shown in Figure 1.
is determined by the timing of a single clock 2 generated by logic and a tester.

As shown in Figure 2, when a waveform distortion 4 occurs in the state logic waveform output from the test section, in order to determine this state logic waveform 1 as abnormal, set the clock 2 to the position of the waveform distortion 4. must be placed. Therefore, the abnormal waveform is determined by generating the clock 2 by shifting the clock 2 by Δ every cycle. As described above, with conventional logic testers, abnormalities in the state logic waveform under test may not be determined in one cycle, so it is necessary to test over many cycles while changing the clock timing, which is a time-consuming process. It takes.

Furthermore, it may not be possible to determine intermittent abnormalities. SUMMARY OF THE INVENTION An object of the present invention is to provide a logic tester that solves the problems of the conventional art as described above. The logic tester according to the present invention is characterized by a means for continuously comparing the logic level of the logic signal under test with a logic level that is repeated multiple times during one cycle of the signal, and for storing the comparison results by this means. and the means to do so. In one embodiment of the present invention, the logic signal under test is judged to match the expected logic level signal using an exclusive OR circuit, and the judgment result is continuously evaluated during one cycle period of the logic signal under test. Sample multiple times and write to memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a configuration diagram of a logic tester which is an embodiment of the present invention.

The logic tester 11 has a check circuit 13, a drive circuit 14, and a tester control circuit 15, and is connected to the logic circuit under test 12 through an output value bus 22 and an input bus 21. The logic circuit under test 12 has an output value bus 22 and an input bus 2.
Connected with 1. When the logic circuit under test 12 receives a specified input pattern from the input bus 21, it outputs the output state value at that time to the output value bus 22 and inputs it to the logic tester 11. The check circuit 13 connects the tester control circuit 15 with a threshold control line 16, an expected value pattern line 17, a judgment clock gate line 18, and a fail bus line 19.
connected to. The drive circuit 14 is connected to the tester control circuit 15 via an input pattern line 20. FIG. 4 is a detailed diagram of the check circuit 13. The output bus 22 of the logic circuit under test 12 is connected to one input of the comparator circuit 31, and the output bus 22 of the logic circuit under test 12 is connected to the other input of the comparison circuit 31. is connected to the threshold signal line. The judgment circuit 32 (exclusive OR circuit) has one input connected to the output of the comparison circuit 31 and the other input connected to the expected value pattern line 17 from the tester control circuit 15, and compares and judges the power of both. do. Furthermore, the output of the determination circuit 32 is input as data to a fail memory 33 consisting of a shift register. The multiple sampling clock gate 34 receives the output of the clock generator 35 and the judgment clock from the tester control circuit 15.
It is connected to the stop line 38 of the counter 37. This multiple sampling●Failure of clock gate 34●
It is used as a shift clock for the memory 33 and serves to sequentially write judgment information from the judgment circuit 32 to the fail memory. Further, the clock counter 37 counts the output of the gate 34, and when the count exceeds a preset counter value according to the capacity of the fail memory 33, the stop line 38 is activated and the multiple sampling clock gate 34 is activated. Stop. Next, the operation will be explained.

A specific input pattern is applied from the tester control circuit 15 to the input of the logic circuit under test 12 via the drive circuit 14.

According to this input pattern, the logic circuit under test 12 outputs a uniquely determined output onto the output bus. Further, the threshold generation circuit 36 outputs a threshold signal according to a threshold instruction given from the tester control circuit 15 through the threshold control line 16. Comparison circuit 31 is output bus 2
2, the logic signal under test and the threshold signal are compared in level, and the logic signal under test is thereby shaped and input to the determination circuit 32. The determination circuit 32 compares the logic level of the input logic signal under test and the expected value pattern provided from the tester control circuit 15 through the expected value pattern line 17. On the other hand, a little later than the sending of the input pattern, the tester control circuit 15 opens the multiple sampling ● clock ● gate 34 on the judgment clock gate line 18 .

Therefore, the clock signal output from the clock generator 35 is applied to the fail memory 33 through the gate 34 as a sampling clock. Thus, the output of the determination circuit 32 is sequentially written into the fail memory 33 at the timing of the sampling clock.

When counter 37 counts over, stop line 3
8, the multiple sampling clock gate 34 is closed, the supply of the sampling clock is stopped, and the sampling of the decision circuit 32 is stopped. In order to clarify the above operation, an example of a time chart of signals of each part is shown in FIG.

In the figure, there is a temporary waveform drop 4 in the logic signal under test, but this waveform drop 4 is sampled as the illustrated fail signal at the third sampling clock and written into the fail memory 33. In addition, R on counter 37
The case where 5J is set in advance is shown. In the above explanation, the logic signal under test with a temporary drop in waveform has been described, but the present invention is also applicable to a case with a waveform jump.

Further, in the above embodiment, an example was shown in which sampling is performed multiple times in one cycle, but the present invention is not limited to this, and the sampling clock shown in FIG. , it may be changed to one continuous long clock signal. As described above in detail, the logic tester according to the present invention can quickly check even intermittent abnormalities by sampling the judgment result of the logic signal under test at least continuously during one cycle.

[Brief explanation of the drawing]

Figures 1 and 2 are time charts for explaining a conventional logic tester, Figure 3 is a block diagram of a logic tester that is an embodiment of the present invention, and Figure 4 is a check mark in Figure 3. Circuit diagram showing an example of a specific circuit of the circuit, No. 5
The figure is a time chart for explaining the operation of the same embodiment. 12...Logic circuit under test, 13...Check circuit, 14...Drive circuit, 15...
・Tester control circuit, 31... Comparison circuit, 32
...Judgment circuit. 33...Fail●Memory, 34...Multiple sampling●Clock gate, 35...Clock generator, 37...
·counter.

Claims (1)

[Claims] 1 A control circuit and a specific pattern output from the control circuit are input to the logic circuit under test, and the level of the output signal output from the logic circuit under test is compared with a preset threshold signal. a determination circuit that continuously performs a match comparison between an output signal of the comparison circuit and an expected value pattern output from the control circuit during one cycle of the output signal of the logic circuit under test; A logic tester characterized by comprising a memory circuit for storing judgment results of times.