JPS6046047A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6046047A
JPS6046047A JP58154303A JP15430383A JPS6046047A JP S6046047 A JPS6046047 A JP S6046047A JP 58154303 A JP58154303 A JP 58154303A JP 15430383 A JP15430383 A JP 15430383A JP S6046047 A JPS6046047 A JP S6046047A
Authority
JP
Japan
Prior art keywords
wafer
metal film
semiconductor
along
scribe line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58154303A
Other languages
Japanese (ja)
Inventor
Miyuki Aoki
青木 覧之
Kenichi Matsui
健一 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58154303A priority Critical patent/JPS6046047A/en
Publication of JPS6046047A publication Critical patent/JPS6046047A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To enhance the working efficiency of manufacturing a semiconductor device by heating a metal film formed on the surface of a semiconductor substrate along a dicing line of a wafer to generate mechanical distortion on the surface of the substrate, quenching the wafer, and dividing into chips, thereby reducing improper dicing. CONSTITUTION:The surface of a semiconductor substrate 12 is etched substantially along the center line of a scribing line 14 between semiconductor elements 11, thereby forming a groove 15. Metal which mainly contains aluminum is covered thereon, and linear metal film 16 of narrow line width and metal films 161, 162 for electrodes are formed. Then, a large current is flowed from the films 161, 162 to the film 16 to sufficiently heat them, and when a wafer 10 is introduced into water to quench it, the wafer 10 is divided along the scribing line dur to mechanical distortion occurred in the substrate 12, thereby readily dicing the chip of long rectangular shape.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置の製造方法に関するもので、特に
ウェハをチップ状に切る段階の半導体装置の製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device at the stage of cutting a wafer into chips.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

半導体装置の一連の製造工程において、所定の素子が形
成されウニI・プロセスが終了したウェーは、ダイソー
トテスト(ウェー・に形成された多数の半導体素子の良
否をウェー・状態で試験するもの)が施された後、半導
体チラノになるように素子ごとに分割される。従来との
ようなウェハを半導体チップに分割する方法としては次
のようなものがあった。
In a series of semiconductor device manufacturing processes, waes on which predetermined elements have been formed and the uni process has been completed are subjected to a die sort test (testing the quality of a large number of semiconductor elements formed on a wafer in the wafer state). After that, it is divided into individual elements to form semiconductor tyrannos. Conventional methods for dividing a wafer into semiconductor chips include the following.

(1) ダイヤモンド?インドスクライビング法ウェハ
のダイシングライン(スクライブライン)上の一部にダ
イヤモンドのエツジにょシ切り込みを入れスクライブラ
インに沿ってウェハを割シ、チップ状にする。この方法
では、ウェー・の結晶方位との関係で効率良くダイシン
グすることが難しく、切シしろとしては約30μm程度
を要し、スクライブマシンとウエハトノフれを見込むと
、通常少なくとも100μmの幅のスクライブラインが
必要である。その上、ウェハの切シくず(シリコンくず
)が発生しやすい欠点があシ、且つ作条効率が悪く、長
い製造時間を要するという欠点がある。
(1) Diamond? Indian scribing method A diamond edge cut is made on a portion of the wafer's dicing line (scribe line), and the wafer is divided into chips along the scribe line. With this method, it is difficult to dice efficiently due to the crystal orientation of the wafer, and a cutting margin of about 30 μm is required, and when considering the wafer torn off with the scribing machine, the scribe line is usually at least 100 μm wide. is necessary. In addition, it has the drawback that wafer cutting chips (silicon chips) are likely to be generated, and the production efficiency is poor and a long manufacturing time is required.

(2) レーザースクライビング法 ウェハのダイシングラインに沿ってレーザ光を走査しス
クライブラインに切シ溝を形成した後、この切シ溝に沿
ってクエ/Sを割る。この方法では、レーザー光によっ
て蒸発したシリコンが再び固ってウェハ上にこびシつく
現象や、レーザー光によ多発生した熱によってウェー・
内にマイクロクラックが発生し半導体チップの特性を劣
化させる問題や、装置が大がかシで高価である等の欠点
がある。
(2) Laser scribing method A laser beam is scanned along the dicing line of the wafer to form a cut groove on the scribe line, and then the Que/S is divided along the cut groove. In this method, the silicon vaporized by the laser beam hardens again and sticks to the wafer, and the heat generated by the laser beam causes the wafer to dry.
There are disadvantages such as the problem that microcracks occur inside the semiconductor chip and deteriorate the characteristics of the semiconductor chip, and the equipment is bulky and expensive.

(3) グイシングツ−法 ダイシングソーによりてウェハをダイシングラインに沿
い切る方法である。この方法はウェー・の結晶方位に依
存せず、残留歪が少ない等の長所があるが、約30μm
程度の切シしろが必要でダイシングソーとの切断時のぶ
れを見込むとスクライブラインは通常100μm以上の
幅に設定する必要がある。また、シリコンくずが発生し
やすく、シかも切断の際に水を使用するため、水とシリ
コンぐずとがいわば泥状に混ざシブバイス表面が汚れや
すい等の欠点がある。
(3) Guising Two Method This is a method in which the wafer is cut along dicing lines using a dicing saw. This method does not depend on the crystal orientation of the wafer, and has the advantage of having little residual strain.
A certain amount of cutting allowance is required, and the scribe line usually needs to be set to a width of 100 μm or more to account for blurring when cutting with a dicing saw. In addition, silicone waste is likely to be generated, and since water is used when cutting the shrivel, the water and silicone waste mix in a mud-like state, which tends to stain the surface of the shive vise.

このように、従来のウニ・・の分割方法にはそ 1れぞ
れ欠点があシ、またいずれの場合もCCD 17ニアイ
メーゾセンサのように例えば1.1門X 37.5mm
とか1.1 mX 72.Ottanというような長辺
状の形状のチップのダイシングでは、チップを1つ1つ
分割するのが困難でチップの収率が低下するという問題
があった。
In this way, each of the conventional methods of dividing sea urchins has its own drawbacks, and in each case, the size of the sea urchin is 1.1 mm x 37.5 mm, such as the CCD 17 near-eye meso sensor.
Or 1.1 mX 72. When dicing chips having a long side shape such as Ottan, there is a problem in that it is difficult to separate the chips one by one and the yield of chips decreases.

〔発明の目的〕[Purpose of the invention]

本発明は上記のような点に鑑みなされたもので、ダイシ
ング不良が低減され作業効率が高く、長辺状のチップも
容易にダイシングすることのできる簡易な半導体装置の
製造方法を提供しようとするものである。
The present invention has been made in view of the above points, and it is an object of the present invention to provide a simple semiconductor device manufacturing method that reduces dicing defects, has high work efficiency, and can easily dice long-sided chips. It is something.

〔発明の概要〕[Summary of the invention]

すなわち本発明に係る半導体装置の1!!遣方法では、
ウェハのダイシングラインに沿って半導体基板表面をエ
ツチングによシ露出させた後、このダイシングライン上
に適宜極く薄い絶縁膜を介して細い線幅で金属膜を被着
させる。そして、上記スクライブラインに沿って形成し
た幅の細い金属膜の全てに電流が流れるように通電し、
金属膜を発熱させ金属膜下の半導体基板表面に機械的歪
を発生させた後、ウェー・を急冷させウェハをダイシン
グラインに沿って割シチッグに分割する方法である。
That is, 1! of the semiconductor device according to the present invention! ! In the sending method,
After exposing the surface of the semiconductor substrate by etching along the dicing line of the wafer, a metal film with a narrow line width is deposited on the dicing line with an appropriately extremely thin insulating film interposed therebetween. Then, energize so that the current flows through all of the narrow metal films formed along the scribe line,
This method generates heat in the metal film to generate mechanical strain on the surface of the semiconductor substrate underneath the metal film, then rapidly cools the wafer and divides the wafer into pieces along dicing lines.

なお、ウニノ1のダイシングラインには通常のウェー・
ゾロセスにおいて、絶縁膜等の上部膜が被着しないよう
にエツチングがくシ返して行なわれているが、これらの
エツチングの際の適当な時期成いはウェー・プロセスの
最後の段階でダイシングラインの幅の中央部にエツチン
グによシ細い溝部を形成し、この溝部上に上記金属膜を
被着するようにすればさらに良い。
In addition, the dicing line of UNINO 1 is equipped with a normal wafer.
In Zorocess, etching is repeated to prevent upper films such as insulating films from adhering, but the appropriate timing for these etchings is determined by adjusting the width of the dicing line at the final stage of the wafer process. It is even better if a narrow groove is formed in the center of the groove by etching, and the metal film is deposited on this groove.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の一実施例につき説明する
An embodiment of the present invention will be described below with reference to the drawings.

第1図は、CCDCDリニアイメージセンサき長辺形の
チップ形状を有する半導体ウニノ・の平面図であシ、半
導体ウェー10には縦横に並んで半導体チップとなる半
導体素子11が形成され、この半導体素子11には図示
しないが所定の不純物領域が形成され、半導体基板の上
面には上部膜として例えばシリコン酸化膜、ポリシリコ
ン、アルミニウム配線層等が積層して形成され、その最
上部にPSG (!lン硅酸ガラス)膜尋の保護膜が形
成されている。
FIG. 1 is a plan view of a semiconductor wafer 10 having a rectangular chip shape and having a CCDCD linear image sensor.Semiconductor elements 11 forming semiconductor chips are formed in rows and columns on a semiconductor wafer 10. A predetermined impurity region (not shown) is formed in the element 11, and an upper film such as a silicon oxide film, polysilicon, aluminum wiring layer, etc. is stacked on the upper surface of the semiconductor substrate, and PSG (!) is formed on the top of the layer. A thick protective film (silicate glass) is formed.

またこのようなウェハL!において半導体素子11間は
通常スクライプライン或いはダイシングラインと呼ばれ
、半導体板12表面が露出した領域となっている。すな
わち、上記各種の上部膜の形成工程において、スクライ
ブライン14上に被着したものは除去するように上部膜
のパターニングの際にエツチングされる。
Another wafer L like this! The area between the semiconductor elements 11 is usually called a scribe line or a dicing line, and is an area where the surface of the semiconductor plate 12 is exposed. That is, in the process of forming the various upper films described above, the material deposited on the scribe line 14 is etched during patterning of the upper film so as to remove it.

このようなウェー・10を通常の手法によ層形成した後
、半導体ウニ/−10の一部を拡大して示す82図およ
び第2図のA −A’断面を示す第3図に示すように、
スクライブライン14の略中心線に沿って半導体基板1
2の表面部分を通常の写真蝕刻法によシエッチングし、
溝部15を形成する。なお、第3図の13は上部膜を示
したものである。
After layering such a wafer 10 by a conventional method, it is formed into a layer as shown in FIG. To,
The semiconductor substrate 1 is placed along approximately the center line of the scribe line 14.
The surface part of 2 is etched by ordinary photoetching method,
A groove portion 15 is formed. Note that 13 in FIG. 3 indicates the upper film.

続いて、このウェハ10上にアルミニウムを主成分とす
る金属を被着しパターニングすることによシ、狭い線幅
を有する線状金属膜16を形成する。この際、ウェー・
周辺部の半導体素子11の形成されない部位には第1図
に示すように電極用金属膜161.16□を広い領域に
渡って形成する。
Subsequently, a metal whose main component is aluminum is deposited on this wafer 10 and patterned to form a linear metal film 16 having a narrow line width. At this time, we
As shown in FIG. 1, an electrode metal film 161.16□ is formed over a wide area in the peripheral area where the semiconductor element 11 is not formed.

次いで、ウェー・10に形成された半導体素子1ノのダ
イソートテストを行い、上記細い線状金属膜16部分を
挾むようにウェハL1の両端の電極用金属膜161,1
62から線状金属膜16に大電流を流す。この際に、電
流を上記線状金属膜16に流すことにより、この線状金
属膜16が発熱する。そして、充分に発熱させた直後に
ウェー・10を例えば水中に入れ急冷させる。ここで、
ウェー・10は半導体基板1ノ内に発生した機械的歪に
よシスクライブラインに沿って割れる。
Next, a die sort test is performed on the semiconductor element 1 formed on the wafer L1, and electrode metal films 161, 1 are formed on both ends of the wafer L1 so as to sandwich the thin linear metal film 16.
A large current is passed through the linear metal film 16 from 62 . At this time, by passing a current through the linear metal film 16, the linear metal film 16 generates heat. Immediately after generating sufficient heat, the wafer 10 is placed in water, for example, and rapidly cooled. here,
The wafer 10 cracks along the silicon scribe line due to mechanical strain generated within the semiconductor substrate 1.

ここで、従来は特に半導体チップの長辺に沿りて割るこ
とが困難であったがこの場合はチップの長辺方向に沿っ
てウニノー1oに切れ目が入シ、ウェハ10に軽く外力
を加えることによシ簡単にウェハ10を半導体チップに
することができる。
Here, in the past, it was difficult to break the semiconductor chip especially along the long side, but in this case, a cut is made in the wafer 10 along the long side of the chip, and a light external force is applied to the wafer 10. The wafer 10 can be easily made into semiconductor chips.

以上のような方法によれば、1枚のウェハのスクライブ
ライン全体を同時に発熱させ同時に急冷させることが可
能であるため、ウェハを一度に多数の半導体チップに分
割させることができる。
According to the method described above, the entire scribe line of one wafer can be simultaneously heated and rapidly cooled, so that the wafer can be divided into a large number of semiconductor chips at once.

また、本方法では従来ダイシングが困M1tであった長
辺状の半導体チップには特に有効なもので、チップの収
率を向上させることができる。
Furthermore, this method is particularly effective for long-sided semiconductor chips, which have traditionally been difficult to dice, and can improve the yield of chips.

さらにまた、スクライブラインのね幅を従来の約100
〜150μmから50μm8度にまで狭くすることがで
きるためウェハの有効な活用を図ることができ、この点
からもチップ収率を向上させることができる。
Furthermore, the width of the scribe line has been reduced to about 100% compared to the conventional one.
Since the width can be narrowed from ~150 μm to 50 μm and 8 degrees, the wafer can be used effectively, and the chip yield can also be improved from this point of view.

尚、本実施例では、スクライブライン14に沿って溝部
15を形成する場合につき述べたが、半導体基板12が
薄いものでは特に溝部15を形成する必要はない。また
、溝部15は、半導体素子10の各部を形成するための
ウェハプロセス中に形成しても良く、同様に線状金属膜
16や電極用金属膜16□ 、162もウェー・プロセ
ス中の適当な時期に形成すれば良いものである。
In this embodiment, a case has been described in which the groove portion 15 is formed along the scribe line 14, but if the semiconductor substrate 12 is thin, it is not necessary to form the groove portion 15. Further, the groove portion 15 may be formed during the wafer process for forming each part of the semiconductor element 10, and similarly, the linear metal film 16 and the electrode metal films 16□, 162 may also be formed during the wafer process. It is good if it is formed at the right time.

また、所定の半導体ウェー・のスクライブラインに沿っ
てエツチングを行い、半導体基板面を露出させた後、酸
化処理等によ電極く薄い絶縁膜を形成し、上記スクライ
ブラインの極く薄い絶縁膜上に線状金属膜を形成して、
以下この線状金属膜16への通電とウニ・・の急冷によ
ってスクライブラインに沿ってウニノ〜を割るようにし
てもよい。
In addition, after etching is performed along the scribe line of a predetermined semiconductor wafer to expose the semiconductor substrate surface, a very thin insulating film is formed by oxidation treatment, etc., and then the very thin insulating film on the scribe line is By forming a linear metal film on
Thereafter, the sea urchins may be broken along the scribe line by applying current to the linear metal film 16 and rapidly cooling the sea urchins.

さらにまた、電極用金属MI6X r16xの形状も第
1図に示すものに限らず、例えば半導体素子11の配列
した部位に沿うように形成してもよいし、例えばウェー
・10の中央部の金属膜163を一方の電極とし、ウェ
ー・10の周辺部の電極用金属膜161 e16zt他
方ノ電極として電流を流すように、適宜電極用金域膜の
形成部位および形状を変更してもよい。
Furthermore, the shape of the electrode metal MI6X r16x is not limited to that shown in FIG. The formation location and shape of the electrode metal film 163 may be changed as appropriate so that current is passed through the electrode metal film 161 e16zt on the periphery of the wafer 10 as one electrode and the electrode metal film 161 e16zt on the periphery of the wafer 10 as the other electrode.

また、上記線状金属膜16および電極用金属膜161,
162の素材としては、アルミニウム系金属の他、モリ
ブデン、タンタル、タングステン、チタン等の高融点金
属を主成分とするものが使用可能でちる。
Moreover, the linear metal film 16 and the electrode metal film 161,
As the material for 162, in addition to aluminum-based metals, materials whose main components are high-melting point metals such as molybdenum, tantalum, tungsten, and titanium can be used.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によればダイシング不良が低減さ
れ作業効率が高く、長辺状のチップも容易にダイシング
することのできる簡易な半導体装置の製造方法を提供す
ることができる◎
As described above, according to the present invention, it is possible to provide a simple semiconductor device manufacturing method that reduces dicing defects, has high work efficiency, and can easily dice long-sided chips.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による半導体装置の製造方法における半
導体ウェー・の一過程を示す図、第2N断面を示す断面
図でおる。 10・・・半導体ウェーへ、11・・・半導体素子、1
2・・・半導体基板、13・・・上部膜、14・・・ス
クライブライン、15・・・溝部、16・・・線状金属
膜、161 、J62・・・電極用金属膜。
FIG. 1 is a diagram showing one process of the semiconductor wafer in the method for manufacturing a semiconductor device according to the present invention, and is a sectional view showing the 2N cross section. 10... To semiconductor wafer, 11... Semiconductor element, 1
2... Semiconductor substrate, 13... Upper film, 14... Scribe line, 15... Groove, 16... Linear metal film, 161, J62... Metal film for electrode.

Claims (1)

【特許請求の範囲】 (リ 半導体ウェハのスクライプラインに沿って工、チ
ングを行い半導体基板面を露出させる工程と、上記スク
ライプラインに沿った半導体基板の露出面上に適宜極く
薄い絶縁膜を介して金属膜を被着させる工程と、この金
属膜に通電し上記スクライブラインに沿った金属膜を発
熱させる工程と、この金属膜の発熱後レエハの急冷処理
を行いウェハをスクライブラインに沿って割る工程とを
具備することを特徴とする半導体装置の製造方法。 (2)上記エツチングによシ半導体基板面を露出させる
工程において、上記金属膜の形成予定部属下をエツチン
グしてスクライブラインに沿った溝部を形成し、この半
導体基板面の露出した溝部上に上記金属膜を被着するこ
とを特徴とする特許請求の範囲第1項記載の半導体装置
の製造方法。 (3)上記金属膜の素材としてアルミニウムを主成分と
する金属を使用することを特徴とする特許請求の範囲第
1項または第2項記載の半導体装置の製造方法。 (4)上記金属膜の素材として高融点金属を主成分とす
る金属を使用することを特徴とする特許請求の範囲第1
項または第2項記載の半導体装置の製造方法。
[Scope of Claims] (Li) A step of etching and etching the semiconductor wafer along the scribe line to expose the semiconductor substrate surface, and forming an extremely thin insulating film as appropriate on the exposed surface of the semiconductor substrate along the scribe line. a step of depositing a metal film through the wafer, a step of applying current to this metal film to generate heat in the metal film along the scribe line, and a process of rapidly cooling the wafer after the metal film generates heat, and then moving the wafer along the scribe line. (2) In the step of exposing the surface of the semiconductor substrate by etching, etching is performed under the area where the metal film is to be formed along the scribe line. A method for manufacturing a semiconductor device according to claim 1, characterized in that the metal film is deposited on the exposed groove on the surface of the semiconductor substrate. A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that a metal whose main component is aluminum is used as the material. (4) A high melting point metal is used as the material of the metal film. Claim 1 characterized in that a metal is used as a component.
A method for manufacturing a semiconductor device according to item 1 or 2.
JP58154303A 1983-08-24 1983-08-24 Manufacture of semiconductor device Pending JPS6046047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58154303A JPS6046047A (en) 1983-08-24 1983-08-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58154303A JPS6046047A (en) 1983-08-24 1983-08-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6046047A true JPS6046047A (en) 1985-03-12

Family

ID=15581173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58154303A Pending JPS6046047A (en) 1983-08-24 1983-08-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6046047A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04238816A (en) * 1990-04-16 1992-08-26 Inco Ltd Preparation of copper arsenate
JPH0888203A (en) * 1995-08-21 1996-04-02 Seiko Epson Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04238816A (en) * 1990-04-16 1992-08-26 Inco Ltd Preparation of copper arsenate
JPH0888203A (en) * 1995-08-21 1996-04-02 Seiko Epson Corp Semiconductor device

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