JPS6045841A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain quickly an arithmetic result and to shorten the arithmetic processing time by providing a deciding circuit for possibility of change of main exponent part and a deciding circuit for bit number of exponent part to an arithmetic device using a real number value displaying method based on the division of double exponent. CONSTITUTION:A deciding circuit 335 for possibility of change of main exponent part decides whether a given exponent part has possibility to be change up to the number of bits by normalization. While a deciding circuit 336 for bit number of exponent part decides the number of bits needed to the exponent part. When an arithmetic result is normalized, both the exponent and mantissa parts of the arithmetic result obtained before normalization are first set to registers 300 and 305 and reach the circuits 335 and 336 via signal lines 332 and 333 respectively. Then the number of bits necessary for display of the exponent part is decided by the circuits 335 and 336 as soon as the above-mentioned normalization. At the same time, whether the number of bits are changed by the normalization is decided. When it is decided that the changing possibility is small from the result of decision, the arithmetic result is set to a register 385. In such a way, the arithmetic result is obtained quickly and the arithmetic processing time can be shortened.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an arithmetic device, and more specifically, to an arithmetic device that uses a real value representation method based on double exponential division, and which performs normalization after the arithmetic operation. The present invention relates to a device that quickly responds with calculation results by starting to generate a button in the real numerical representation method before the calculation is completed.

[Background of the invention]

In the prior art, real value representation methods based on double exponential division are known.

Information Processing Society of Japan Transactions Vol. 22, No. 6, ``Data length independent real number representation method based on double exponential partitioning'' is a real number representation method for data processing devices based on the binary system, that is, a real number representation method based on double exponential partitioning. A numerical expression method is proposed. This representation method has the following advantages: the format does not depend on the length of the data, the precision conversion operation is easy, the range of numbers that can be represented is sufficiently wide, and blurring virtually never occurs.

[Data Length Independent Real Number Representation Method Based on Double Exponential Split ■] in Information Processing Society of Japan Transactions Volume 24, No. 2 improves the above real number representation method.

With reference to FIG. 1, an improved real value representation method based on double exponential division will be described. In the following, to avoid misunderstanding, 2'' will be expressed as e x p 2(n).

The configuration of the real numerical representation method is shown in Figure 1. The representation method consists of a sign part 11, an exponent part 12, and a mantissa part 13. In addition to the exponent part 12, a main exponent part 121 and a sub-exponent part 122
It consists of The code section 11 has a fixed length of 1 bit, but the other bits have variable lengths.

Now, let X be the number we want to represent. This is x=exp
2 (e)xf ・・・・・・・・・・・・・・・(1
), and is expressed by two numbers, an exponent e and a mantissa f.

However, e is an integer, and in order to uniquely represent the value, 1≦f<2 or -2≦f<-1...
・Set as (2).

First, if the mantissa f is negative, "1" is set as the sign part 11, and otherwise, "0" is set as the sign part 11.

Next, due to the constraints of equation (2), the binary representation of the part of the mantissa f minus the sign is f=l・f, f2...f,...
・・・・・・・・・・・・・・・(3). At this time r
f1f2...fj..." as the mantissa part 13
A bit of a bang.

In addition, when the exponent e is expressed as a binary digit (m≧0, but the sign only holds when e = Q or e-1), the expression of the integer e is as follows x) O, When e≧0, 1...1oevQ-1...e2e1x
)0. e(When O, x(0,, e(When O, 1...10el, l-1..."e2e
l Here, "e, ll-1...e2 e, J is the exponent e expressed in binary m digits, with the most significant digit removed. Also, the overline "" “1” and “0” for each digit
” represents the inversion operation. Also, the upper digit "1..."
・1" and "0...0" are a sequence of m+1 digits of "1" or "0" indicating that the exponent e is represented by exactly m binary digits. After these "1" or "0", a delimiter "0" or "1" is placed. At this time, "1...1" or "
The string of ``0...0'' and the delimiter ``0'' or ``1'' are the bit bumps of the main exponent part 121. Further, the remaining [e, Il-■...e2elJ or re ml-1...e2e7J is used as the bit bang of the sub-exponent part 122.

This concludes the explanation of the real number representation method based on double exponential division.

Next, with reference to FIG. 2, an explanation will be given of the calculation procedure using the real number representation method based on double exponential division.

As an example, the multiplication procedure is shown in FIG.

When an operand is given, it is first separated into an exponent part and a mantissa part 21. As mentioned above, the exponent part has a variable length, so the length of the exponent part is determined based on the focus pattern of the main exponent part, and the operand is separated into its exponent part and the mantissa part.

Below, the addition 22 of the exponent parts of the operands, the multiplication 23 of the mantissa parts, and the normalization of the mantissa part 24 to satisfy the constraint of equation (2) are the same as the multiplication procedure using the normal floating point representation method. be.

Finally, in multiplication using a real-valued representation based on double exponential division, the exponent and mantissa parts of the result are combined 25. To do this, first select a focus pattern for the main exponent part that is suitable for the exponent part, combine it with the sub-exponent part, and finally decide the length of the mantissa part so that the overall result is a fixed length.
Combine with exponent. This is the result.

Regarding other four arithmetic operations, separation of exponent part and mantissa part21
The operation of the connection 25 is similar.

This concludes the explanation of the calculation procedure using the real number representation method based on double exponential division.

As mentioned above, in an arithmetic unit that uses a real number representation method based on double exponential division, compared to an operation that uses a normal floating point representation method, there is an unnecessary need to separate and combine the exponent part and the mantissa part. It takes time.

[Purpose of the invention]

An object of the present invention is to add some devices to an arithmetic device that uses a real-value representation method based on double exponential division, so that the arithmetic device can perform post-operation normalization and bang generation using the above-mentioned representation method. The object of the present invention is to quickly respond to a bang using the above expression method as a calculation result when parallelization is performed and there is no possibility that even the main exponent part in the above expression method will be changed during post-operation normalization.

[Summary of the invention]

In an arithmetic unit that uses a real number representation method based on double exponential division, in addition to the arithmetic processing using the normal floating point representation method, complex processing is required to separate and combine the exponent and mantissa parts before and after the calculation. do. On the other hand, to combine the exponent part and the mantissa part, first it is determined how many bits are required to express the exponent part, and then the main exponent part is generated, and the sub-exponent part and the mantissa part are combined.

So-called post-operation normalization, which is performed at the end of a normal operation, generally changes the value of the exponent part, but it is relatively rare to change the number of bits in the exponent part. Particularly in normalized multiplication and division, the value of the exponent part changes by one at most, so it can be said that the number of bits changes very rarely.

In view of this phenomenon, the present invention parallelizes the post-operation normalization and the determination of the number of bits required to express the exponent, and also measures whether the post-operation normalization may change the number of bits in the exponent. Add a device to determine whether or not. If there is no possibility that the number of bats in the exponent part will change, immediately after normalization after calculation, the main exponent part is generated and the sub-exponent part and the mantissa part are combined. Only when there is a possibility that the number of bits in the exponent part may change, the focus number of the exponent part is determined again after normalization after calculation. As a result, calculation results can be obtained faster than conventional methods in many cases.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 3 shows the configuration of the latter half of the arithmetic device, that is, the part that performs post-arithmetic normalization. FIG. 4 shows a timing diagram of the main parts of the embodiment.

In the timing diagram, for convenience of explanation, the reference time is set as to. Furthermore, considering the unit time/interval, for a natural number n, the time n units of time after the reference time to is determined as to.

Although this embodiment shows an arithmetic device that performs only multiplication, it is easy to see that it can be extended to other arbitrary operations, such as addition, subtraction, division, etc. Furthermore, the length of the numerical data to be handled is not particularly determined. It is possible to handle arbitrary fixed length data. On the other hand, the operands for the arithmetic unit may be expressed in either real number representation based on double exponential division or normal floating point representation, but at least they must be normalized before performing the operation. shall be.

Assume that the output of the calculation result is expressed using a real number representation method based on double exponential division.

First, an overview of the configuration of the arithmetic device of the embodiment will be explained with reference to FIG. In FIG. 3, only the latter half of the arithmetic unit, that is, the part that performs post-arithmetic normalization and subsequent operations, is shown. Other components within the arithmetic unit, ie, parts that separate the exponent and mantissa parts, add the exponent parts, and multiply the mantissa parts will not be discussed here.

Register 300 and register 305 are used to store the exponent part and mantissa part, respectively, before normalization. Register 320 and register 325 are used to store the exponent part and mantissa part after normalization, respectively. Register 350, register 355, and register 356 are used to store the absolute value part of the exponent part, the absolute value part of the mantissa part, and the sign part of the mantissa part, respectively, for standby purposes. The register 385 is used to store the final calculation result based on the real value representation method based on double exponential division.

The circuits 310 and 315 each add 1 to the exponent part and shift the mantissa part to the right by 1 point for normalization. For a given exponent part, circuit 336 determines how many points are required to represent the exponent part. Circuit 335 determines whether a given exponent is likely to be changed by the number of bits due to normalization. Circuit 341 and circuit 3
71 and generates a focus button for the main exponent part. A circuit 370 generates a focus pattern for the sub-exponent part. circuit 37
5 generates a focus button for the mantissa. Circuit 380 combines the major exponent, minor exponent, and mantissa.

This concludes the explanation of the configuration of the embodiment.

Next, details of the operation of the arithmetic device of the embodiment will be explained with reference to FIGS. 3 and 4. The explanation is register 300
The process starts from the time when the exponent part and the mantissa part before normalization are set in the register 305.

First, the exponent part and mantissa part of the operation result before normalization are stored in register 300 and register 305, respectively. This time is set as a reference time and is expressed as to as shown in FIG. It is assumed that both the exponent part and the mantissa part are expressed in the form of a sign and an absolute value. Furthermore, it is assumed that the exponent part is an integer.

The contents of register 300 are applied to signal line 301, which reaches circuit 310. Also, register 300
The sign part of is applied to the signal line 302 and is also applied to the register 300
The absolute value portion of is applied to signal line 303, and signal line 30:
l″l: Reaches register 301.

The sign portion of register 305 is applied to signal line 307;
Signal line 307 reaches register 325.

The absolute value portion of register 305 is also applied to signal line 308 , which reaches circuit 315 .

At time to, when the exponent and mantissa parts before normalization are stored in registers 300 and 305, circuits 310 and 315 start normalizing the exponent and mantissa parts. In the normalization multiplication circuit of this embodiment, the normalization after the operation only shifts the mantissa part to the right by one bit at most. That is, the circuit 315 shifts the absolute value part of the mantissa on the signal line 308 to the right by one pin point as necessary, that is, when normalization is necessary. The result is applied to signal line 318 which reaches register 325. On the other hand, the circuit 310 adds 1 to the exponent part on the signal line 301 as necessary, that is, when the mantissa part is shifted in the circuit 315. The result is signal line 3
11 and the signal line 311 reaches the register 320.

The I/register 20 and the register 325 respectively store the normalized exponent part on the signal line 311, the sign part and the absolute value part of the normalized mantissa part on the signal lines 307 and 318, as shown in FIG. Set to time 1 as shown in .

The sign portion of register 320 is applied to signal line 322;
The signal line 322 reaches the selector 330.

The absolute value portion of register 320 is applied to signal line 323 and reaches selector 331, register 350, and selector 360 by signal line 323.

Further, the sign part of the register 325 is applied to the signal line 327, and the signal line 327 register 356 and the selector 3
It reaches 66. The absolute value part of register 325 is connected to signal line 3.
28, and the signal line 328 reaches the register 355 and the selector 365.

On the other hand, the selector 330 and the selector 331 select the signal line 302 and the signal line 303, respectively, at time to, and set the sign part and the absolute value part of the exponent part before normalization to the signal line 332 and the signal line 303, respectively. 333 is applied. Signal line 332 reaches circuit 335 and register 346. The signal line 333 reaches a circuit 335 and a circuit 336.

The circuit 336 determines from the absolute value portion of the exponent on the signal line 333 how many focuses are required to express the exponent. Specifically, this means that the absolute value of the exponent part is expressed using fixed-point representation, starting from the most significant bit.
It is checked whether adjacent bits match each other, and the number of bits is determined as the number of bits from the focus position where they do not match for the first time to the lowest bit position. The determined result, that is, the number of bits necessary to represent the exponent part, is applied to a signal line 338, which reaches a register 345.

In addition, the circuit 335 can change the number of bits necessary to express the exponent part from the sign part of the exponent part on the signal line 332 and the absolute value part on the signal line 333 by normalizing the mantissa part. Determine whether or not there is sex. The change in the number of bits in the exponent occurs due to carry propagation when 1 is added to the exponent as the mantissa is normalized. Therefore, the specific determination method is as follows. That is, when the sign part of the exponent part on the signal line 332 means positive, the valid part of the absolute value part of the exponent part on the signal line 333,
In other words, it is determined that there is a possibility that the number of bits in the exponent part may be changed only when all the parts excluding the upper bits "0...η" are "1". On the other hand, signal line 33
When the sign part of the exponent part on 2 means negative, the valid part of the absolute value part of the exponent part of signal line 3337J:
It is determined that there is a possibility that the number of bits in the exponent part may be changed only when all of them except the high-order 1 bit are "0". The result of the determination is applied to the signal line 337;
reaches register 340.

At time t1, the register 345 and the register 340 set the number of bits of the exponent part on the signal line 338 and the number of bits on the signal line 33, respectively.
The result of determining the possibility that the focus number of the exponent part above 7 will be changed is set. At the same time, 346 registers, signal a3
Sets the sign part of the exponent part before normalization on T.32.

The contents of register 345 are applied to signal line 348, which reaches circuit 371, circuit 37o1, and circuit 375. The contents of register 340 are applied to signal line 344, which is connected to selector 360, selector 365,
Selector 366 is reached. The contents of register 346 are applied to signal line 347, which reaches circuit 341.

The above operation is performed whenever the exponent part and mantissa part before normalization are sent to register 300 and register 305.

The following operations differ depending on the result of the determination as to whether or not the number of bits of the exponent part is likely to be changed.

First, a case where the number of bits of the exponent part may be changed will be described.

In this case, the number of bits of the exponent part before normalization is set in the register 300 at time io, and the number of bits in the register 300 is set at time t1.
Since there is a possibility that the number of bits of the exponent part after normalization that was set to 0 has been changed, the focus number is determined again based on the exponent part set in the register 320.

That is, at time t1, -selector 330 and selector 3
31 selects the signal line 322 and the signal line 323, respectively,
The sign part and absolute value part of the exponent part after normalization are applied to signal line 332 and signal line 333, respectively. As previously discussed, signal line 332 goes to register 346 and signal line 333 goes to circuit 336 and circuit 335. however,
In this case, circuit 335 is meaningless.

As described above, the circuit 336 determines the number of bits necessary for its representation from the absolute value part of the exponent part and applies it to the signal line 338. Signal line 338 reaches register 345.

As shown in FIG. 4, at time t2, register 345 stores the number of bits necessary to represent the exponent after normalization on signal line 338. At the same time, register 346 is
The sign part of the exponent part after normalization on the signal line 332 is set.

The contents of register 345 are applied to signal line 348, which reaches circuit 371, circuit 37o1, and circuit 375. The contents of register 346 are applied to signal line 347, which reaches circuit 341.

In addition, the register 35o1, the register 355, and the registers 35 and 6 are connected to the absolute value portion of the exponent after normalization on the signal line 323 in order to wait while the circuit 336 determines the number of bits of the exponent. The absolute value part of the mantissa after normalization above and the sign part of the mantissa after normalization on the signal line 327 are respectively set at time t2 as shown in FIG.

At this time, the register 340 stores information indicating that the number of bits in the exponent part may be changed.

The information is applied to signal line 344 and reaches selector 360, selector 365, and selector 366.

Based on the determination signal on the signal line 344, the selector 360, selector 365, and selector 366 respectively select the absolute value part of the exponent part on the signal line 353, the absolute value part of the mantissa part on the signal line 358, and the signal line 357. Select the sign part of the upper mantissa and connect the signal line 363, signal line 368, and
and is applied to the signal line 367. The signal line 363 is the circuit 37
0, the signal line 368 reaches the turning force 375, and the signal line 3
67 reaches circuit 341, circuit 370, and register 385.

Next, a pattern is generated using a real numerical representation method based on double exponential division.

That is, the circuit 341 compares the sign part of the exponent part on the signal line 347 with the sign part of the mantissa part on the signal line 367, determines whether they match, and applies it to the signal m342. Signal line 342 reaches circuit 371. This is used to generate the main index part.

The circuit 371 generates a pattern of the main exponent part based on the determination signal on the signal line 342 and the number of bits of the exponent part on the signal line 348. The generated pattern is applied to a signal line 372, and the wiring line 372 reaches a circuit 380.

The circuit 370 outputs the absolute value part of the exponent on the signal line 363,
The sign part of the mantissa on the signal line 367 and the signal line 348
A sub-exponent pattern is generated based on the number of Ω bits in the exponent part above. The generated pattern is applied to a signal line 373, which reaches a circuit 380.

The circuit 375 generates a mantissa pattern based on the absolute value of the mantissa on the signal line 368 and the number of bits of the exponent on the signal line 348. The generated pattern is applied to signal line 378, which reaches circuit 380.

Circuit 380 performs 9-combination of the patterns of the main exponent, sub-exponent, and mantissa parts on signal line 372, signal line 373, and signal line 378. The combined result pattern is the signal line 38
3 and signal line 383 reaches register 385.

The register 385 sets the code on the signal line 367 and the pattern representing the numerical value on the signal line 383 at time t3, as shown in FIG.

This concludes the explanation of the operation when the number of bits in the exponent part may be changed.

Next, the operation when there is no possibility that the number of bits of the exponent part will be changed will be explained.

In this case, as shown in FIG.
The number of bits in the exponent part set to 5 is used as is.

Further, the register 340 stores information indicating that there is no possibility that the focus number of the exponent part will be changed. The information is applied to signal line 344 and reaches selector 360, selector 365, and selector 366.

Based on the determination signal on the signal line 344, the selector 360, selector 365, and selector 366 select the absolute part of the exponent part on the signal line 323, the absolute value part of the mantissa part on the signal line 328, and the absolute value part of the mantissa part on the signal line 327, respectively. The sign portion of the mantissa is selected and applied to signal line 363, signal line 368, and signal line 367, respectively. Signal line 363 reaches circuit 370, signal line 368 reaches circuit 375, signal line 367
reaches circuit 341.

Subsequently, circuit 341, circuit 371, circuit 370, circuit 3
The operation of generating the numerical pattern by the circuit 75 and the circuit 380 is as described above.

As a result, the register 385 is stored at time t2 as shown in FIG.
, the code on the signal line 367 and the pattern representing the numerical value on the signal line 383 are set.

This concludes the explanation of the operation of the arithmetic device of this embodiment.

Next, effects specific to this embodiment will be explained.

In the conventional method, the number of bits required to express the exponent part was always determined after normalization was completed, so the calculation result was set in the register 385 at time t3.

On the other hand, in this embodiment, in parallel with the normalization, the number of bits required to express the exponent part is determined and whether or not the number of bits is changed by normalization is determined, and as a result of the above determination, If there is no possibility of change, the calculation result is set in the register 385 at time t2.

In the multiplication circuit of this embodiment, the probability that normalization is actually performed on the mantissa part is about half.

Moreover, the number added to the exponent part at this time is 1 at most.

Therefore, the probability that the focus number of the exponent part will change due to carry propagation is extremely small. However, in most cases, the calculation result is obtained at time t2.

〔Effect of the invention〕

According to the present invention, the change in the exponent part due to normalization after calculation is
When generating a numerical pattern when the number of bits does not reach the number of bits, conventionally pattern generation always started after normalization, that is, determining the number of bits in the exponent part, etc., but now it starts at the same time as normalization. As long as there is no possibility that the number of bits in the exponent part will be changed due to normalization, the calculation result can be obtained quickly. Moreover, the probability of obtaining a calculation result earlier than usual is extremely high, especially in normalized multiplication and division. Therefore, the average calculation processing time in the calculation device according to the present invention is shortened.

[Brief explanation of drawings]

Figure 1 is a diagram of the real number representation method based on double exponential division.
FIG. 2 is a diagram showing the procedure for performing multiplication using the real value representation method based on double exponential division, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a diagram showing the main parts of the embodiment of FIG. 3. FIG. 3 is a timing diagram showing the operation. 300..., exponent register before normalization, 305...
- Mantissa register before normalization, 310... Exponent normalization circuit, 315... Mantissa normalization circuit, 320...
Exponent part register after normalization, 325... Mantissa register after normalization, 335... Circuit for determining the possibility that the number of bits of the exponent part will be changed, 336... Number of bits of the exponent part Determination circuit, 340...Register for storing the determination result of the possibility that the number of bits of the exponent part will be changed, 34
5...Register for storing the number of bits of the exponent part, 346
...Exponent part sign part register, 350...Exponent part absolute value part register for waiting, 355...Mantissa part absolute value part register for waiting, 356...mantissa part sign part for waiting Register, 370... Sub-exponent part bang generation circuit, 371... Main exponent part bang generation circuit, 375.
. . . Mantissa part slam generation circuit, 380 . . . Circuit for combining the main exponent part, sub-exponent part, and mantissa part; 385 . . . Register for storing calculation results.

Claims (1)

[Claims] In a device that processes data expressed by a real number representation method based on double exponential division, it is possible to determine whether or not the number of bits of an exponent part is changed by normalization after an operation in a normalization operation. It is equipped with a circuit for determining the number of bits of the exponent part at the same time as the normalization after the operation, and if the above-mentioned determination circuit determines that there is no possibility that the number of bits of the exponent part will be changed, the above-mentioned Using the number of bits in the exponent part as it is, continue to generate a numerical value button using the above expression method and output the result. On the other hand, the above judgment circuit judges that there is a possibility that the number of bits in the exponent part may be changed. If the number of bits in the exponent part is determined, the number of bits in the exponent part is determined again, and then a numerical value stamp is generated using the above expression method and the result is output.