JP2002175179A - Integer dividing method and integer dividing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integer dividing method and an integer dividing device for realizing a high speed integer division by reducing the division processing amount without increasing the circuit scale. SOLUTION: A partial remainder and a partial quotient can be simultaneously determined, division processing processes can be saved, redundant calculations of a dividing circuit are reduced by a higher rank invalid bit number of a dividend and the number of times of repeated processing in the dividing circuit can be reduced without increasing the circuit scale, by providing an estimation digit matching circuit 100 for calculating shift amount based on the invalid bit number of 0 following highest rank figures of the dividend and a divisor, a left shifter 101 for left-shifting the dividend by the shift amount, a divisor converting part 102 for converting the divisor so as to simultaneously determine the partial remainder and the partial quotient when the divisor is subtracted from the dividend, and a division processing part 103 for repeatedly subtracting the divisor, left-shifting the left-shifted dividend 1-bit by 1-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integer division method and an integer division device used for an arithmetic unit or the like of a microprocessor.

[0002]

2. Description of the Related Art Conventionally, as a division algorithm in a division apparatus of this kind, for example, "Patterson &Hennessy" (translated by Mitsuaki Narita) "Computer Configuration and Design: Interface between Hardware and Software" (1996,
Nikkei BP ISBN4-8222-8001-2) P
P. 191 to 201, Chapter 4 Arithmetic and Logic Calculations in Computers, Algorithms shown in Section 4.7 (Division), and algorithms that repeatedly perform shift and subtraction in the same manner as division performed by hand Etc. are known.

A configuration example of a conventional integer division device will be described below with reference to a block diagram of FIG. In FIG. 7, first, when performing integer division of a ÷ b (a is the dividend, b is the divisor), the dividend a is stored in the lower part of the dividend / quotient register 701, and the upper part is set to the initial value 0. Also, the divisor b
Is stored in the upper part of the divisor register 702, and the lower part is set to the initial value 0.

A shifter (shift circuit) 703 shifts the contents of the dividend / quotient register 701 left by one bit. The output data of the shift result is supplied to one input side of an arithmetic logic unit (ALU) 704 for performing subtraction,
The other input of the ALU 704 has a divisor register 7
The divisor b is supplied from 02, and the divisor b is subtracted from the shift result described above. The operation result of the ALU 704 is output to the partial remainder register / partial quotient register 705.

The sign determination signal sine (Si
gn: +,-) are supplied to the LSB (least significant bit) of the partial remainder register / partial quotient register 705 through the inverter 706, and are also supplied to the selector 707. When the operation result of the ALU 704 is positive, the quotient of the digit is “1”, so the value of the sign determination signal sign “0”
Is inverted to make the partial quotient "1". When the operation result of the ALU 704 is negative, the quotient of the digit is "0". Therefore, the value "1" of the sign determination signal sign is inverted and the partial quotient is changed to "1". 0 "
And

The output of the shifter 703 is supplied to one input side of the selector 707, and the output of the partial remainder / partial quotient register 705 is supplied to the other input side. The selector 707 selects one of the two inputs according to the sign determination signal signature supplied from the ALU 704 as follows, and supplies the selection result to the dividend register / quotient register 701. That is, if the operation result of the ALU 704 is negative, the sign determination signal sign becomes “1”,
At this time, since the ALU 704 did not subtract the output of the shifter 703, the selector 707 selects the output data of the shifter 703, and if the operation result of the ALU 704 is positive,
The sign determination signal sign becomes "0". At this time, the selector 707 selects the output of the partial remainder register / partial quotient register 705 which is the result of the subtraction of the ALU 704.

[0007] CLK is input to a counter 708 and counts for each bit. The decoder 709 has a counter 7
When the count of 08 is input and the word length of the integer division is reached, the selector 710 is opened, and the output of the selector 707 is output to the remainder register / quotient register 711.

Hereinafter, with reference to the flowchart of FIG.
An example of a conventional integer division method will be described. In FIG. 8, in the conventional example, it is assumed that integer division of a 16-bit word length is performed. <Initial processing> ● In step S801, the dividend a is substituted for a variable RQ. In step S802, the divisor b is shifted to the left by 16 bits, and the divisor b is substituted for the variable DV. In step S803, the word length of the integer division is assigned to a variable N representing the number of repetitions.

<Repeated Processing> In step S804, the variable RQ is shifted left by one bit. ● In step S805 (when RQ ≧ DV)
Subtracts DV from RQ in step S806 and adds 1 to RQ in step S807 to set the partial quotient to 1. (RQ
In the case of <DV), the partial quotient becomes 0, and step S80
6, S807 is not performed. ● Then, in step S808, steps S804 to S808 are repeated until the number of times reaches N.

<End Processing> In step S809, a remainder r is obtained above the variable RQ, and a quotient q is obtained below the variable RQ. In such integer division by repetition of shift and subtraction, since the calculation is performed for all digits regardless of the values of the dividend and the divisor, the calculation is repeated by the word length of the integer division. Therefore, there has been a problem that the division processing time becomes long.

Therefore, as a conventional method for solving the above-mentioned problems, there is a method disclosed in Japanese Patent Application Laid-Open No. Hei 7-244578. According to this, the shift amount of the dividend a is determined by digit alignment processing,
By performing the conventional division method from the bit position obtained by shifting the dividend a by the shift amount obtained by the digit alignment processing, the division is performed on the number of bits of the difference between the word length and the shift amount. Integer division with less than length can be performed.

Hereinafter, referring to the flowchart of FIG.
An example of a conventional integer division method by digit alignment processing will be described. <Initial processing> ● In step S901, the dividend a is substituted for a variable RQ. In step S902, the divisor b is shifted left by 16 bits, and the divisor b is substituted for the variable DV. In step S920, digit alignment processing is performed to determine the shift amount S of the dividend a.
Will be explained). In step S903, the number of repetitions N is set to a value obtained by subtracting the digit shift amount S from the word length. In step S930, the dividend a is shifted to the left by the shift amount S obtained by the digit alignment processing.

<Iterative processing> Same as the above conventional example. ● In the following steps S904 to S909, the above-described conventional method is executed.

Next, the flowchart of FIG.
The details of the procedure for determining the shift amount S shown in step S920 of FIG. 9 will be described with reference to an example of the procedure for determining the shift amount S. Here, as an example, an operation of calculating the shift amount S when the dividend a = 601 and the divisor b = 33 will be described.
First, as shown in FIG. 11, the variable RQ has a value 601 (binary number: indicated by W10-1), and the variable DV has a value (3
3 << 16 (16-bit left-shifted binary number 3
It is assumed that 3)) is set. [State of W10-1] Hereinafter, characters such as WQ and W10 mean an intermediate result of the calculation.

<Initial processing> In step S921,
The shift amount S is initialized to zero. In step S922, the shift width intermediate value T is set to half the word length, and here T = 8.

<First iteration> In step S923, the current shift amount S = 0 + 8 is determined. Step S
At 924, the variable RQ is shifted leftward by the current shift amount S = 8. [State of W10-2] In step S925, the magnitude relationship between WQ and DV is determined. Since WQ is smaller than DV, the process proceeds to step S927. In step S927, the shift width intermediate value T is set to half the current value. Here, T = 4. In step S928, since the shift width intermediate value T is not 0, the repetition processing is performed.

<Second iteration> In step S923, the current shift amount S = 8 + 4 is determined. Step S
At 924, the variable RQ is shifted leftward by the current shift amount S = 12. [State of W10-3] In step S925, the magnitude relationship between WQ and DV is determined. Since WQ has become too larger than DV, step S925 is performed.
At 926, the shift amount S is set to 12-4, and the original value is restored. In step S927, the shift width intermediate value T is set to half the current value. Here, T = 2. In step S928, since the shift width intermediate value T is not 0, the repetition processing is performed.

<Third iteration> In step S923, the current shift amount S = 8 + 2 is determined. Step S
At 924, the variable RQ is shifted to the left by the current shift amount S = 10. [State of W10-4] In step S925, the magnitude relationship between WQ and DV is determined. Since WQ is still smaller than DV, step S927 is performed.
Proceed to. In step S927, the shift width intermediate value T
Is set to half of the current. Here, T = 1. In step S928, since the shift width intermediate value T is not 0, the repetition processing is performed.

<Fourth iteration> In step S923, the current shift amount S = 10 + 1 is determined. In step S924, the variable RQ is set to the current shift amount S = 11.
To shift left. [State of W10-5] In step S925, the magnitude relationship between WQ and DV is determined. Since WQ is still smaller than DV, step S927 is performed.
Proceed to. In step S927, the shift width intermediate value T
Is set to half of the current. Here, T = 0. In step S928, since the shift width intermediate value T is 0, the repetition processing ends.

As described above, the procedure for determining the shift amount S is to reduce the shift width intermediate value to half of the word length by the binary search algorithm, and to determine the shift increment by the magnitude relationship between the dividend a and the divisor b. Switch the direction left and right,
The shift amount S is determined by converging to a target shift position.

[0021]

However, when the above-described integer division algorithm of the first prior art is realized by software in a DSP or the like that does not have a divider, a procedure of 4 steps per bit is required, Further, since calculation is required for all digits regardless of the values of the dividend a and the divisor b, the time cost required for the division requires a minimum of word length times × 4 steps. For example, in the case of a 16-bit word length, Since 16 times × 4 steps = 64 steps are required, there is a problem that the division processing time is long.

In the second prior art division method in which the number of repetitions is made smaller than the word length by digit alignment processing, the number of repetitions of division can be reduced, but in the digit alignment processing, log ₂ N times (N 5 steps are required for the shift procedure of the word length), the comparison procedure, and the determination of the shift increment value. There are many pre-processing procedures for the conventional division process, and the longer the word length, the more the digit alignment. processing amount is increased, for example, in the case of 16-bit word length, etc. require log ₂ 16 × 5 = 20 steps digit alignment treatment, there is a problem that division processing time is greater.

Further, in the second prior art division device in which the number of repetitions is made smaller than the word length by a digit matching circuit,
In addition to an increase in the processing amount, there is a problem that the scale of the shift amount determination circuit becomes large in order to perform digit alignment.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an integer division method for realizing a high-speed integer division by reducing the amount of division processing without increasing the circuit scale. An integer division device is provided.

[0025]

The integer division method according to the present invention converts the divisor before the division processing so that the partial remainder and the partial quotient are simultaneously obtained when the divisor is subtracted from the dividend, and the dividend is divided by one bit. The divisor is repeatedly subtracted from the dividend while shifting to the left, and the quotient of each digit is obtained. According to this configuration, the divisor is converted so that the partial remainder and the partial quotient are simultaneously obtained when the divisor is subtracted from the dividend, so that the procedure for obtaining the partial remainder and the procedure for obtaining the partial quotient are simultaneously performed. One process can be saved.

According to the integer division method of the present invention, the shift amount of the dividend is obtained by rough estimation based on the number of invalid bits consisting of 0 following the most significant digit of the dividend, and the dividend is left-shifted by the obtained shift amount. , And repeatedly subtracting the divisor from the dividend while shifting left by one bit from the left-shifted bit position. According to this configuration, the partial remainder and the partial quotient are obtained simultaneously, and the dividend is left-shifted based on the number of invalid bits consisting of 0s following the most significant digit of the dividend, whereby the redundant operation of the division processing procedure is performed in advance. Can be reduced, and the number of repetitions of the division processing procedure can be reduced.

In the integer division method according to the present invention, the final number of the dividend is approximated based on the number of invalid bits consisting of 0 following the most significant digit of the dividend and the number of invalid bits consisting of 0 following the most significant digit of the divisor. The dividend is left-shifted by the obtained final shift amount, and the divisor is repeatedly subtracted from the dividend while shifting left by one bit from the left-shifted bit position to obtain a quotient of each digit. It has the structure of. With this configuration, the partial remainder and the partial quotient are simultaneously obtained, and the dividend is calculated based on the number of invalid bits consisting of 0 following the most significant digit of the dividend and the number of invalid bits consisting of 0 following the most significant digit of the divisor. Is shifted to the left, redundant operations in the division procedure can be reduced in advance, and the number of repetitions of the division procedure can be reduced.

The integer division device according to the present invention comprises: a first digit matching circuit for roughly calculating the shift amount of the dividend based on the number of invalid bits consisting of 0s following the most significant digit of the input dividend; A shift circuit that shifts the dividend to the left by a shift amount;
And a division circuit for repeatedly subtracting the divisor from the dividend while shifting left by a bit to obtain a quotient of each digit. With this configuration, the shift amount of the dividend is roughly determined from the number of invalid bits following the most significant digit of the dividend by the first digit matching circuit, and the dividend is left-shifted by the shift circuit, whereby the redundancy of the division circuit is determined in advance. The number of repetitive processes in the division circuit can be reduced without increasing the number of operations and increasing the circuit scale.

The integer division device according to the present invention approximates the number of invalid bits consisting of 0 following the most significant digit of the input dividend and the number of invalid bits consisting of 0 following the most significant digit of the inputted divisor. A second digit alignment circuit for calculating the shift amount of the dividend, a shift circuit for shifting the dividend left by the determined shift amount, and calculating the divisor from the dividend while shifting left by one bit from the bit position left shifted. And a division circuit for repeatedly subtracting to obtain a quotient of each digit. With this configuration, the first
The shift amount of the dividend is roughly determined from the number of invalid bits following the most significant digit of the dividend and the divisor by the digit matching circuit of
By shifting the dividend to the left by the shift circuit, redundant operations of the division circuit can be reduced in advance, and the number of repetitive processes in the division circuit can be reduced without increasing the circuit scale.

The integer division device according to the present invention shifts by approximation based on the number of invalid bits consisting of 0 following the most significant digit of the input dividend and the number of invalid bits consisting of 0 following the most significant digit of the inputted divisor. An approximate digit matching circuit for calculating the quantity, a left shifter for shifting the dividend to the left by the calculated shift amount, and the divisor before the division process so that a partial remainder and a partial quotient are obtained simultaneously when the divisor is subtracted from the dividend. And a division processing unit for repeatedly subtracting the converted divisor while shifting the dividend left-shifted by one bit to the left to obtain a quotient of each digit. I have. With this configuration, the divisor is converted so that the partial remainder and the partial quotient are obtained at the same time when the divisor is subtracted from the dividend by the divisor conversion means, so that one step can be saved in the division process by the division circuit. Approximately determining the shift amount of the dividend from the dividend and the number of invalid bits following the most significant digit of the divisor by the matching circuit, and shifting the dividend to the left by the shift amount by the shift circuit to perform the redundant operation of the division circuit in advance. It is possible to reduce the number of repetitive processes in the division circuit without reducing the circuit scale.

The recording medium according to the present invention has a configuration in which a program for causing a computer to execute each processing step in the integer division method according to any one of claims 1 to 3 is recorded in a computer-readable manner. . With this configuration, a program that implements the integer division method according to the present invention is stored in a plurality of types of recording media, and can be read by another computer.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, first to seventh embodiments of the present invention will be described in detail with reference to the accompanying drawings. (First Embodiment) First, a processing procedure (processing step) of an integer division method according to a first embodiment of the present invention will be described with reference to a flowchart of FIG. In the present embodiment, as shown in FIG. 12, a partial remainder a 'is set at an upper position of a variable RQ, and a partial quotient a "is set at a lower position, and (divisor b << 16-1) is set as a variable DV. Is set.

<Initial Processing> In step S201, the dividend a is substituted for a variable RQ. ● In the divisor conversion step S202, the divisor b is shifted to the left.
The value obtained by subtracting 1 from the value shifted by 16 bits is substituted for the variable DV. (* The difference from the conventional example is that 1 is subtracted.) In step S203, the word length of the integer division is substituted into a variable N representing the number of repetitions.

<Repetition Processing> In step S204, the variable RQ (partial dividend / partial quotient) is shifted one bit to the left. ● In step S205, [if RQ> DV]
Sets the partial quotient to 1 only by subtracting DV from RQ in step S206. (* The difference from the conventional example is the presence or absence of an equality sign.) [In the case of RQ ≦ DV], the partial quotient becomes 0, and the process proceeds to step S207 without performing step S206. ● In step S207, steps S204 to S207 are repeated until N times are reached.

<End Processing> In step S208, the remainder r is obtained above the variable RQ, and the quotient q is obtained below the variable RQ.

Next, the operation principle of the integer division method according to the first embodiment of the present invention will be described in detail with reference to FIG. In the present embodiment, the variable R
The partial remainder a 'is set at the upper part of Q, the partial quotient a "is set at the lower part, and (divisor b << 16-1) is set as the variable DV. The divisor b-1) is
That is, (−1) is set in the lower order. [RQ
> DV], that is, if RQ> b-1, then R
Q ← RQ−DV is subtracted, and the lower order of the variable RQ is
a ″ +1 is obtained by a ″ − (− 1). The top of the variable RQ is
Since there is a Borrow from the bottom, a'-1- (b-1)
[In the case of RQ = DV], that is, RQ = b−1, and since RQ <b, no operation is performed. [RQ <DV
In other words, RQ <b-1 and RQ <b, so that no operation is performed. Therefore, an operation equivalent to the conventional method is performed.

As described above, according to the first embodiment of the present invention, by adding the divisor conversion step S202 before the repetition procedure of division, the dividend a The procedure for obtaining the partial remainder by subtracting the divisor b from the above and the procedure for obtaining the partial quotient can be performed at the same time, and the procedure which conventionally required a 4-step procedure per bit can be performed in a 3-step procedure. , The amount of processing per bit can be reduced.

For example, in the case of a 16-bit word length,
The processing amount that required 6 steps × 4 steps = 64 steps can be reduced to the processing amount of 16 times × 3 steps = 48 steps, and integer division can be performed at high speed.

(Second Embodiment) Next, referring to a flowchart of FIG. 3, an integer division method for calculating a shift amount by digit alignment processing of a dividend in a second embodiment of the present invention. The processing procedure will be described. <Initial processing> ● Leading zero in step S301
ro) In the process, an invalid bit number consisting of 0 following the MSB (most significant digit) of the dividend a is obtained. This bit number is used as a rough approximation as the shift amount S for digit alignment. In step S302, the dividend a is shifted by the shift amount S
Is shifted to the left, and assigned to the variable RQ. ● In the divisor conversion step S303, the divisor b is shifted to the left.
The value obtained by subtracting 1 from the value shifted by 16 bits is substituted for the variable DV. In step S304, a value obtained by subtracting the shift amount S shifted earlier from the word length of the integer division is substituted into the variable N as the number of repetitions. <Repeated processing> The repeated processing from step S305
This is the same as that of the first embodiment.

Next, the operation principle of the integer division method for calculating the shift amount by digit alignment processing of the dividend in the second embodiment of the present invention will be described in detail with reference to the explanatory view of the operation principle of FIG. Will be described. Here, the dividend a = 60
The operation when 1, the divisor b = 33 will be described. In FIG. 13, as long as the invalid 0 following the MSB (most significant digit) of the dividend a continues, at least (RQ> D
V) does not hold. That is, useless repetitive processing is performed. Therefore, M of the value 601 of the dividend a
When 0 following the SB (most significant digit) is counted by the leading zero procedure, S = 6 bits. This shift amount S
Is used as a rough estimate of the digit alignment process, and the
By shifting the dividend a in advance at 02, redundant calculations in the division processing procedure can be reduced.

As described above, according to the second embodiment of the present invention, prior to the repetition procedure of division, as a digit alignment process, a rough shift is calculated in step S301 to obtain a shift amount. By performing the division from the bit position where the dividend a is shifted by the final shift amount obtained by the rough estimation, the number of repetitions can be reduced with a small number of procedures. However, the number of repetitions is larger than that of the conventional digit alignment processing because of the rough estimation accuracy, but the digit alignment processing amount is only two steps compared to the conventional log ₂ N (N is the word length) × 5 steps. It can be reduced and it is not affected by the word length. In particular, the effect is large when the value of the dividend a is small. For example, in the case of a 16-bit word length, the processing amount which conventionally required log ₂ 16 × 5 steps = 20 steps in the digit alignment processing can be reduced to the processing amount of 2 steps, and the integer division can be performed at high speed. Can be.

(Third Embodiment) Next, with reference to the flowchart of FIG. 4, an integer for calculating a shift amount of a dividend by digit alignment processing of a dividend and a divisor in a third embodiment of the present invention. The processing procedure of the division method will be described. <Initial processing> In the leading zero processing of step S401, an invalid bit number S1 consisting of 0 following the MSB (most significant digit) of the dividend a is obtained. In the leading zero process of step S402, an invalid bit number S2 consisting of 0 following the MSB (most significant digit) of the divisor b is obtained. ● In step S403, a digit shift amount S
= S1-S2 + 15 is roughly calculated. In step S404, the dividend a is shifted by the shift amount S
Is shifted to the left, and assigned to the variable RQ. In the divisor conversion step S405, a value obtained by subtracting 1 from a value obtained by shifting the divisor b 16 bits to the left is substituted for a variable DV storing the divisor b. In step S406, a value obtained by subtracting the shift amount S shifted earlier from the word length of the integer division is substituted for a variable N representing the number of repetitions. <Repetition processing> The repetition processing from step S407 is as follows.
This is the same as that of the first embodiment.

Next, with reference to the explanatory diagram of the operation principle of FIG. 14, the operation of the integer division method for calculating the shift amount of the dividend by digit alignment of the dividend and the divisor in the third embodiment of the present invention. The principle will be described in detail. here,
The operation when the dividend a = 601 and the divisor b = 33 will be described. As long as the invalid 0 following the MSB (most significant digit) of the dividend a and the valid bits of the divisor b continue at least,
(RQ> DV) in step S408 does not hold. That is, useless repetitive processing is performed. Therefore, 0 following the MSB (most significant digit) of the value 601 of the dividend a
Are counted in the leading zero procedure, S1 = 6 bits. Next, the MSB (most significant digit) of the value 33 of the divisor b
When the following 0 is counted in the leading zero procedure, S2
= 10 bits. Shift amount S = S1 + (16−S
2) By using -1 = S1−S2 + 15 as an approximation for digit alignment processing and shifting the dividend a in advance in step S404, redundant calculations in the division processing procedure can be reduced.

As described above, according to the third embodiment of the present invention, before the repetition procedure of the division, as a digit alignment process, the shift amount is roughly calculated in steps S401 to S403. By shifting the dividend a by the final shift amount obtained by the approximation of the matching process and performing the division from the shifted bit position, the number of times of division can be reduced in a small number of steps.

According to the integer division method of the present embodiment, the accuracy of the estimation is high, and the number of repetitions is equal to or one more than that of the conventional digit alignment processing. For it,
The digit alignment processing amount is the conventional log ₂ N (N is the word length) × 5.
The number of steps can be reduced to only 5 steps, and the number is not affected by the word length. The case where the dividend a = 601 and the divisor b = 33 in the above example is equivalent to the conventional method. If the dividend a = 601 and the divisor b = 40, since (RQ> DV) is not established in the first determination,
Only one increase compared to the conventional method.

For example, in the case of a 16-bit word length, the conventional log ₂ 16 × 5 steps = 20
The processing amount that required a step can be reduced to a processing amount of five steps, and integer division can be performed at high speed.

(Fourth Embodiment) Next, an integer division device according to a fourth embodiment of the present invention will be described with reference to the block diagram of FIG. The integer division device according to the present embodiment shown in FIG. 5 includes a rough approximation digit matching circuit 520 including a leading zero count circuit (leading zero circuit, the same applies hereinafter) 521 for counting the leading zero of the dividend a, (Shift circuit) 510 that shifts left by the number of, and a divider 500 that divides the dividend a shifted left by leading zero by the divisor b.

That is, in the integer dividing apparatus according to the present embodiment, the leading zero circuit 521 in the digit matching circuit 520 counts invalid 0s following the MSB (most significant digit) of the dividend a, and converts this value to a rough approximation. The conventional divider 500 divides the dividend a from the bit position shifted by the shifter 510 by the final shift amount S obtained by the rough approximation of the coarse approximation circuit 520 as the shift amount S.

As described above, according to the fourth embodiment of the present invention, the rough approximate digit alignment circuit 520 obtains the shift amount by the rough estimation, and the rough approximate digit alignment circuit 520 obtains the shift amount. By performing division from the bit position where the dividend a is shifted by the final shift amount obtained, the number of clocks until a result is obtained can be reduced. However, because of the rough estimation accuracy, the number of clocks after digit alignment is larger than that of a conventional digit alignment circuit. The rough approximation digit matching circuit 520 can obtain the shift amount by only one clock by the rough approximation digit matching circuit 520 as compared with the case where the shift amount is obtained by log ₂ N (N is the word length) conventionally. It is less affected by length. In particular, the effect is large when the value of the dividend a is small.
The circuit scale is only the addition of the leading zero circuit 521 of the dividend a, and can be realized by a small-scale circuit.

For example, in the case of a 16-bit word length, the rough approximate digit alignment circuit 520 conventionally calculates the shift amount by log ₂ 16 = 4 times alignment, but only 1
It can be obtained with a clock, and integer division can be performed at high speed without increasing the circuit scale.

(Fifth Embodiment) Next, an integer division apparatus according to a fifth embodiment of the present invention will be described with reference to the block diagram of FIG. The integer division device according to the present embodiment shown in FIG. 6 includes a leading zero count circuit (leading zero circuit, hereinafter the same) 621 for counting leading zero of dividend a and a leading zero circuit 622 for counting leading zero of divisor b.
An approximate digit matching circuit comprising: a subtractor 623 for subtracting the output of the leading zero circuit 622 from the output of the leading zero circuit 621; and an adder 624 for adding 15 to the output of the subtractor 623 and outputting an approximate shift amount. 620
And a shifter 610 that shifts the dividend a left by the approximate shift amount, and a divider 600 that divides the dividend a left shifted by the approximate shift amount by the divisor b.

That is, in the integer dividing apparatus according to the present embodiment, in the approximate digit matching circuit 620, the leading zero circuit 621 counts invalid 0 following the MSB (most significant digit) of the dividend a, and the leading zero circuit 622
, The invalid 0 following the MSB (most significant digit) of the divisor b is counted, the output of the leading zero circuit 622 is subtracted from the output of the leading zero circuit 621 by the subtractor 623, and the output of the subtractor 623 is output by the adder 624. The value obtained by adding the value 15 is regarded as an approximate shift amount, and the divider 600 is shifted from the bit position where the dividend a is shifted by the shifter 610 with the final shift amount obtained by the estimation of the approximate digit aligning circuit 620 as in the related art. Performs division.

As described above, according to the fifth embodiment of the present invention, the dividend a
And the approximate shift amount of the divisor b, and the dividend a by the final shift amount obtained by the approximate calculation of the approximate digit alignment circuit 620.
Is shifted to the left, and the divisor b is divided from the bit position shifted to the left, whereby the number of clocks until a result is obtained can be reduced as compared with the conventional method.

Although the approximate digit matching circuit 620 of the integer division device according to the present embodiment has a high approximate accuracy,
The number of clocks after digit matching is equal to or one more than that of the conventional digit matching circuit. Approximate digit matching circuit 62
0 is an approximate digit matching circuit 620 compared to the conventional method of finding the shift amount by log ₂ N (N is word length) digit matching.
Can be obtained with only one clock, and the number is reduced without being affected by the word length. The circuit scale can be realized by a small-scale circuit only by adding a leading zero circuit of the dividend a, a leading zero circuit of the divisor b, a subtractor and an adder.

For example, in the case of a 16-bit word length, in the approximate digit alignment circuit 620, the shift amount can be obtained with only one clock, as compared with the conventional method in which log ₂ 16 = 4 times of alignment was obtained. Integer division can be performed at high speed without increasing the circuit scale.

(Sixth Embodiment) The integer division method according to the embodiment of the present invention can be realized by a software program, and the software program is recorded on a recording medium such as a floppy (registered trademark) disk. Can be transported. The software program recorded on the recording medium is independent of other computer
The embodiment of the present invention can be easily implemented by reading from the recording medium by the system.

That is, the software program can be recorded and reproduced on a recording medium such as a floppy disk by the floppy disk device connected to the computer system. When recording, a software program is recorded on a floppy disk from a floppy disk device of the computer system. When reproducing, a software program can be read from a floppy disk by a floppy disk device and transferred to a computer system for execution.

As a recording medium, in addition to a floppy disk, an optical disk, a magneto-optical disk or the like may be used. Further, the recording medium is not limited to these, and any recording medium such as an IC card and a ROM cassette, which can record a program, can be similarly implemented.

(Seventh Embodiment) Next, an integer division device according to a seventh embodiment of the present invention will be described with reference to the block diagram of FIG. The integer division device according to the present embodiment shows the entire configuration of the integer division device according to the embodiment of the present invention. The integer division device according to the present embodiment includes a digit alignment processing unit that counts leading zeros of a dividend a and a divisor b to determine a shift amount of a dividend a, and a left shifter 101 that shifts the dividend a left by the determined shift amount. A divisor conversion unit 102 for converting the divisor b so that a partial remainder and a partial quotient are simultaneously obtained when the divisor b is subtracted from the dividend a, a division processing unit 103 for subtracting the divisor b from the dividend a, A counter 104 counts the clock by a clock (CLK), a decoder 105 decodes the count result, and a selector 106 outputs a calculation result of the division processing unit 103. That is, the integer division device according to the present embodiment has all the components for realizing the integer division devices according to the first to fifth embodiments.

Next, the operation of the integer division device according to the seventh embodiment of the present invention will be described with reference to FIG. First, the digit alignment processing unit 100 checks the bit patterns of the dividend a and the divisor b, roughly calculates a shift amount for reducing redundant operations in the division process, and transmits the shift amount to the left shifter 101 and the decoder 105. The left shifter 101 shifts the dividend a to the left based on the obtained shift amount. The divisor conversion unit 102 converts the divisor b by, for example, shifting left by 16 bits and subtracting 1 in advance. The division processing unit 103 inputs the dividend a processed from the output of the left shifter 101,
Input the processed divisor b from the output of the divisor conversion unit 102, subtract the divisor b from the partial dividend a while shifting the dividend a left one bit at a time, and perform integer division by the pullback method for repeatedly obtaining the quotient of each digit. Do.

The counter 104 counts up the number of bits of the division process in synchronization with CLK. Decoder 1
05 decodes the count result and outputs a signal to the selector 106 when the count reaches a predetermined count. The selector 106 selects and outputs the operation result of the division processing unit 103, and outputs the remainder r
And quotient q.

As described above, according to the seventh embodiment of the present invention, the divisor b is converted in advance by the divisor conversion unit 102, thereby reducing the amount of division processing per bit in the division processing unit 103. be able to. In the digit matching processing unit 100, the dividend a and the divisor b
Based on the leading zero of, the shift amount of the digit alignment is roughly determined, the dividend a is previously shifted by the shift amount by the left shifter 101, and division is performed from the bit position after the shift by the division processing unit 103. The number of times of division can be reduced. Due to the reduction in the processing amount per bit and the reduction in the number of repetitions, integer division can be realized at high speed.

[0063]

The integer division method and the integer division apparatus according to the present invention are constructed as described above. In particular, when the divisor is subtracted from the dividend by adding a divisor conversion procedure before the repetition procedure of the division. , The partial remainder and the partial quotient are obtained at the same time, and the amount of division processing per bit is reduced, whereby integer division can be performed at high speed.

In addition, the integer division method and the integer division apparatus according to the present invention can provide a rough circuit based on an invalid bit number consisting of 0s following the MSB (most significant digit) of the dividend before repeating the division by a few circuits. By shifting the dividend by the approximate shift amount and performing digit alignment processing of the dividend and the divisor, the number of repetitions of the division processing can be reduced and the integer division can be performed at high speed without increasing the circuit. it can.

Further, the integer division method and the integer division apparatus according to the present invention can reduce the number of invalid bits consisting of zeros following the MSB (most significant digit) of the dividend and the divisor before repeating the division by a small circuit. 0 following MSB (most significant digit) of
By shifting the dividend by the shift amount roughly calculated based on the invalid bit number consisting of and executing the digit alignment processing of the dividend and the divisor, without increasing the circuit,
Integer division can be performed at high speed by reducing the number of repetitions of the division process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire configuration of an integer division device according to an embodiment of the present invention;

FIG. 2 is a flowchart showing an integer division method according to the first embodiment of the present invention;

FIG. 3 is a flowchart showing an integer division method according to the second embodiment of the present invention;

FIG. 4 is a flowchart illustrating an integer division method according to a third embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of an integer division device according to a fourth embodiment of the present invention;

FIG. 6 is a block diagram showing a configuration of an integer division device according to a fifth embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of an example of a conventional integer division device;

FIG. 8 is a flowchart showing an example of a conventional integer division method;

FIG. 9 is a flowchart showing an example of a conventional integer division method with digit matching processing;

FIG. 10 is a flowchart showing an example of a method of determining a shift amount in the conventional integer division method with digit alignment processing;

FIG. 11 is an explanatory diagram illustrating an example of a conventional integer division method with digit alignment processing;

FIG. 12 is an explanatory diagram illustrating an integer division method according to the first embodiment of the present invention;

FIG. 13 is an explanatory diagram for explaining a digit alignment processing procedure of the integer division method according to the second embodiment of the present invention;

FIG. 14 is an explanatory diagram illustrating a digit alignment processing procedure of the integer division method according to the third embodiment of the present invention.

[Explanation of symbols]

100 digit alignment processing unit 101 left shifter 102 divisor conversion unit 103 division processing unit S202, S303, S405 divisor conversion procedure S301 rough approximate digit alignment procedure S401 approximate digit alignment procedure 1 S402 approximate digit alignment procedure 2 S403 approximate digit alignment procedure Procedure 3 S302, S404 Shift procedure 520 Rough approximate digit matching circuit 620 Approximate digit matching circuit 510, 610, 703 Shifter (shift circuit) 500, 600 Division circuit 623 Subtractor 624 Adder 521, 621, 622 Reading zero circuit (Reading zero) Count circuit) 701 dividend register / quotient register 702 divisor register 704 arithmetic logic unit (ALU) 705 partial remainder register / partial quotient register 706 inverter 707, 710 selector 708 cow Data 709 decoder 711 remainder register and business register

Claims (7)

[Claims] 1. A divisor is converted before a division process so that a partial remainder and a partial quotient are simultaneously obtained when the divisor is subtracted from the dividend, and the divisor is repeatedly subtracted from the dividend while shifting the dividend left by one bit. An integer division method, wherein the quotient of each digit is obtained by using 2. A method of calculating a shift amount of the dividend by rough estimation based on the number of invalid bits consisting of 0s following the most significant digit of the dividend, shifting the dividend left by the determined shift amount, 2. The method according to claim 1, wherein the divisor is repeatedly subtracted from the dividend while shifting left by one bit from the position. 3. A final shift amount of the dividend is obtained by rough estimation based on the number of invalid bits consisting of 0 following the most significant digit of the dividend and the number of invalid bits consisting of 0 following the most significant digit of the dividend. The dividend is left-shifted by the obtained final shift amount, and the divisor is repeatedly subtracted from the dividend while shifting leftward by one bit from the left-shifted bit position to obtain a quotient of each digit. Item 1. The integer division method according to Item 1. 4. A first digit aligning circuit for calculating a shift amount of the dividend by approximation based on the number of invalid bits consisting of 0s following the most significant digit of the input dividend, and calculating the dividend by the determined shift amount. An integer division device comprising: a shift circuit for shifting left; and a division circuit for repeatedly subtracting the divisor from the dividend while shifting left by one bit from the left-shifted bit position to obtain a quotient of each digit. 5. The shift amount of the dividend is obtained by rough estimation based on the number of invalid bits consisting of 0 following the most significant digit of the input dividend and the number of invalid bits consisting of 0 following the most significant digit of the inputted divisor. A second digit aligning circuit, a shift circuit for shifting the dividend to the left by the determined shift amount, and repeatedly subtracting the divisor from the dividend while shifting left by one bit from the bit position shifted left; And a division circuit for obtaining a quotient of the integer. 6. An approximate digit for calculating a shift amount by rough estimation based on the number of invalid bits consisting of 0 following the most significant digit of the input dividend and the number of invalid bits consisting of 0 following the most significant digit of the inputted divisor. A matching circuit, a left shifter that shifts the dividend left by the calculated shift amount, and a divisor conversion unit that converts the divisor before the division process so that a partial remainder and a partial quotient are simultaneously obtained when the divisor is subtracted from the dividend. And a division processing unit for repeatedly subtracting the converted divisor while shifting the dividend left-shifted one bit at a time to obtain a quotient of each digit. 7. A computer-readable recording medium in which a program for causing a computer to execute each processing step in the integer division method according to claim 1 is recorded.