RU2276805C2 - Method and device for separating integer and fractional components from floating point data - Google Patents

Abstract

FIELD: data processing technologies, in particular, method and device for decreasing number of operations with floating point, required for extracting integer and fractional components.

SUBSTANCE: device has computing component, which generates first constant, second value by means of shifting truncated integer part of value with floating point, value with floating point by subtracting first constant from floating point value, extracts multiple mantissa bits from second value to produce integer value, generates remainder value from floating point value, extracts part of bits from integer value to produce integer component, stores remainder value, integer component and floating point component in memory.

EFFECT: decreased computation time without negative effect on precision of result.

7 cl, 8 dwg

Description

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The invention relates to computational data processing and, more specifically, relates to a method and apparatus for reducing the number of floating-point operations required to extract an integer and fractional component.

State of the art

In many current data processing systems, such as personal computers (PCs), mathematical calculations play an important role. Numerical algorithms for calculating the values of many mathematical functions, such as exponentiation and trigonometric operations, require decomposition of floating-point numbers into corresponding integer and fractional parts. Such operations can be used to reduce arguments, pointers to table values, or to construct a result from a number of components. Decompositions of floating point numbers into integer and fractional parts are often found in critical computational paths. As a result, the time to perform calculations of the values of mathematical functions is often limited.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and is not limited to the accompanying explanatory drawings, in which like references denote like elements. It should be noted that references to “one” or “some” implementation in this description do not necessarily refer to the same implementation, and similar links refer to at least one implementation.

Figure 1 illustrates the ANSI / IEEE 754-1985 standard, the IEEE standard for binary floating-point arithmetic, IEEE, New York 1985 (IEEE) single-precision floating-point representation, double-precision representation, and extended double-precision representation.

Figure 2 depicts a typical method for calculating integers and floating point numbers for some equalities.

Figure 3 illustrates one implementation of the present invention in which the number of floating-point operations necessary to calculate the integer and fractional components is reduced.

Figure 4 contains one implementation of the invention used to generalize the choice of the constant S.

Figure 5 illustrates a typical process of loading constants and calculating the necessary coefficients for decomposing floating-point numbers into integer and fractional parts.

6A-B show some embodiment of the invention for loading constants and decomposing floating-point numbers into integer and fractional parts.

7 shows some implementation of the present invention having a computing component.

DETAILED DESCRIPTION OF THE INVENTION

In General, the invention relates to a method and apparatus for reducing the number of floating point operations necessary for calculating the integer and fractional components. Next, with reference to the figures, typical implementations of the present invention will be described. Typical implementations are selected in order to illustrate the invention and should not be construed as limiting the scope of the invention.

1 illustrates the ANSI / IEEE 754-1985 standard, the IEEE standard for binary floating-point arithmetic, IEEE, New York 1985 (IEEE) images for representing 105 single-precision floating-point numbers, double-precision representations 106, and 107 representations with extended double precision. A single-precision representation of IEEE 105 requires a 32-bit word. This 32-bit word can be represented by bits numbered from left to right (from 0 to 31). The first bit, marked as S 110, is a bit for the sign. The next eight bits, labeled E 120, are exponent bits. The last 23 bits, from 9 to 31 bits, labeled F 110, are used to represent a significant part of the number (also called mantissa).

For the IEEE standard in double precision representation of a 106 number, the S 110 bit is a sign bit, the E 140 bits are exponent bits (11 bits), and the last F 150 representation bits are 52 bits representing the significant part of the number (also called mantissa) .

For the IEEE standard in double precision representation of a 107 number, bit S 110 is the sign bit, bits E 160 are exponent bits (15 bits), and the last bits of the representation F 170 are 64 bits representing the significant part of the number (also called mantissa) .

As an example of decomposition of floating-point numbers into integer and fractional parts, the following equalities are proposed, which illustrate one similar example:

Given

w = x * A (equality 1),

where A = 1 / B (equality 2).

Find n and r such that x = n * B + r (equality 3),

where n is an integer, and A, B, r and w are floating point numbers. Thus, the problem can be reformulated as follows: for a given input number x and constants A and B, it is necessary to find a number n such that the number B exactly "fits" in the number x exactly and what is the rest? Moreover, n is often used as an index for searching a table or as an exponent of a certain quantity, such as 2 ⁿ . Therefore, it is necessary to represent the number n both as an integer (n _i ) and as a floating-point number (n _f ). Thus, after the calculations, it is necessary to obtain three quantities: n _i (n as an integer), n _f (n as a floating-point number) and r as a floating-point number.

Figure 2 depicts a typical method for calculating n _i , n _f and r. 2, process 200 begins with block 210, where w = x * A. In block 220, the number w is converted to a non-normalized integer obtained after rounding. The value calculated in block 220 is then used in block 230 to calculate n _f by normalizing it as an integer. In block 240, the value from block 220 is also used: converting the value from block 220 to an integer, the number n _{i is} calculated. In block 250, the obtained value of n _{i is} sent to the arithmetic logic unit (ALU) or stored in memory. In block 260, the number r is calculated: the value n _f * B is subtracted from the number x. At block 270, the r value can be sent to the ALU or stored in memory.

Table I illustrates a typical method for computing n _i , n _f, and r in terms of pseudo-code instructions. As can be seen from Table I, there are three floating-point operations that are performed by the floating-point arithmetic and logical unit (Palu), and one integer operation performed by the integer-arithmetic and logical unit (Tsalu). Note that the numbers in parentheses are the total number of clock cycles when executing commands (delay) for a processor such as an Intel Itanium ™ processor.

Table I Palu operas. one w = x * A (one) Palu operas. 2 w_prismount = convert_ to_normalization_ rounded_integer (w) (6) Palu operas. 3 n _f = convert_to_normalized_integer_number (w_prismount) (13) Tsalu operas. one n _i = convert_to_integer (w_prismount) (fourteen) n _i available (eighteen) Palu operas. four r = x-n _f * V (eighteen) r available (23)

Figure 3 illustrates one implementation of the present invention in which the number of floating-point operations needed to calculate n _i , n _f and r is reduced. Process 300 begins at block 310, in which the value x * A + S is calculated, where S and A are constants, and x is a floating-point number. In one implementation of the invention, the constant S is selected so that adding the number S to the number x * A shifts the rounded integer part of the number x * A to the rightmost bits of the mantissa. Then, in block 320, n _{f is} calculated by subtracting S from the value calculated in block 310. Thus, an integer is obtained. In block 330, n _i + S is obtained as follows: the mantissa bits are extracted from the result of block 310. In block 340, the value r is calculated: the value n _f * B is subtracted from x. In block 350, the least significant bits are extracted from the value calculated in block 330 and the value n _{i is} obtained. In block 360, the value of n _{i is} available ready for transmission to the ALU or for storage in memory. At block 370, the value of r is available for transmission to the ALU or for storage in memory.

Table II illustrates the implementation of the present invention in the form of pseudo-code instructions, and in this implementation, the number of floating-point operations is reduced. Note that, as an example, the numbers in parentheses are the total number of clock cycles when executing commands (delay) for a processor such as an Intel Itanium ™ processor. In one implementation of the invention, the constant S is selected so that adding the number S to the number x * A shifts the rounded integer part of the number x * A to the rightmost bits of the mantissa. Thus, S can be converted to an integer n _i after one Palu operation instead of two. Moreover, the floating-point representation n _f can be directly obtained using the second Palu operation: subtracting S from the result of the first Palu operation. Thus, when obtaining the required values, one less Palu command is used. Thus, the implementation of the invention translates into savings of seven clock cycles of the processor, such as the Intel Itanium ™ processor.

Table II Palu operas. one w_plus_S_shifted right = x * A + S (one) Palu operas. 2 n _f = w_plus_S_shifted right - S (6) Tsalu operas. one n _i _plus_S = extract_bit_mantissa (w_plus_S_shifted to the right) (9) Palu operas. 3 r = xn _f * B (eleven) Tsalu operas. 2 n _i = extract_small_bits (n _i _ plus_S) (eleven) n _i available (12) r available (16)

The benefit in productivity increases when using this implementation of the invention in the cycles of software products. Many loops are limited by the number of floating point instructions required for calculations. Since this implementation of the invention assumes one less floating point operation than the typical method, the maximum cycle throughput is increased.

Further discussion relates to the selection of the constant S in one embodiment of the invention. For simplicity, suppose a floating-point representation contains b bits of the mantissa (for example, 64 bits), an explicit integer bit, and b-1 bits of the fractional part. The exponent field of the floating point representation determines the position of the binary point inside or outside the significant digits. Thus, the integer part of the normalized floating-point number is the rightmost mantissa bits after applying the reverse normalization operation, which shifts the b-1 bit of the mantissa to the right, rounds the mantissa, and adds b-1 to the exponent. The mantissa contains integers as a sequence of b bits, which is a complement to 2. The least significant mantissa bits containing the integer part of the original floating-point number can be obtained by adding the constant 1.10 ... 000 * 2 ^{b-1 to the number} . This constant is one of the values of S selected in one implementation of the present invention.

The resulting mantissa contains an integer in the form of (b-2) bits complementing 2. The bit immediately to the left of b-2-x zeros in the significant part is used to ensure that the result is not normalized for negative numbers , thereby shifting the integer to the left of the required position in the rightmost bit of the mantissa. If in subsequent operations with integers less than b-2 bits are used, then the instructions for calculating n _i , n _f and r in Table II are equivalent to the corresponding commands from Table I.

In one implementation of the invention, the choice of the number S can be generalized if the desired result should be equal to m, where m = n * 2 ^k . In this case, the exponent of the constant will be equal to (bk-1). In this implementation, the choice of S is useful when the desired integer must be divided into sets of indices for searching in a table with several inputs. For example, the number n can be broken down as follows n = n ₀ * 2 ⁷ + n ₁ * 2 ⁴ + n ₂ in order to calculate the indices for access to tables with 16 and 8 inputs. For this implementation, it is necessary that the number S be available at the same time that the constant A. In one implementation of the invention, the constant S can be loaded from memory or for processors such as Intel Itanium ™, S can be easily calculated using the following commands: 1) movI for 64-bit IEEE binary double precision, 2) setf.d for loading S into the register for working with floating-point numbers.

In one implementation of the present invention, a constant may take the following form: “1” followed by a decimal point, j-1 bits (zeros or ones) immediately to the right of the decimal point, “1” after the indicated j-1 bits, and then bj-1 bit of zeros. Note that the implementation described earlier contained a constant of the same form with j = 1.

The following discussion relates to the implementation of the present invention, including generating the constants necessary to calculate n _i , n _f and r. Accuracy requirements of mathematical library algorithms usually imply that w = x * A multiplication is performed for representations with extended double precision (64-bit mantissa space). Thus, the constant A at boot should have a representation with extended double precision. Usually this is achieved as follows: the constant is stored statically in memory and then loaded into the register for working with floating-point numbers (for example, the ldfe command for Intel Itanium ™ processor).

Due to the requirement that the library must be located independently (that is, be shared), loading is performed using indirect loading. With this indirect loading, the address of the pointer to the constant is first calculated, then the pointer to the constant is loaded, and then the constant is loaded. For a processor such as Intel Itanium ™, this sequence runs at least 13 clock cycles. This sequence of actions may require more than 13 clock cycles if the pointer and constants are not in the cache.

For some processors, such as Intel Itanium ™, there is no way to directly load the extended double precision constant without using memory instructions. Nevertheless, there is a way to directly load the constant mantissa with a floating point: first, a 64-bit mantissa is formed in the register for working with integers, and then a command is used (for example, set.sig for the Intel Itanium ™ processor) to load the mantissa in the register with floating point. A similar team sets the exponent to 2 ⁶³ . For a processor such as Intel Itanium ™, this sequence runs in 10 cycles. In one implementation of the invention, three measures can be stored using a constant S having the correct mantissa but a modified exponent.

Figure 4 illustrates one implementation of the invention used to generalize the choice of the constant S in determining n _i , n _f and r. In process 400, at block 410, the result x * A ′ + S ′ is calculated (where S ′ is the S variant, which will be discussed below). In block 420, using the result of block 410, the result of block 410 is multiplied by T (T is a factor of 2 ^{- (b-1-j)} ), and S is subtracted from the result obtained. In block 430, the mantissa bits are extracted from the result block 410, so an integer is obtained. In block 440, r is calculated, namely, the expression xn _f * B is calculated. In block 450, the least significant bits are extracted from the result of block 430. In block 460, the value of n _{i is} available for transmission to the ALU or for storage in memory. In block 470, the value of r is available for transmission to the ALU or for storage in memory. In process 400, the value of A is 2 ^{j *} F, where F is the mantissa of the form 1.xxxxxxxx, 1.0≤ | F | <2.0. Also A '= 2 ^b-1 * F.

Table III contains pseudo-codes of steps for the process 400 shown in FIG. 4.

Table III Palu operas. one w_plus_S_shifted right = x * A '+ S' (one) Palu operas. 2 n _f = w_plus_S_shifted right * T-S (6) Tsalu operas. one n _i _plus_S = extract_bit_mantissa (w_plus_S_shifted to the right) (9) Palu operas. 3 r = x-n _f * B (eleven) Tsalu operas. 2 n _i = extract_small_bits (n _i _ plus_S) (eleven) n _i available (12) r available (16)

In one implementation of the invention, in order for the shift to occur correctly, when executing the command of the Palais operas. 1, a variant of the number S is needed - the number S ', where S' = S * 2 ^b-1-j . Upon receipt of n _f during the execution of the Pal oper. 2, the number w_plus_S_shifted to the right is scaled “back” using the factor T, where T = 2 ^{- (b-1-j)} . In this implementation of the invention, four constants are generated: A ', S', S, and T. In one implementation of the invention, these four constants are defined in parallel.

5 illustrates a typical process 500 for loading constants and calculating coefficients for decomposing floating-point numbers into integer and fractional parts. On a regular processor such as Intel Itanium ™, the whole sequence of steps from loading constants to calculate r requires 36 cycles. The process 500 begins at block 510, in which the address of the pointer to A and B is calculated. At block 520, the addresses of the pointer to A and B are loaded. At block 530, A and B are loaded. At block 540, the value w = x * A is calculated. At block 550, the result from block 540 (the number w) is converted to a non-normalized integer. At block 560, the result of block 550 is normalized to an integer and n _{f is} obtained. At block 570, converting the value from block 550 to an integer, the number n _{i is} calculated. In block 580, the obtained value of n _{i is} available for transmission to the ALU or stored in memory. In block 590, the number r is calculated: the value n _f * B is subtracted from the number x. In block 595, the value of r is available for transmission to the ALU or for storage in memory.

Table IV illustrates the process 500 in pseudo-code instructions. The numbers on the right side of Table IV are typical clock cycles for a processor such as Intel Itanium ™.

6A-B show some embodiment of the invention for loading constants and decomposing floating-point numbers into integer and fractional parts. Process 600 begins with block 605, in which a binary code S 'is generated in the register for working with integers. In block 610, the binary code of mantissa A is generated in the register for working with integers. In block 615, S 'is generated in the floating-point register. At block 620, A ′ is generated in the floating point register. In block 625, a binary code for S is generated in the register for working with integers. In block 630, a binary code for T is generated in the register for working with integers. In block 635, the address of the pointer to B. is calculated. In block 640, a floating-point register is generated S. In block 645, a T. is generated in the floating-point register. In block 650, the address of the pointer to B is loaded. In block 655, B. is loaded. In block 660, x * A '+ S' is calculated. In block 665, the result of block 660 is multiplied by T and S is subtracted from the obtained value. The result of operations carried out in block 665 is n _f . At block 670, the mantissa bits are extracted from the result of block 660, thereby obtaining an integer. In block 675, r is calculated, namely: the expression x-n _f * B is calculated. At block 680, the least significant bits are extracted from the result of block 670. The result of operations carried out in block 680 is n _i . At block 685, the value of n _i becomes available for transmission to the ALU or for storage in memory. In block 690, the value of r becomes available for transmission to the ALU or for storage in memory.

Table V contains pseudo-codes of steps for process 600 (see FIGS. 6A-B). Note that the numbers on the right side of Table V, which are enclosed in brackets, represent clock cycles of a processor such as Intel Itanium ™. In one implementation of the present invention, process 300 and process 600 are loaded into math libraries used by various compilers. In another implementation of the invention, the same processes loaded into the mathematical library can be used to calculate functions such as double-scalar tangent, sine, cosine, exponential functions, hyperbolic cosine, hyperbolic sine, hyperbolic tangent and so on. Using this implementation allows you to reduce the number of clock cycles required to perform operations compared with the methods that currently exist. It should be noted that other implementations of the present invention can be used to process functions, such as scalar functions of single precision, vector functions of double precision and vector functions of single precision.

Table v Tsalu operas. one Generate binary code S 'in register for integers (movl) (one) Tsalu operas. 2 Generate binary code of mantissa A in register for integers (movl) (one) Tsalu operas. 3 Generate S 'in a floating point register (setf.d) (2) Tsalu operas. four Generate A 'in a floating point register (setf.d) (2) Tsalu operas. 5 Generate binary S in register for integers (movl) (2) Tsalu operas. 6 Generate binary T in register for integers (movl) (2) Tsalu operas. 7 Calculate the address of a pointer to B (3) Tsalu operas. 8 Generate S in a floating point register (setf.d) (four) Tsalu operas. 9 Generate T in a floating point register (setf.d) (four) Tsalu operas. 10 Download pointer address to B (5) Tsalu operas. eleven Download To (8) Palu operas. one w_plus_S_shifted right = x * A '+ S' (eleven) Palu operas. 2 n _f = w_plus_S_shifted right * T-S (16) Tsalu operas. 12 n _i _plus_S = extract_bit_mantissa (w_plus_S_shifted to the right) (19) Palu operas. 3 r = x-n _f * V (21) Tsalu operas. 13 n _i = extract_small_bits (n _i _ plus_S) (21) n _i available (22) r available (26)

7 shows some implementation of the present invention having a computing component 710. Circuit 700 also includes a microprocessor 720, cache 730, memory 740, disk storage 750, prefetch queue 755, decoder / assignment / extrapolator 760, integer trunk A 770, highway for integers B 775, highway for floating-point numbers A 780, ALU 781-782, ALU for floating point 783, sets of registers for integers 785-786, set of registers for floating point 787 and data bus 790. In one implementation of the present of the invention, computing component 710 includes processes 300, 400, or 600 illustrated in FIGS. 3, 4, and 6A-B, respectively.

The above implementations of the invention can be used whenever integer and fractional components of floating-point numbers are necessary to perform the reduction of the arguments of scalar and vector functions with double precision, scalar and vector functions with single precision, various mathematical functions, and preprocessing before calculating mathematical functions . Using the above-described embodiments of the invention, computation time is reduced without adversely affecting the accuracy of the result.

The above implementations can also be stored on a device or machine-readable medium and read by a machine to execute commands. Machine-readable media include any mechanisms that contain (i.e. store and / or transmit) information that can be read by a machine (e.g., computer). For example, a machine-readable medium may be read-only memory (ROM); random access memory or random access memory (RAM); magnetic disk drive; optical disk; flash memory; an electrical, optical, audible signal, or any other form of propagated signal (for example, carrier waves, infrared signals, digital signals, and so on). The device or machine-readable medium may be a semiconductor memory device and / or a rotating magnetic or optical disk. A device or machine-readable medium can be distributed when parts of the commands are divided between different machines, for example, between networked computers.

Although some typical implementations are described and shown in the accompanying drawings, it must be understood that such implementations are merely illustrations and do not limit the scope of the invention, and that the invention is not limited to the specific structures and structures shown and described herein, as one skilled in the art many other modifications can be offered to the corresponding area.

Claims (25)

1. A method of extracting integer and fractional components from a floating point value, comprising decomposing the floating point value into a plurality of parts, comprising shifting the rounded integer part of the floating point value to generate a second value; generating a floating point value from the second value by subtracting the first constant from the second value; extracting a plurality of mantissa bits from a second value; generating a residual value from a floating point value; extracting a portion of the bits from the plurality of mantissa bits to generate an integer component, where the floating point value, residual value, and integer component are stored in memory and transferred to an arithmetic logic unit (ALU). 2. The method according to claim 1, characterized in that the floating point values, the first constant and the second value are presented in floating point format. 3. The method according to claim 1, characterized in that the rounded integer part is shifted to the rightmost bits of the mantissa of the first value. 4. The method according to claim 1, characterized in that the shift of the rounded integer part contains such a choice of a floating point value that adding the first constant to the floating point value shifts the rounded integer part. 5. A method for decomposing a floating point value into integer and fractional components, including decomposing a floating point value into a plurality of parts, comprising generating a first constant; scaling the first constant with a multiplier to get the second constant; generating a second value by shifting the rounded integer part of the floating-point value; extracting a plurality of mantissa bits from the second value to generate an integer value; extracting a portion of bits from an integer value to generate an integer component. 6. The method according to claim 5, characterized in that the rounded integer part is shifted to the rightmost bits of the mantissa of the floating point value. 7. The method according to claim 5, characterized in that the first constant, the second constant and the floating point value and the second value are floating point numbers. 8. The method according to claim 5, characterized in that the shift of the rounded integer part includes adding a second constant to the floating point value. 9. A method for extracting integer and fractional components from a floating point value, which includes generating the first constant; scaling the first constant to get the second constant; formation of the binary code of the first, second, third and fourth constants in separate registers for processing integers; determination of the address of the pointer to the fifth constant; loading the address of the pointer to the fifth constant in memory; generating a second value by shifting the rounded integer part of the floating-point value; extracting a plurality of mantissa bits from the second value to generate an integer value; extracting a portion of bits from an integer value to generate an integer component. 10. The method according to claim 9, characterized in that the rounded integer part is shifted to the rightmost bits of the mantissa of the first value. 11. The method according to claim 9, characterized in that it further comprises creating a representation of the first constant in the first floating-point register; creating a representation of the second constant in the second floating-point register; creating a representation of a scaled third constant in a third floating-point register; creating a fourth constant representation in the fourth floating-point register. 12. The method according to claim 9, characterized in that the first, second, third and fourth constants and the first and second values are floating point numbers. 13. Machine-readable medium with instructions, the execution of which on the machine causes the machine to perform operations, including decomposition of the floating point value into many parts, instructions, the execution of which on the machine leads to the fact that the machine performs operations containing generating the first constant; shifting the rounded integer part of the floating point value to generate a second value; generating a floating point value from the second value by subtracting the first constant from the second value; extracting a plurality of mantissa bits from a second value; generating a residual value from a floating point value; extracting a portion of the bits from the plurality of mantissa bits to generate an integer component, where the floating point value, residual value, and integer component are stored in memory and transferred to an arithmetic logic unit (ALU). 14. Machine-readable medium according to item 13, wherein the rounded integer part is shifted to the rightmost bits of the mantissa floating-point values. 15. Machine-readable medium according to item 13, wherein the floating point value, the first constant and the second value are floating point numbers. 16. A machine-readable medium with instructions, the execution of which on the machine causes the machine to perform operations, including decomposition of the floating point value into many parts, commands, the execution of which on the machine leads to the fact that the machine performs operations containing generating the first constant; scaling the first constant to get the second constant; generating a second value by shifting the rounded integer part of the floating-point value; extracting a plurality of mantissa bits from the second value to generate an integer value; extracting a portion of bits from an integer value to generate an integer component. 17. The machine-readable medium of claim 16, wherein the rounded integer part is shifted to the rightmost bits of the mantissa of the floating point value. 18. Machine-readable medium according to claim 17, wherein the first and second constants, the floating point value and the second value are floating point numbers. 19. Machine-readable medium with instructions whose execution on the machine causes the machine to perform operations including generating a first constant; generating a second constant by scaling the first constant; formation of the binary code of the first, second, third and fourth constants in separate registers for processing integers; determination of the address of the pointer to the fifth constant; loading the address of the pointer to the fifth constant in memory; generating a second value by shifting the rounded integer part of the floating-point value; generating a floating point value from the second value by subtracting the constant; extracting a plurality of mantissa bits from the second value to generate an integer value; extracting part of the bits from an integer value to obtain an integer component; generating a residual value from a floating point value; storage of residual value, integer component and floating point value in memory. 20. Machine-readable medium according to claim 19, characterized in that the rounded integer part is shifted to the rightmost bits of the mantissa of the floating point value. 21. Machine-readable medium according to claim 19, characterized in that it further comprises instructions whose execution on the machine causes the machine to perform operations including creating a representation of the first constant in the first floating-point register; creating a representation of the second constant in the second floating-point register; creating a representation of a scaled third constant in a third floating-point register; creating a fourth constant representation in the fourth floating-point register. 22. Machine-readable medium according to claim 19, characterized in that the first, second, third and fourth constants, the first, second and third values are floating point numbers. 23. A computing device comprising a processor having a computing component; a bus connected to the processor; memory connected to the processor; many arithmetic logic devices (ALU) connected to the processor; a plurality of sets of registers connected to a plurality of ALUs, where the computational component generates the first constant, generates the second value by shifting the rounded integer part of the floating point value, generates a floating point value by subtracting the first constant from the floating point value, extracts the many mantissa bits from the second value to generate an integer value, generates a residual value from a floating-point value, extracts part of the bits from an integer value in order to obtain an integer ponents, stores the residual value, the integer component, and the floating-point value in memory. 24. The device according to item 23, wherein the rounded integer part is shifted to the rightmost bits of the mantissa floating-point values. 25. The device according to item 23, wherein the floating point value, the first and second constants and the second value are floating point numbers.

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