JPS6043827A - Formation of fine pattern - Google Patents
Formation of fine patternInfo
- Publication number
- JPS6043827A JPS6043827A JP58151947A JP15194783A JPS6043827A JP S6043827 A JPS6043827 A JP S6043827A JP 58151947 A JP58151947 A JP 58151947A JP 15194783 A JP15194783 A JP 15194783A JP S6043827 A JPS6043827 A JP S6043827A
- Authority
- JP
- Japan
- Prior art keywords
- film
- etched
- etching
- resist film
- organic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/004—Photosensitive materials
- G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
- G03F7/094—Multilayer resist systems, e.g. planarising layers
Landscapes
- Engineering & Computer Science (AREA)
- Architecture (AREA)
- Structural Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は光線、電子ビームなどに感応する感応性レジ
スト膜を用いて微細パターンを形成する方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of forming fine patterns using a sensitive resist film that is sensitive to light, electron beams, and the like.
半導体集積回路装置などの製造工程においては、半導体
基板の主面上にエツチングによって微細パターンを形成
すべきポリシリコン膜などの被エツチング膜を形成し、
この被エツチング膜の表面上に、光線、X線、電子ビー
ムまたはイオンビームに感応する感応性レジストをスピ
ンナ法などで塗布しベーキングして感応性レジスト膜を
成膜したのちに、この感応性レジスト膜の被エツチング
膜の微細パターンを形成すべき部分上の部分が残るよう
に、この感応性レジスト膜に光線、X線、電子ビーム筐
たはイオンビームを照射し現像してエツチングマスク用
レジスト膜を形成し、このレジスト膜をマスクとして被
エツチング膜にエツチングを施して被エツチング膜の微
細パターンを形成する工程がある。In the manufacturing process of semiconductor integrated circuit devices, etc., a film to be etched, such as a polysilicon film, on which a fine pattern is to be formed by etching is formed on the main surface of a semiconductor substrate.
A sensitive resist that is sensitive to light, X-rays, electron beams, or ion beams is coated on the surface of this film to be etched using a spinner method and baked to form a sensitive resist film. This sensitive resist film is irradiated with light, X-rays, electron beams, or ion beams and developed to form a resist film for an etching mask so that the portion of the film to be etched on which the fine pattern is to be formed remains. There is a step of forming a resist film and etching the film to be etched using this resist film as a mask to form a fine pattern of the film to be etched.
ところで、このような方法では、半導体基板の主面部に
段差かある場合には、この半導体基板の主面上に形成さ
れる被エツチング膜の表面部にも半導体基板の工面部に
おける段差と同様の段差ができる。しかし、この段差の
ある被エツチング膜の表面上にスピンナ法などで形成さ
れる感応性レジスト膜の表面は平坦になるので、この感
応性レジスト膜の被エツチング膜の段差の上面側の部分
の膜厚は段差の下面側の部分の膜厚より薄くなる。By the way, in such a method, if there is a step on the main surface of the semiconductor substrate, the surface of the film to be etched formed on the main surface of the semiconductor substrate also has a step similar to the step on the cut surface of the semiconductor substrate. There will be a step. However, since the surface of the sensitive resist film formed by a spinner method or the like on the surface of the film to be etched that has a step becomes flat, the film on the upper surface side of the step of the sensitive resist film of the film to be etched is The thickness is thinner than the film thickness on the lower surface side of the step.
従って、膜厚の薄い部分と膜厚の厚い部分とがある感応
性レジメ)JIkによって微細パターンのエツチングマ
スク用レジスト膜を精度よく形成することは容易ではな
いという問題があった。Therefore, there is a problem in that it is not easy to accurately form a resist film for an etching mask with a fine pattern using the sensitive regime (JIk), which has a thin part and a thick part.
このような問題を解決するために、三層レジストプロセ
スと呼ばれる方法が提案されている。In order to solve these problems, a method called a three-layer resist process has been proposed.
第1図(A)〜(F)は従来の三層レジストプロセスの
一例の主要段階の状態を示す断面図である。FIGS. 1A to 1F are cross-sectional views showing the main stages of an example of a conventional three-layer resist process.
まず、第1図(A)に示すように、半導体基板[++の
主面上に被エツチング膜(2)を形成したのちに、被エ
ツチング膜(2)の表面上にフォトレジストなどの有機
物の塗布液をスピンナ法などで塗布しベーキングして有
機膜(3)を成膜する。次いで、有機膜(3)の表面上
に酸化シリコン膜などの中間膜(4)をCVD法などで
形成し、更に、中間膜(4)の表面上に光線。First, as shown in FIG. 1(A), a film to be etched (2) is formed on the main surface of a semiconductor substrate [++], and then an organic material such as a photoresist is deposited on the surface of the film to be etched (2). A coating liquid is applied using a spinner method or the like and baked to form an organic film (3). Next, an intermediate film (4) such as a silicon oxide film is formed on the surface of the organic film (3) by CVD or the like, and then a light beam is applied onto the surface of the intermediate film (4).
X線、電子ビームまたはイオンビームに感応する感応性
レジストをスピンナ法などで塗布リベーキングして感応
性レジスト膜(5)を成膜する。A sensitive resist film (5) sensitive to X-rays, electron beams, or ion beams is coated and rebaked using a spinner method or the like to form a sensitive resist film (5).
次に、第1図(B)に示すように、感応性レジスト膜(
5)の被エツチング膜(2)の微細パターンを形成すべ
き部分に対応する部分が残るように、感応性レジスト膜
(5)に光KQ + ””X K9 +電子ビーム甘た
はイオンビームを照射し現像して中間膜(4)の表面上
にエツチングマスク用しジス) Mk (5a)を形成
する。Next, as shown in FIG. 1(B), a sensitive resist film (
The sensitive resist film (5) is exposed to light KQ + "" By irradiating and developing, an etching mask (Mk) (5a) is formed on the surface of the intermediate film (4).
次に、第1図(C)に示すように、レジスト膜(5a)
をエツチングマスクとして中間膜(4)にエツチングを
施してレジストIlu (5a)の下に中間11M (
4a)を残す。Next, as shown in FIG. 1(C), a resist film (5a) is formed.
The intermediate film (4) is etched using the etching mask as an etching mask, and the intermediate film (11M) is etched under the resist Ilu (5a).
4a) remains.
次に、第1図(D)に示すように、レジスト膜(5a)
および中間膜(4a)をエツチングマスクとして、有機
膜(3)にロタ素(02)のプラズマによる異方性エツ
チングを施して中間膜(4a)の下に有機膜(3a)を
残す。Next, as shown in FIG. 1(D), a resist film (5a) is formed.
Using the intermediate film (4a) as an etching mask, the organic film (3) is subjected to anisotropic etching using rota element (02) plasma to leave the organic film (3a) under the intermediate film (4a).
体に、第1図(E)に示すように、レジスト膜(5a)
+中間膜(4a)および有機膜(3a)をエツチングマ
スクとして被エツチング膜(2)にエツチングを施して
有機膜(3a、)の下に被エツチング膜(2a)を残す
。As shown in FIG. 1(E), a resist film (5a) is applied to the body.
+ Using the intermediate film (4a) and the organic film (3a) as etching masks, the film to be etched (2) is etched to leave the film to be etched (2a) under the organic film (3a,).
最後に、第1図(F)に示すように、レジスト膜(5a
)、中間膜(4a)および有機膜(3a)を順次エツチ
ング除去する゛と、この従来例の三層レジストプロセス
の作業が完了する。Finally, as shown in FIG. 1(F), a resist film (5a
), the intermediate film (4a) and the organic film (3a) are sequentially etched away, completing the work of this conventional three-layer resist process.
この従来例の三層レジストプロセスでは、半導体基板+
1+の工面部に段差があり、被エツチング膜(2)の表
面部に段差がある場合でも、有機膜(3)が被エツチン
グ膜(2)の表面上にスピンナ法などで成膜されるので
、有機膜(3)の表面は平坦になる。従って、有機膜(
3)の平坦な表面上に順次形成される中間膜(4)およ
び感応性レジスト眸(5)の表面も平坦になり、感応性
レジスト膜(5)の膜厚は均一になるので、感応性レジ
スト膜(5)によって微細ノくターンのエツチングマス
ク用レジスト膜(5a)を精度よく形成することができ
る。そして、レジストIlk −(5a)の下に順次形
成される中間膜(4a)、有機膜(3a)および被エツ
チング膜(2a)のノくターンがレジスト膜(5a)の
パターンに対応するノくターンになるので、被エツチン
グ膜(2a)のノ(ターンの微細化を図ることができる
。In this conventional three-layer resist process, the semiconductor substrate +
Even if there is a step on the 1+ surface and there is a step on the surface of the film to be etched (2), the organic film (3) is formed on the surface of the film to be etched (2) by a spinner method or the like. , the surface of the organic film (3) becomes flat. Therefore, the organic film (
The surfaces of the intermediate film (4) and the sensitive resist film (5), which are sequentially formed on the flat surface of 3), also become flat, and the thickness of the sensitive resist film (5) becomes uniform, so that the sensitivity With the resist film (5), a resist film (5a) for an etching mask having fine notches can be formed with high precision. Then, the notches of the intermediate film (4a), organic film (3a), and film to be etched (2a) formed sequentially under the resist Ilk-(5a) correspond to the pattern of the resist film (5a). Since the pattern is a turn, the pattern of the film (2a) to be etched can be made finer.
しかしながら、この従来例のプロセスでは、工程数が非
常に多いという欠点がある上に、中間膜(4a)の除去
が非常に困難であるという欠点もあった。すなわち、中
間膜(4a)が酸化シリコン(S102)#捷たけアル
ミニウム(AL)膜である場合が多く、この場合には、
中間1反(aa)の除去時のエツチングによって半導体
基板(1)が損傷されたり、被エツチングJ[K(2a
)のパターンが劣化したりする。However, this conventional process has the drawback that it requires a very large number of steps, and also has the drawback that it is very difficult to remove the intermediate film (4a). In other words, the intermediate film (4a) is often a silicon oxide (S102) #aluminum (AL) film, and in this case,
The semiconductor substrate (1) may be damaged by etching when removing the intermediate layer (aa), or the etched layer J[K(2a) may be damaged.
) pattern may deteriorate.
この発明は、かかる欠点を除去する目的でなされたもの
で、半導体基板の主面上に形成された被エツチング膜の
表面上に有機膜、中間膜および感応性レジスト膜の三層
膜を形成し、この三層膜を用いて被エツチング膜の微細
パターンを形成する方法において、中間膜を被エツチン
グ膜のエツチング時にエツチング除去可能な材質および
膜厚に設定することによって、被エツチング膜のパター
ンの微細化を図ることができ、しかも半導体基板の損傷
や被エツチング膜のパターンの劣化のおそれのない、工
程数の少ない微細パターンの形成方法を提供するもので
ある。This invention was made with the aim of eliminating such drawbacks, and involves forming a three-layer film of an organic film, an intermediate film, and a sensitive resist film on the surface of a film to be etched formed on the main surface of a semiconductor substrate. In this method of forming a fine pattern on a film to be etched using this three-layer film, the intermediate film is made of a material and has a thickness that can be removed by etching when etching the film to be etched, thereby forming a fine pattern on the film to be etched. The present invention provides a method for forming a fine pattern with a small number of steps, which can reduce the number of etching steps, and is free from damage to a semiconductor substrate or deterioration of a pattern of a film to be etched.
第2図(A)〜(F)はこの発明の一実施例の微細パタ
ーンの形成方法の主要段階の状態を示す断面図である。FIGS. 2A to 2F are cross-sectional views showing the main stages of a method for forming a fine pattern according to an embodiment of the present invention.
まず、第2図(A)に示すように、半導体基板+llの
主面上に帆3〜コμm程度の厚さの祈エツチング膜(2
)を形成したのちに、被エツチング膜(2)の表面上に
感応性レジストとほぼ同一のエツチング速度で除去可能
なポリイミド樹脂などの有機物の塗布液をスピンナ法な
どで塗布しベーキングして1〜3μm程度の厚さの有機
膜(3)を成膜する。次いで、有機膜(3)の表面上に
中間膜(4)をプラズマ0VJ)法捷たは光OVD、法
で成膜する。この中間膜(4)としては、被エツチング
Jlq(2+をエツチングする際にエツチング除去でき
るようにするために、例えば枦エツチング膜(2)がポ
リシリコン膜である場合には、ポリシリコンB餡オたけ
ポリシリコン月にとほぼ同一のエツチング速度で除去可
能なアモルファスシリコン膜にし、その膜厚は被エツチ
ング月莫(2)の膜厚より薄くなるように設定する。し
かるのち、中間膜(4)の表面上に光線、X線、電子ビ
ームまたはイオンビームに感応する感応性レジストをス
ピンナ法などで塗布しベーキングして有機膜(3)の厚
さより薄い0.2・−0,4μm程度の厚さの感応性レ
ジスト膜(5)を成膜する。First, as shown in FIG.
), on the surface of the film to be etched (2), a coating liquid of an organic material such as a polyimide resin that can be removed at almost the same etching speed as the sensitive resist is applied using a spinner method, and baked. An organic film (3) with a thickness of about 3 μm is formed. Next, an intermediate film (4) is formed on the surface of the organic film (3) by plasma 0VJ) or optical OVD. As this intermediate film (4), in order to be able to remove the etching target Jlq (2+) by etching, for example, when the etching film (2) is a polysilicon film, a polysilicon B bean paste is used. An amorphous silicon film that can be removed at approximately the same etching rate as the polysilicon layer is formed, and its thickness is set to be thinner than that of the polysilicon layer (2).Then, the intermediate film (4) is formed. A sensitive resist that is sensitive to light, X-rays, electron beams, or ion beams is coated on the surface of the film using a spinner method, etc., and baked to a thickness of approximately 0.2 to -0.4 μm, which is thinner than the thickness of the organic film (3). A sensitive resist film (5) is formed.
次に、ゐ52図(B)に示すように、感応性レジスト族
(5)の被エツチングJli+i[2iの微細パターン
を形成スべき部分に対応する部分が残るように、感応性
レジスト月晃[5iにブ0糸ハXか呆、電子ビーム廿た
はイオンビーム奈照射し現像して中間膜(4)の表面上
にエツチングマスク用レジスト膜(58、)を形成する
。Next, as shown in FIG. 52(B), the sensitive resist tsukkou [ A resist film (58) for an etching mask is formed on the surface of the intermediate film (4) by irradiating the resist film 5i with an electron beam or an ion beam and developing it.
次に、第2図(0)に示すように、レジスト膜(5a)
をエツチングマスクとして、フレオン115 (C2G
tF5)のプラズマによる異方性エツチングを中間膜(
4)に施してレジスト膜(5a)の下に中間膜(4a)
を残す。Next, as shown in FIG. 2(0), a resist film (5a) is formed.
as an etching mask, Freon 115 (C2G
Anisotropic etching with plasma of tF5) is applied to the interlayer film (
4) to form an intermediate film (4a) under the resist film (5a).
leave.
次に、第2図(D)に示すように、中間膜(4a)をエ
ツチングマスクとして、有機膜(3)に02のプラズマ
による異方性エツチングを施して中間Jli(aa)の
下に有機膜(3a)を残す。このとき、レジスト膜(5
a)の厚さは有機膜(3a)の厚さより薄いので、レジ
スト膜(5a)はエツチング除去される。Next, as shown in FIG. 2(D), using the intermediate film (4a) as an etching mask, the organic film (3) is subjected to anisotropic etching using 02 plasma to form an organic layer under the intermediate Jli(aa). Leave the membrane (3a) behind. At this time, the resist film (5
Since the thickness of a) is thinner than the thickness of the organic film (3a), the resist film (5a) is removed by etching.
次に、第2図(E)に示すように、有様膜(3a)をエ
ツチングマスクとして、フレオン115(1:!207
F5)のプラズマによる異方性エツチングを被エツチン
グ膜(2)に施して有機膜(3a)の下に被エツチング
膜(2a)を残す。このとき、被エツチング膜(2)か
ポリシリコン膜である場合には、中間膜(4a)はポリ
シリコン膜またはアモルファスシリコン膜であり、中間
膜(4a)の膜厚は被エツチングII!(2iの膜厚よ
り薄いので、中間膜(4a)はエツチング除去される0
最後に、第2図(F)に示すように、有機膜(3a)を
0□のプラズマによるエツチングで除去すると、この実
施例の方法の作業が完了する。Next, as shown in FIG. 2(E), using the patterned film (3a) as an etching mask, Freon 115 (1:!207
The film to be etched (2) is subjected to anisotropic etching using the plasma of F5) to leave the film to be etched (2a) under the organic film (3a). At this time, when the film to be etched (2) is a polysilicon film, the intermediate film (4a) is a polysilicon film or an amorphous silicon film, and the thickness of the intermediate film (4a) is that of the film to be etched II! (Since it is thinner than the film thickness of 2i, the intermediate film (4a) is removed by etching.
Finally, as shown in FIG. 2(F), the organic film (3a) is removed by etching with 0□ plasma to complete the process of this embodiment.
この実施例の方法では、第1図に示した従来例と同様に
、半導体基板il+の王面部に段差があり、被エツチン
グ膜(2)の表面部に段差がある場合でも、有機膜(3
)の表面が平坦になり、この有機膜(3)の表面上に1
@次形成される中間膜(4)および感応性レジヌト膜(
5)の膜厚が均一になるので、この感応性レジスト膜(
5)によって微細パターンのエツチングマスク用レジス
ト膜(5a)を精度よく形成することができる。In the method of this embodiment, as in the conventional example shown in FIG.
) becomes flat, and 1 is deposited on the surface of this organic film (3).
@ Next formed interlayer film (4) and sensitive resin film (
Since the film thickness of 5) becomes uniform, this sensitive resist film (
5) makes it possible to form a resist film (5a) for an etching mask with a fine pattern with high precision.
そして、中間膜(4a)、有機膜(3a)および被エツ
チング1(2a)のパターンがレジスト膜(5a)のパ
ターンに対応するパターンになるので、禎エツチング膜
(2a)のパターンの微細化を図ることができる。しか
も、中間膜(4a)が被エツチング膜(2)とほぼ同一
のエツチング速M+−で除去可能な材質で構成されてお
り、その上レジスト膜(5a)の膜厚がレジストIIU
(5a)とほぼ同一のエツチング速1隻で除去可能な
有機膜(3)の膜厚より薄く設定され、中間膜(4a)
の膜厚が中間膜(4a)とほぼ同一のエツチング速度で
除去可能な被エツチング膜(2)の膜厚より薄く設定さ
れているので、レジスト膜(5a)および中間膜(4a
)はそれ・それ有機膜(3a)および被エツチング膜(
2a)の形成時のエツチングによって自動的にエツチン
グ除去される。従って、最終段階において有機膜(3a
)のみをエツチング除去すればよいので、半導体基板m
を損傷させたり、被エツチング膜(2a)のパターンを
劣化させたりするおそれがなく、工程数を第1図に示し
た従来例の工程数より少7.r、くすることができる。Since the patterns of the intermediate film (4a), organic film (3a), and etching target 1 (2a) correspond to the pattern of the resist film (5a), the pattern of the etching film (2a) can be made finer. can be achieved. Moreover, the intermediate film (4a) is made of a material that can be removed at approximately the same etching speed M+- as the film to be etched (2), and the thickness of the resist film (5a) is that of the resist IIU.
The thickness of the intermediate film (4a) is set to be thinner than that of the organic film (3), which can be removed with one etching speed at approximately the same etching speed as (5a).
The film thickness of the resist film (5a) and the intermediate film (4a) is set to be thinner than that of the film to be etched (2), which can be removed at approximately the same etching speed as the intermediate film (4a).
) is the organic film (3a) and the film to be etched (
It is automatically etched away by etching during the formation of 2a). Therefore, in the final stage, the organic film (3a
) only need to be removed by etching, so the semiconductor substrate m
There is no risk of damaging the film or deteriorating the pattern of the film to be etched (2a), and the number of steps is smaller than that of the conventional example shown in FIG. r, can be reduced.
この実施例において、感応性レジスト膜(5)、中間膜
(4)および有機膜(3)のいずれか一つ祉たは全部に
感応性レジスト膜(5)を感応させる光線、XtX。In this embodiment, a light beam, XtX, is used to sensitize any one or all of the sensitive resist film (5), the intermediate film (4), and the organic film (3) to the sensitive resist film (5).
電子ビームまたはイオンビームを吸収可能な色素などの
添加物を混入捷たは化合させて、半導体基板+1+から
の光線もしくはX線の反射せたは電子ビームもしくはイ
オンビームの後方散乱による悪影響を減らすようにして
もよい。Additives such as dyes that can absorb electron beams or ion beams are mixed or combined to reduce the negative effects of reflection of light or X-rays from the semiconductor substrate +1+ or backscattering of electron beams or ion beams. You can also do this.
ン;仁お、この実施例では、被エツチング膜(2)がポ
リシリコン膜である場合を例示したが、この発明はこれ
に限らず、有機膜(3)&こ対するエツチングとは異な
るエツチングによって除去し得るAtk 、 5in2
膜などのその他の被膜である場合にも適用することがで
きる。In this example, the film to be etched (2) is a polysilicon film, but the present invention is not limited to this. Removable Atk, 5in2
It can also be applied to other coatings such as membranes.
また、この実施例では、有機膜(3)のエツチングに0
2のプラズマを用いたが、必ずしもこれは0゜のプラズ
マである必要がなく、02とOF4.0C14などのハ
ロゲン化合物との混合ガスのプラズマを用いてもよく、
この場合には有機膜(3)に対するエツチング速度を大
きくすることができる。In addition, in this example, the etching of the organic film (3) was carried out at zero
2 plasma was used, but this does not necessarily have to be a 0° plasma, and a mixed gas plasma of 02 and a halogen compound such as OF4.0C14 may be used.
In this case, the etching rate for the organic film (3) can be increased.
この実施例では、レジスト膜(5a)が有機膜(3)へ
のエツチング時にエツチング除去されるようにしたが、
必ずしも有機膜(3)へのエツチング時にエツチング除
去されるようにする必要はない。In this example, the resist film (5a) was etched away when etching the organic film (3).
It is not necessary that the organic film (3) be etched away when etching the organic film (3).
以上、説明したように、この発明の微細パターンの形成
方法においては、半導体基板の主面上に形成された被エ
ツチング膜の表面上に有1L中間月戻および感応性レジ
スト膜の三層膜を形成し、この三層ル4を用いて被エツ
チング膜の微細パターンを形成するので、半導体基板の
主面部に段差があり、被エツチング膜の表面部Gこ段差
がある場合でも、有機j挨の表面が平坦になり、この有
機膜の表面上に順次形成される中間膜および感応性レジ
スト膜の膜厚が均一になる。従って、この感応性レジス
ト膜によって微細パターンのエツチングマスク用しシス
)IINを精度よく形成することができるので、このエ
ツチングマスク用レジスト膜のパターンをエツチングに
よって順次下層に転写して最終的に形成される被エツチ
ング膜のパターンの微fill化を図ることができる。As explained above, in the method for forming a fine pattern of the present invention, a three-layer film of a 1L intermediate resist film and a sensitive resist film is formed on the surface of a film to be etched formed on the main surface of a semiconductor substrate. Since the three-layer rule 4 is used to form a fine pattern on the film to be etched, even if there is a step on the main surface of the semiconductor substrate and a step on the surface of the film to be etched, the organic The surface becomes flat, and the thicknesses of the intermediate film and sensitive resist film that are successively formed on the surface of this organic film become uniform. Therefore, it is possible to form a micropatterned etching mask (cis)IIN with high accuracy using this sensitive resist film, so that the pattern of this etching mask resist film is sequentially transferred to the lower layer by etching and is finally formed. The pattern of the film to be etched can be made finer.
しかも、中間版を被エツチング膜のエツチング時にエツ
チング除去可能な材質および膜厚に設定するので、中■
]股がエツチングマスク用レジスト膜のパターンの被エ
ツチング膜への転写時のエツチングによって自動的に除
去されるので、半導体基板の損傷や扱エツチング膜のパ
ターンの劣化のおそれが少すくすり、工程数を従来例の
工程数より少なくすることができる。Moreover, since the intermediate plate is made of a material and has a film thickness that can be removed by etching when etching the film to be etched,
] Since the crotch is automatically removed by etching when the pattern of the resist film for the etching mask is transferred to the film to be etched, there is little risk of damage to the semiconductor substrate or deterioration of the pattern of the etched film being handled, and the number of steps is reduced. can be made smaller than the number of steps in the conventional example.
第1図は従来の三層レジストプロセスの一例の主要段階
の状態を順次示す断面図、輿2図はこの発明の一実施例
の微細パターンの形成方法の主要段階の状態を順次示す
断面図である。
図において、(1)は半導体基板、(2)および(2a
)は被エツチング膜、(3)および(3a)は南機欣、
(4)オよび(4a)は中間膜、t51は感応性レジメ
)肋、(5a)はエツチングマスク用レジスト膜である
。
なお、図中同一符号はそれぞれ同一またをま相当部分を
示す。
代理人 大 岩 増 雄
(C)
(E、)
(F)
(F)
手続補正書(自発)
特許庁長官殿
1、事件の表示 特願昭58−151947号2 、
’zl ’!JJ (’) 名f’示 微細パターンの
形成方法3、補正をする者
5、 補正の対象
明細書の発明の詳細な説明の欄
6、 補正の内容
(ll 明細書の第4頁第1行に「平坦」とあるのを「
比較的平坦」と訂正する。Figure 1 is a cross-sectional view sequentially showing the main stages of an example of a conventional three-layer resist process, and Figure 2 is a cross-sectional view sequentially showing the main stages of a fine pattern forming method according to an embodiment of the present invention. be. In the figure, (1) is a semiconductor substrate, (2) and (2a
) is the film to be etched, (3) and (3a) are the films to be etched,
(4) O and (4a) are interlayer films, t51 is a sensitive regimen rib, and (5a) is a resist film for an etching mask. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (C) (E,) (F) (F) Procedural amendment (voluntary) Commissioner of the Japan Patent Office1, Indication of case Patent application No. 151947/19822,
'zl'! JJ (') Name f' Indication Method for forming fine patterns 3, Person making the amendment 5, Detailed explanation of the invention in the specification subject to amendment 6, Contents of the amendment (ll Page 4, line 1 of the specification The word "flat" is replaced by "
"It's relatively flat," he corrected.
Claims (1)
膜の表面上に順次有機膜、中間膜および感応性レジスト
膜を形成し、上記感応性レジスト膜の上記被エツチング
膜の微細パターンを形成すべき部分上の部°分か残るよ
うに上記感応性レジスト膜を感応させ現像してエツチン
グマスク用レジスト膜を形成し、上記エツチングマスク
用レジスト膜のパターンをエツチングによって順次下層
に転写して最終的に上記被エツチング膜の微細パターン
を形成する方法において、上記中間膜を上記被エツチン
グ膜のエツチング時にエツチング除去可能な材質および
膜厚に設定することを%、徴とする微細パターンの形成
方法。 (2)感応性レジスト膜を感応させる光線、X線。 電子ビームまたはイオンビームを吸収可能な添加物が混
入または化合された中間膜を用いることを特徴とする特
許請求の範囲第1項記載の微細パターンの形成方法。 (3)感応性レジスト膜を感応させる光線、X線。 電子ビームまたはイオンビームを吸収可能な添加物が混
入寸たは化合された有機膜を用いることを特徴とする特
許請求の範囲第1項捷たけ第2項記載の微細パターンの
形成方法。 (4)感応性レジスト膜を感応させる光線、X線。 電子ビームまたはイオンビームを吸収可能な添加物が混
入または化合された感応性レジスト膜を用いることを特
徴とする特許請求の範囲第1項ないし第3項のいずれか
に記載の微細パターンの形成方法。[Claims] +11 An organic film, an intermediate film, and a sensitive resist film are sequentially formed on the surface of a film to be etched formed on the main surface of a semiconductor substrate, and the film to be etched is formed on the sensitive resist film. The sensitive resist film is sensitized and developed to form a resist film for an etching mask so that a portion above the portion where a fine pattern is to be formed remains, and the pattern of the resist film for an etching mask is sequentially etched into the lower layer. In the method of transferring and finally forming a fine pattern of the film to be etched, the fine pattern is characterized in that the intermediate film is made of a material and has a film thickness that can be removed by etching during etching of the film to be etched. How to form. (2) Light rays, X-rays, that sensitize the sensitive resist film. The method for forming a fine pattern according to claim 1, characterized in that an intermediate film mixed with or combined with an additive capable of absorbing an electron beam or an ion beam is used. (3) Light rays, X-rays, that sensitize the sensitive resist film. 2. A method for forming a fine pattern according to claim 1, wherein an organic film mixed with or combined with an additive capable of absorbing an electron beam or an ion beam is used. (4) Light rays or X-rays that sensitize the sensitive resist film. A method for forming a fine pattern according to any one of claims 1 to 3, characterized in that a sensitive resist film mixed with or combined with an additive capable of absorbing an electron beam or an ion beam is used. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58151947A JPS6043827A (en) | 1983-08-20 | 1983-08-20 | Formation of fine pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58151947A JPS6043827A (en) | 1983-08-20 | 1983-08-20 | Formation of fine pattern |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6043827A true JPS6043827A (en) | 1985-03-08 |
JPH0458167B2 JPH0458167B2 (en) | 1992-09-16 |
Family
ID=15529679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58151947A Granted JPS6043827A (en) | 1983-08-20 | 1983-08-20 | Formation of fine pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6043827A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0200477A2 (en) * | 1985-04-26 | 1986-11-05 | Hitachi, Ltd. | Process for pattern formation |
JPS6316623A (en) * | 1986-07-08 | 1988-01-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS63273767A (en) * | 1987-05-06 | 1988-11-10 | 三洋電機株式会社 | Plate type heat exchanger for absorption type water heater and chiller |
JPH0396286A (en) * | 1989-09-08 | 1991-04-22 | Nippon Telegr & Teleph Corp <Ntt> | Formation of patterned oxide superconducting thin film |
JPH03235380A (en) * | 1990-02-13 | 1991-10-21 | Sumitomo Cement Co Ltd | Formation of thin superconducting film pattern |
JPH0792688A (en) * | 1990-02-26 | 1995-04-07 | Applied Materials Inc | Method of multilayer photoresist etching |
JP2002110509A (en) * | 2000-09-27 | 2002-04-12 | Fujitsu Ltd | Method for manufacturing electronic device |
-
1983
- 1983-08-20 JP JP58151947A patent/JPS6043827A/en active Granted
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0200477A2 (en) * | 1985-04-26 | 1986-11-05 | Hitachi, Ltd. | Process for pattern formation |
EP0200477A3 (en) * | 1985-04-26 | 1988-12-28 | Hitachi, Ltd. | Process for pattern formation |
JPS6316623A (en) * | 1986-07-08 | 1988-01-23 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS63273767A (en) * | 1987-05-06 | 1988-11-10 | 三洋電機株式会社 | Plate type heat exchanger for absorption type water heater and chiller |
JPH0396286A (en) * | 1989-09-08 | 1991-04-22 | Nippon Telegr & Teleph Corp <Ntt> | Formation of patterned oxide superconducting thin film |
JPH03235380A (en) * | 1990-02-13 | 1991-10-21 | Sumitomo Cement Co Ltd | Formation of thin superconducting film pattern |
JPH0792688A (en) * | 1990-02-26 | 1995-04-07 | Applied Materials Inc | Method of multilayer photoresist etching |
JP2002110509A (en) * | 2000-09-27 | 2002-04-12 | Fujitsu Ltd | Method for manufacturing electronic device |
Also Published As
Publication number | Publication date |
---|---|
JPH0458167B2 (en) | 1992-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6323657B2 (en) | ||
JPS6043827A (en) | Formation of fine pattern | |
JPH09218500A (en) | Manufacture of resist patterns | |
JPH0463349A (en) | Photomask blank and photomask | |
US20050244721A1 (en) | Composite layer method for minimizing PED effect | |
WO1983003485A1 (en) | Electron beam-optical hybrid lithographic resist process | |
US20050130069A1 (en) | Resist pattern forming method | |
JPH0319540B2 (en) | ||
JP2666420B2 (en) | Method for manufacturing semiconductor device | |
JPS61271838A (en) | Manufacture of semiconductor device | |
JPS6331135A (en) | Manufacture of semiconductor device | |
JPS6074521A (en) | Pattern forming process | |
JPS61131446A (en) | Formation of resist pattern | |
JPS59195824A (en) | Formation of wiring | |
JPH03104113A (en) | Formation of resist pattern | |
JPS61263219A (en) | Forming method of resist pattern | |
JPS5912437A (en) | Formation of resist pattern | |
JPS5968744A (en) | Manufacture of photomask | |
JPS60106132A (en) | Formation of pattern | |
JPS60142516A (en) | Manufacture of semiconductor device | |
JPH01258420A (en) | Protection of mark | |
JPS63160224A (en) | Manufacture of semiconductor device | |
JPS63160225A (en) | Manufacture of semiconductor device | |
JPS61213846A (en) | Pattern forming method | |
JPS59155936A (en) | Forming method of minute pattern |