JPS6043590B2 - associative memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an associative memory device, particularly an M bits×N words×I memory device that uses a plurality of memory elements composed of m bits×n words that can read or write m bits simultaneously. In an associative level associative memory device, even if one memory element fails and all the contents of that memory element are destroyed, the error caused by the failure is only a 1-bit error. It is related to the device.

In general, an M-bit x N-word storage device is constructed using a plurality of m-bit x n-word storage elements 1 that can read or write m bits at the same time, as shown in FIG. In this type of storage device, SEC-DED (1-bit error correction/2-bit error detection code) is normally used as an error correction method. However, the above SEC-D
When an ED is used, for example, if a failure occurs in one memory element 1, all the contents of the failed memory element 1, that is, m bits x n words, are destroyed and an m bit error occurs. If is an integer value of 3 or more, the error detection function and error correction function cannot be fully performed. On the other hand, it is conceivable to use an adjacent bit error correction code as an error correction method. However, when using this type of adjacent bit error correction code, an extremely large amount of hardware is required for error correction code generation processing and error detection/correction processing, and the processing time increases. For this reason, it is inappropriate to use the above-mentioned adjacent bit error correction code in an associative memory device that performs high-speed processing. In view of the above points, a storage device as illustrated in FIG. 2 is considered.

The storage device shown in FIG. 2 uses the individual storage elements 1 shown in FIG. It is composed of In this type of storage device, if one storage element 1' fails, the failed storage element 1'
Even if all the contents of ' are destroyed, only one bit of the M-bit word information is affected by the failure, and the error correction/detection function of SEC-DED described above can be fully demonstrated. . FIG. 3 shows the application of the above-mentioned 1 bit x (m x n) word memory element 1' to an associative memory device consisting of M bits x IK words x 4 associative levels according to the method described in FIGS. 1 and 2. An example is shown below.

In the figure, 1' is a 1 bit x 4 word storage element, 2-1, 2
-2, 2-3, and 2-4 each represent blocks (hereinafter referred to as associative blocks) corresponding to one associative level. In FIG. 3, for example, when a read process is performed on an associative memory device, when the P-th address is specified, the above-mentioned The information on the address corresponding to the P address, that is, the four word information in each area 3-1, 3-2, 3-3, and 3-4 is read out at once.

For example, one word information in each area 4-1, 4-2, 4-3, 4-4 is not selected from among the four word information read out. In this way, for a certain address specification,
Only one piece of information is used in each associative block 2-1, 2-2, 2-3, 2-4, and the remaining three word information are never used. That is, each associative block 2-1, 2-2
, 2-3, and 2-4, only 1/4 area is used for storing information, and the remaining 3/4 area is wasted. The present invention aims to solve the above-mentioned problems and provides an associative memory device that can use SECeDED as an error correction method and use the entire storage area as an effective storage area.

Therefore, the associative memory device of the present invention is an M bits x N words x I associative level associative memory device that uses a plurality of memory elements each consisting of m bits x n words that can read or write m bits at the same time. The above memory elements are arranged to have 1 bit x n words x m associative levels, and M bits x
It is characterized by being structured into N words x 1 association level. The present invention will be explained below with reference to FIGS. 4 and 5. FIG. 4 shows the structure of an embodiment of the associative memory device according to the present invention, and FIG. 5 shows a wiring state for the memory elements in FIG. 4.

In FIG. 4, 5 is a main memory device consisting of A column x B set, and 6 is a tag part of an associative memory device, such as a buffer memory device, which is composed of M bits x N words x 1 associative level. 7-1, 7-2, 7-3...
7-M are storage elements each composed of 1 bit x n words x m association levels, 8-1, 8-2, 8-3...
8-M,9-,1,9-2,9-3,9-MllO-1
,10-2,10-3,・10-Mlll-1,11
-2, 11-3, 11-M are each 1 bit storage area, 1
2 is a decoder, 13 is an address register in which address information is set, 14-1, 14-2, 14
-3 and 14-4 represent comparison circuits, respectively.

M bits x N words x 1 The tag part 6 of the associative ν bell is 1 bit x
Memory elements 7-1, 7-2, 7-3 of n words x m association level
, 7-M are arranged as shown in the figure.

In the case of the figure, a configuration is shown where N=n and I=m=4, where n is, for example, 1K. Also, a storage area (temporarily referred to as a unit information storage area) consisting of 1-bit storage areas 8-1 to J8-M, a unit information storage area consisting of 1-bit storage areas 9-1 to 9-M, 1-bit storage A unit information storage area consisting of areas 10-1 to 10-M and a 1-bit storage area 11-1. Ishi 11-M
Each unit information storage area consists of main storage device 5.
For example, set number information of the main memory device 5 corresponding to the unit block belonging to the #e column and transferred and stored in the data section (not shown) of the buffer memory device is stored. An example of the processing operation will be described below using a read operation as an example. Address◆When address information is set in the register 13, the column number information of the set address information is decoded by the decoder 12, and the corresponding address of the tag section 6 is designated.

For example, if the specified address is an address corresponding to the #e column of the main storage device 5 as described above, each unit information storage area 8-1 to 8-Ml9-1 to 9-MllO belonging to the address -1 to 101Mll-1 to 11-M are simultaneously read out and input to comparison circuits 14-1, 14-2, 14-3, and 14-4. Comparing circuits 14-1, 14-2, 14-3, and 14-4 receive the set number information and address read from the tag unit 6, respectively. The set number information in the register 13 is compared.
When a comparison is found, the desired data is read from the storage area of the data section corresponding to the set number information. On the other hand, if a comparison match is not obtained, it is determined that the desired data does not exist on the buffer memory device, and the desired data is transferred to the buffer memory device.
An update process for storing is performed. As shown in FIG. 4, each of the memory elements 7-1, 7-2, 7-3, and 7-M stores at most 1 bit of information constituting unit information, that is, set number information. It is.

Therefore, if one memory element 7-1, 7-2, 7-3,
Even if 71M fails and all contents are destroyed, the only error caused by the failure will be a 1-bit ● error. Therefore, the error correction and detection functions of SEC●DED can be fully utilized. Furthermore, since the N words in the tag section 6 and the number of columns in the main memory 5 can be made equal, the entire storage area in the tag section 6 can be used for storing set number information. FIG. 5 is a conceptual diagram, and the memory elements 7-1, 7-2, 7- in FIG.
3, shows an example configuration specifically expressing 7-M.

In the figure, 7 is a memory element, 15-1, 15-2, 15-3,
15-4 is a 1 bit×n word block, ADR is an address information input terminal, WE is a write enable signal input terminal, WD is a write information input terminal, TA is a block selection signal input terminal, and RD is a read information output terminal. It represents. When performing information write processing, address information, write enable signal, 1-bit write information, and block selection signal are input to input terminals ADR, WE, WD, and B, respectively.
Let S input the information.

As a result, 1 bit x n word blocks 15-1, 15-2
, 15-3, and 15-4, the 1 bit x n word block indicated by the block selection signal is selected, and the bit information is stored at the address indicated by the address information in the selected 1 bit x n word block. is written. On the other hand, when performing information read processing, address information is input to the address information input terminal ADR. As a result, each 1 bit x n word block 15-1, 15-2, 15-3, 1
1 within the address indicated by the above address information in 5-4
Bit information is output to read information output terminal RD. As described above, according to the present invention, SEC/DED can be used as an error correction method, and the entire storage area can be used as an effective storage area.

[Brief explanation of drawings]

FIG. 1 is an example of a conventional memory device composed of M bits x N words, FIGS. 2 and 3 are examples of an associative memory device considered prior to the present invention, and FIG. 4 is an associative memory device according to the present invention. FIG. 5 shows an example configuration of a memory device specifically representing the memory element in FIG. 4. In the figure, 6 represents a tag part of an associative memory device, such as a buffer memory device, and 7-1, 7-2, 7-3, and 7-M each represent a storage element of 1 bit x n words x m associative levels.

Claims (1)

[Claims] 1. In an associative memory device of M bits x N words x I associative level that uses a plurality of memory elements each consisting of m bits x n words that can read or write m bits at the same time, the above storage element is 1 bit x n words. An associative memory device characterized in that it is arranged to have words x m associative levels and configured as M bits x N words x I associative levels.