JPS604332A - デコ−ダ型論理演算回路 - Google Patents

デコ−ダ型論理演算回路

Info

Publication number
JPS604332A
JPS604332A JP58110926A JP11092683A JPS604332A JP S604332 A JPS604332 A JP S604332A JP 58110926 A JP58110926 A JP 58110926A JP 11092683 A JP11092683 A JP 11092683A JP S604332 A JPS604332 A JP S604332A
Authority
JP
Japan
Prior art keywords
switch
switch group
exclusive
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58110926A
Other languages
English (en)
Japanese (ja)
Other versions
JPH053769B2 (enExample
Inventor
Makoto Hanawa
花輪　誠
Tadahiko Nishimukai
西向井　忠彦
Yoshiki Noguchi
孝樹 野口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58110926A priority Critical patent/JPS604332A/ja
Publication of JPS604332A publication Critical patent/JPS604332A/ja
Publication of JPH053769B2 publication Critical patent/JPH053769B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/215—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using field-effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP58110926A 1983-06-22 1983-06-22 デコ−ダ型論理演算回路 Granted JPS604332A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58110926A JPS604332A (ja) 1983-06-22 1983-06-22 デコ−ダ型論理演算回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58110926A JPS604332A (ja) 1983-06-22 1983-06-22 デコ−ダ型論理演算回路

Publications (2)

Publication Number Publication Date
JPS604332A true JPS604332A (ja) 1985-01-10
JPH053769B2 JPH053769B2 (enExample) 1993-01-18

Family

ID=14548111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58110926A Granted JPS604332A (ja) 1983-06-22 1983-06-22 デコ−ダ型論理演算回路

Country Status (1)

Country Link
JP (1) JPS604332A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009517980A (ja) * 2005-11-28 2009-04-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド １ステージの遅延による投機的なアドレスデコーダ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244551A (en) * 1975-10-06 1977-04-07 Toshiba Corp Logic circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244551A (en) * 1975-10-06 1977-04-07 Toshiba Corp Logic circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009517980A (ja) * 2005-11-28 2009-04-30 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド １ステージの遅延による投機的なアドレスデコーダ
JP4920044B2 (ja) * 2005-11-28 2012-04-18 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド １ステージの遅延による投機的なアドレスデコーダ

Also Published As

Publication number Publication date
JPH053769B2 (enExample) 1993-01-18

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