JPS6043039B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device having a field effect transistor structure and nonvolatilely storing a difference in gate threshold values as information.

A conventionally known nonvolatile semiconductor memory device of this type is, for example, a transistor.

Its structure is usually as shown in Figure 1. Figure 1a is a schematic plan view, b and c are respectively a(7)I-I'
, ■-■′ cross-sectional view. Here, an example of an n-channel, aluminum gate structure is shown. That is, using a P-type Si substrate 1, a source region 2 and a drain region 3 of n1 thickness are formed on the surface thereof at positions separated from each other, and a gate insulating film 4 is interposed between these regions so as to be made of Al. A gate electrode 5 is provided. The gate insulating film 4 has a double structure of an extremely thin silicon oxide film 4 of about 20 Λ and a silicon nitride film 42 of about 500 Λ so that information can be stored in a non-volatile manner. 6 is a silicon oxide film formed by the CVD method, and 7 is a so-called field insulating film also made of a silicon oxide film or the like.

In this transistor, when a positive voltage is applied to the gate electrode 5 with respect to the substrate 1, electrons that have passed through the silicon oxide film 4 from the substrate 1 due to the tunnel effect are trapped in the silicon nitride film 42.

As a result, the gate threshold value of the transistor changes in the positive direction. Next, when a negative voltage is applied to the gate electrode 5 to the substrate 1, holes are injected, canceling the negative charge in the gate insulating film 4 and changing the gate threshold value in the negative direction. In this way, by selecting the polarity of the voltage applied to the gate electrode, two values can be obtained as the threshold value. Furthermore, even if the power is turned off, the binary information is stored in the form of charges, so it can be used as a nonvolatile memory device. However, such traditional MNOs
The S memory transistor has the following problems.

As is clear from FIG. 1J, since the end face of the field insulating film 7 is normally inclined, the gate electrode 5 is located at the portions A and B where it overlaps the end of the field insulating film 7 on the side of the channel region. , a parasitic MOS transistor with a kind of fixed threshold is formed. Therefore, when the threshold value of the gate region that functions as a gate memory becomes a large positive value, a parasitic MOS transistor with a smaller positive threshold value is connected in parallel to the memory transistor by sharing the source and drain. It enters a state in which, as a whole, it exhibits characteristics with a threshold value determined by the parasitic MOS transistor. This situation is shown in a characteristic diagram as shown in FIG. This figure is 3
Gate voltage in the tube region cm Drain current 1D characteristics, C is the state where the threshold value changes in the negative direction, D is the state where the threshold value changes in the positive direction, and D is the state where the threshold value changes in the positive direction. Broken line portion E due to the parasitic MOS transistor effect mentioned above
appears. For this reason, for example, if the identification current value is 12, the interval between thresholds corresponding to binary information is Δ■2=■
H2-VL2, whereas if the identification current value is 11, the interval becomes ΔV1=VHl-VLl, which clearly becomes ΔV1<ΔV2. That is, when operating in a low current region, the margin of operation is reduced due to the influence of the parasitic MOS transistor at the end of the gate. The present invention provides a semiconductor memory device which eliminates the above-mentioned parasitic MOS transistor effect and provides sufficient operating margin even in a low current region. In a storage device such as an MNOS memory transistor, this invention has a structure in which at least a portion of the gate electrode overlapping with the edge of the field insulating film on the side of the channel is removed, and a parasitic MOS transistor is connected in parallel to the memory transistor. It is characterized by the fact that it prevents it from entering.

An embodiment of this invention is shown in FIG.

This is an embodiment of an n-channel MNOS memory transistor, in which FIG. 3a is a schematic plan view, and FIG. 11 is a p-type Si substrate, 12 is a Gi-type source region, 13 is an n+-type drain region,
14 is a gate insulating film, 15 is a gate electrode, and 16 is a CVD film.
The oxide film 17 is a field insulating film, and the gate insulating film 14 has a two-layer structure of an extremely thin silicon oxide film 141 and a thicker silicon nitride film 142 in order to have memory characteristics.

Its basic structure is the same as the conventional one explained in FIG. The difference from FIG. 1 is that partial notches F and G are provided in the portion where the gate electrode 15 overlaps the end of the field insulating film 17 on the side of the channel.
4 With such a structure, a parasitic MOS transistor is not inserted in parallel with the memory transistor, sharing the source and drain. Therefore, MNOS
Even when the threshold value of the memory transistor is greatly changed in the positive direction, the broken line portion E shown in FIG. 2 does not appear, and sufficient operating margin can be obtained even in the low current region. 4 to 6 are plan views of another embodiment of the invention, corresponding to FIG. 3a.

In FIG. 4, a notch j is provided near the drain in the portion of the gate electrode 15 that overlaps with the edge of the field insulating film. In FIG. 5, the gate electrode 15 is made not to overlap the edge of the field insulating film at all. In FIG. 6, the gate electrode 15 has a pattern similar to that of the conventional example shown in FIG. On the other hand, the gate electrode 15 is prevented from completely overlapping the edge of the field insulating film. These Figure 4~
Similarly to FIG. 3, the structure of FIG. 6 can eliminate the parasitic MOS transistor effect. As described above, according to the present invention, in a memory device such as an MNOS memory transistor, parasitic MOS transistor effects can be eliminated with a simple structure, and sufficient operating margin can be provided even in a low current region.

Although the above explanation has focused on MNOS memory transistors as an example, this invention applies not only to so-called MAOS memory transistors that use alumina in the silicon nitride film, but also to a more complex multilayer gate insulating film structure that improves memory characteristics. The present invention can be similarly applied to a storage device provided with the same device.

[Brief explanation of the drawing]

Figures 1a-c are diagrams showing a conventional MNOS memory transistor, Figure 2 is a diagram showing its gate voltage-drain current characteristics, and Figures 3a-c are East B memory transistors of an embodiment of the present invention. FIGS. 4 to 6 are diagrams showing an east B memory transistor of another embodiment. 11...p-type Si substrate, 12...n-type sous region, 13...n+-type drain region, 1
4...Gate insulating film, 141...Silicon oxide film, 14.

Claims (1)

[Claims] 1. A semiconductor substrate, a source region and a drain region of a conductivity type opposite to that of the substrate provided at positions separated from each other on this substrate, and a memory characteristic provided on the substrate spanning between these source and drain regions. and a gate electrode provided on the insulating film, the gate electrode having a structure in which at least a portion of the gate electrode that overlaps with an end of the field insulating film on the side of the channel region is removed. A semiconductor memory device characterized by: