JPS6043026U - DC clamp circuit - Google Patents
DC clamp circuitInfo
- Publication number
- JPS6043026U JPS6043026U JP13575683U JP13575683U JPS6043026U JP S6043026 U JPS6043026 U JP S6043026U JP 13575683 U JP13575683 U JP 13575683U JP 13575683 U JP13575683 U JP 13575683U JP S6043026 U JPS6043026 U JP S6043026U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- clamp circuit
- buffer circuit
- input
- input buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はダイオードクランプ方式による直流補償回路の
基本構成図、第２図は直流補償回路への入力信号を示す
図、第３図は第２図の入力信号に対するダイオードクラ
ンプ方式による直流補償後の出力信号を示す図、第４図
はダイオードクランプ方式を実現する従来の回路図、第
５図は本考案の直流クランプ回路の構成図、第６図は第
２図の入力信号に対する本考案の回路による直流補償後
の出力信号を示す図、第７図はソース接地形直流増幅器
としてデュアルゲート形のＦＥＴを用いた帰還形直流増
幅器を用いた例を示す図である。
図において１はダイオード、２はキャパシタ、３は入力
バッファ回路、４は出力バッファ回路、５はキャパシタ
２とダイオード１の接続点、２０は過渡的に変化する入
力信号の直流レベル、２１はパルス波形のサグ頁たるみ
）、４０は入力バッファ回路、４１は出力バッファ回路
、４２はバイポーラトランジスタ、４３はベースバイア
スＮ流供給用の抵抗、５０は入力バッファ回路、５１は
ソース接地形直流増幅回路、５２はディプレッション形
の接合形電界効果トランジスタ、５３はキャパシタ、５
４は５０の出力点、５５は５１の入力点、５６はドレイ
ン、５７は電源接続点である。
ｌ
第 ２ 図
’ １１ ４ １３ １４ ｔ５第３図
１ ４ ’２ ’ｊ ’４
１５４０ ４Ｆ −
〆 −どFigure 1 is a basic configuration diagram of a DC compensation circuit using the diode clamp method, Figure 2 is a diagram showing the input signal to the DC compensation circuit, and Figure 3 is a diagram showing the input signal in Figure 2 after DC compensation using the diode clamp method. Figure 4 is a diagram showing the output signal. Figure 4 is a conventional circuit diagram that implements the diode clamp method. Figure 5 is a configuration diagram of the DC clamp circuit of the present invention. Figure 6 is the circuit of the present invention for the input signal of Figure 2. FIG. 7 is a diagram showing an example in which a feedback DC amplifier using a dual gate FET is used as a grounded source DC amplifier. In the figure, 1 is a diode, 2 is a capacitor, 3 is an input buffer circuit, 4 is an output buffer circuit, 5 is a connection point between capacitor 2 and diode 1, 20 is a DC level of a transiently changing input signal, and 21 is a pulse waveform 40 is an input buffer circuit, 41 is an output buffer circuit, 42 is a bipolar transistor, 43 is a resistor for supplying base bias N current, 50 is an input buffer circuit, 51 is a source grounded DC amplifier circuit, 52 5 is a depletion type junction field effect transistor, 53 is a capacitor, and 5 is a depletion type junction field effect transistor.
4 is an output point of 50, 55 is an input point of 51, 56 is a drain, and 57 is a power supply connection point. l Figure 2' 11 4 13 14 t5 Figure 3 1 4 '2 'j '4
1540 4F -〆-do
Claims (1)
ッション形の接合形電界効果トランジスタを用いたリー
ス接地形直流増幅回路と、前記入力バッファ回路の出力
点と前記ソース接地形直流増幅回路の入力点との間に接
続されたキャパシタとから成る直流クランプ回路。an input buffer circuit with low output impedance, a lease grounded DC amplifier circuit using a depletion type junction field effect transistor, and between an output point of the input buffer circuit and an input point of the source grounded DC amplifier circuit. A DC clamp circuit consisting of a connected capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13575683U JPS6043026U (en) | 1983-09-01 | 1983-09-01 | DC clamp circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13575683U JPS6043026U (en) | 1983-09-01 | 1983-09-01 | DC clamp circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6043026U true JPS6043026U (en) | 1985-03-26 |
Family
ID=30305457
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13575683U Pending JPS6043026U (en) | 1983-09-01 | 1983-09-01 | DC clamp circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6043026U (en) |
-
1983
- 1983-09-01 JP JP13575683U patent/JPS6043026U/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| PROC IEEE=1980 * |
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