JPS5988756U - anti-phase summing amplifier - Google Patents
anti-phase summing amplifierInfo
- Publication number
- JPS5988756U JPS5988756U JP18451482U JP18451482U JPS5988756U JP S5988756 U JPS5988756 U JP S5988756U JP 18451482 U JP18451482 U JP 18451482U JP 18451482 U JP18451482 U JP 18451482U JP S5988756 U JPS5988756 U JP S5988756U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- current
- emitter
- impedance circuit
- reference potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来の逆相加算増幅器を示す回路図、第２図
は、本考案の一実施例を示す回路図、第３図は、本考案
の他の実施例を示す回路図、第４図は、本考案の更に他
の実施例を示す回路ブロック図、第５図、第４図の装置
の動作を示す波形図である。
主要部分の符号の説明、３，４・・・・・・電流ミラー
−回路、５・・・・・・バッファアンプ、Ｑ□
＋ Ｑ２＋ Ｑ３＋ Ｑ４＋Ｑ、、 Ｑ６・・・・・・
トランジスタ、Ｒ６，Ｒ７，Ｒ８，Ｒ９゜ＲＩＯ・・・
・・・抵抗、Ｄ工、 Ｄ２． Ｄ３． Ｄ４． Ｄ５・
・・・・・ダイオード。FIG. 1 is a circuit diagram showing a conventional anti-phase summing amplifier, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. FIG. 4 is a circuit block diagram showing still another embodiment of the present invention, and FIGS. 5 and 4 are waveform diagrams showing the operation of the apparatus shown in FIG. Explanation of symbols of main parts, 3, 4...Current mirror - circuit, 5...Buffer amplifier, Q□
+ Q2+ Q3+ Q4+Q,, Q6...
Transistor, R6, R7, R8, R9゜RIO...
...Resistance, D-work, D2. D3. D4. D5・
·····diode.
Claims (2)
ピーダンス回路と、第１人力信号がベースに供給された
第１トランジスタと、前記第１トランジスタのエミッタ
と第２所定基準電位点間に接続された第２インピーダン
ス回路ト、第２人力信号がベースに供給されかつコレク
タが第３所定基準電位点に接続された第２トランジスタ
と、前記第２トランジスタのエミッタと第４所定基準電
位点間に接続された第３インピーダンス回路と、前記第
１トランジスタのコレクタに所定電圧を印加することに
よって該コレクタに流入する電流に応じた電流を前記第
１インピーダンス回路に供給する電流供給手段と、前記
第２トランジスタのエミッタより流出する電流に応じた
電流を前記第１インピーダンス回路から吸込む電流吸込
み手段とを含み、前記第１インピーダンス回路の他端に
おける電位変化を出力信号として導出することを特徴と
する逆相加算増幅器。(1) A first idipedance circuit whose one end is connected to a first predetermined reference potential point, a first transistor whose base is supplied with a first human input signal, and an emitter of the first transistor and a second predetermined reference potential point. a second impedance circuit connected between a second transistor having a base supplied with a second human input signal and a collector connected to a third predetermined reference potential point; and an emitter of the second transistor and a fourth predetermined reference potential point. a third impedance circuit connected between points; and current supply means for supplying a current to the first impedance circuit according to the current flowing into the collector by applying a predetermined voltage to the collector of the first transistor; and current sinking means for sucking a current from the first impedance circuit according to the current flowing out from the emitter of the second transistor, and derives a potential change at the other end of the first impedance circuit as an output signal. anti-phase summing amplifier.
タであり、かつ前記電流吸込み手段は前記第２トランジ
スタのエミッタより流出した電流が供給されるダイオー
ドと、前記ダイオードのアノードにベースが接続された
ＮＰＮ ）ランジスタとからなる電流ミラー回路である
ことを特徴とする実用新案登録請求の範囲第１項記載の
逆相加算増幅器。(2) The second transistor is an NPN transistor, and the current sink means includes a diode to which a current flowing out from the emitter of the second transistor is supplied, and an NPN transistor whose base is connected to the anode of the diode. 2. The anti-phase summing amplifier according to claim 1, which is a current mirror circuit consisting of a current mirror circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18451482U JPS5988756U (en) | 1982-12-06 | 1982-12-06 | anti-phase summing amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18451482U JPS5988756U (en) | 1982-12-06 | 1982-12-06 | anti-phase summing amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5988756U true JPS5988756U (en) | 1984-06-15 |
Family
ID=30399059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18451482U Pending JPS5988756U (en) | 1982-12-06 | 1982-12-06 | anti-phase summing amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5988756U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175353U (en) * | 1988-05-26 | 1989-12-13 |
-
1982
- 1982-12-06 JP JP18451482U patent/JPS5988756U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01175353U (en) * | 1988-05-26 | 1989-12-13 |
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