JPS6042975B2 - Time division data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data transfer between a plurality of devices,
In particular, the present invention relates to a time-division data transfer control method applicable to electronic computers and electronic switching equipment.

Conventionally, in a data transfer control method in a time division system, data transfer time on a common bus is allocated in advance.

For example, in the system shown in FIG. 1, devices 31 and 32 shown in FIG. 2 are connected to a common bus line between clock pulses.
, . . . is the data transfer time on the 3n common bus. This data transfer time is determined in advance by estimating the length of data that will be necessary, and is fixed at a length that matches that length. Therefore, this common bus has the disadvantage that as the number of devices connected increases, the time required for the above devices increases, and in order to reduce the time required, the number of devices connected to the common bus is limited. There was a drawback. The present invention is capable of controlling the stoppage of clock pulses from the device to the common bus line only when a data transmission request is received from the device connected to the common bus line, and creating a data transmission interval. As a result, the data transfer time allocated to devices that do not have data transmission requests is shortened, and the above-mentioned drawbacks are solved by time-sharing, which allows the length of transmission data to be set arbitrarily by devices that have transmission requests. This provides a data transfer control method.

The time-division data transfer control system of the present invention includes a common bus that connects a plurality of devices, a clock pulse stop control line added to the common bus, and a clock pulse that is common to the plurality of devices. and a circuit for sending out the
A counting circuit that inputs a signal line that takes in clock pulses supplied to a common bus line and a signal line that takes in a clock pulse stop signal from a clock pulse stop control line through a gate circuit, and an output of the counting circuit and a predetermined value. a coincidence control circuit that compares the output of the coincidence control circuit and outputs an output when the two match, and a control signal that takes the logic between the output of the coincidence control circuit and the data transmission request signal and stops the clock pulse when there is a data transmission request. A clock pulse stop signal from a device requesting data transmission is supplied from the clock pulse stop control line to all devices connected to the common bus line, and the clock pulse stop signal from the device requesting data transmission is supplied to each device. After stopping the counting circuit, data is transferred via the common bus line, and further, at the end of the data transfer, the sending of the clock pulse stop signal is stopped to restart counting in the counting circuit of each device, thereby achieving the above-described method. Each device operates autonomously and transfers data between the devices.

Next, embodiments of the present invention will be described with reference to the drawings.
FIG. 3 is a block diagram showing an embodiment of the present invention, which includes a data transfer common bus 2, which is connected to the common bus 2, counts clock pulses, and sends data to the common bus at an allocated time. devices 21 to 23 including a circuit for controlling whether or not there is a request to send data, and a control circuit for stopping the common clock pulse and sending data on the common bus when there is a request to send data; and a common clock on the common bus. It is composed of a pulse generation circuit 13. Referring to FIG. 4, there is shown a specific block circuit diagram of one device of the embodiment shown in FIG. A step-by-step explanation will be given below. First, the clock pulse and clock pulse stop signal supplied to the common bus 2 are taken in through the signal line 3 and the clock pulse stop signal line 4, and the output of the counting circuit 5 is input to the coincidence control circuit 6 through the gate circuit 11. The coincidence control circuit 6 outputs an output when the value matches a predetermined value, that is, the corresponding time of the device. On the other hand, the sending request register 1 in the transfer unit 9 in the data transfer control unit 9
If 0 is set and a data transfer request is made, a clock pulse stop signal is sent to the common bus line 2 from the clock pulse stop control line 7 through the gate circuit 12. This control signal is sent through the common bus 2 to all devices connected to the common bus 2, closes the gate circuit 11 via the clock pulse stop signal line 4, and stops the counting circuit 5. Thereafter, data is sent to the common bus 2 by the data transfer control section 9. At the end of data transmission, the data transfer control unit 9 resets the transmission request register 10.
As a result of this reset, the clock pulse stop signal disappears from the clock pulse stop control line 7, and the counting circuit 5 of each device starts counting again. Next, referring to the time chart in FIG.
When the clock pulse stop control signal reaches the sending time 42, a clock pulse stop control signal is sent to stop the counting circuits of all devices connected to the common bus.

At the time 43 when the data transfer is completed, the clock pulse stop signal is reset, and the counting circuit starts counting again 44.
Ru. The same applies to the device 23. As explained above, according to the present invention, the time allotted for data transfer, which was conventionally given to all devices 42-43, is reduced by 44-45, thereby reducing waiting time. It became possible to remove the limit on the number of devices connected to a common bus.

As explained above, the present invention can shorten the gate time allocated to devices that do not have data transfer requests by adding a clock pulse stop control line for common bus synchronization, and reduce the time available for each of the devices. At the same time, restrictions on the number of devices that can be connected to a common bus can be removed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional embodiment (shown in a block diagram), Fig. 2 is a time chart of the embodiment shown in Fig. 1,
Fig. 3 is a circuit diagram showing an embodiment of the present invention as a block diagram, Fig. 4 is a circuit diagram partially showing the embodiment shown in Fig. 3, and Fig. 5 is a circuit diagram showing a part of the embodiment shown in Fig. 3. It is a time chart of an example. 1...Common bus bar in conventional embodiment, 2...
・Common bus bar in one embodiment of the present invention, 3...
Clock pulse signal line, 4... Clock pulse stop signal line, 5... Counting circuit, 6...
Coincidence control circuit, 7... Clock pulse stop control line,
8...Data line, 9...Data transfer control line, 10...Send request register, 11, 12...
... Gate circuit, 13... Clock pulse generation circuit, 31, 32, 3n... Devices connected to the common bus in the conventional embodiment, 21, 22, 23...
- Devices D3l, D3 connected to the common bus in one embodiment of the present invention.

Claims (1)

[Claims] 1 one common bus connecting multiple devices,
a clock pulse stop control line attached to the common bus;
A circuit that sends out a common clock pulse to the plurality of devices, a signal line that takes in the clock pulse supplied to the common bus, and a signal line that takes in the clock pulse stop signal from the clock pulse stop control line are input through the gate circuit. a counting circuit; a coincidence control circuit that compares the output of the counting circuit with a predetermined value and outputs an output when the two match; and when there is a data transmission request, the output of the coincidence control circuit and the data transmission request. Each device is equipped with a means for transmitting a control signal for stopping the clock pulse by performing logic with the signal, and transmitting the clock pulse stop signal from the device requesting data transmission to all devices connected to the common bus. After supplying clock pulses to the devices from the said clock pulse stop control line to stop the counting circuits of each device, data is transferred via the common bus line, and furthermore, when the data transfer is completed, sending out the clock pulse stop signal is stopped. 1. A time-division data transfer control system, characterized in that each device operates autonomously and transfers data between the devices by restarting the counting circuit of each device.